[ar71xx] reorganize PCI code

[openwrt.git] / target / linux / brcm63xx / files / include / asm-mips / mach-bcm63xx / bcm63xx_cpu.h

diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
index 2ad2c9d..58ed270 100644 (file)
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
@@ -121,20 +121,32 @@ enum bcm63xx_regs_set {
  * 6338 register sets base address
  */
 
  * 6338 register sets base address
  */
 

+#define BCM_6338_DSL_LMEM_BASE         (0xfff00000)

 #define BCM_6338_PERF_BASE             (0xfffe0000)
 #define BCM_6338_PERF_BASE             (0xfffe0000)

-#define BCM_6338_BB_BASE               (0xfffe0100) /* bus bridge registers */
+#define BCM_6338_BB_BASE               (0xfffe0100)

 #define BCM_6338_TIMER_BASE            (0xfffe0200)
 #define BCM_6338_WDT_BASE              (0xfffe021c)
 #define BCM_6338_UART0_BASE            (0xfffe0300)
 #define BCM_6338_GPIO_BASE             (0xfffe0400)
 #define BCM_6338_SPI_BASE              (0xfffe0c00)
 #define BCM_6338_TIMER_BASE            (0xfffe0200)
 #define BCM_6338_WDT_BASE              (0xfffe021c)
 #define BCM_6338_UART0_BASE            (0xfffe0300)
 #define BCM_6338_GPIO_BASE             (0xfffe0400)
 #define BCM_6338_SPI_BASE              (0xfffe0c00)

+#define BCM_6338_UDC0_BASE             (0xdeadbeef)
+#define BCM_6338_USBDMA_BASE           (0xfffe2400)
+#define BCM_6338_OHCI0_BASE            (0xdeadbeef)
+#define BCM_6338_OHCI_PRIV_BASE                (0xfffe3000)
+#define BCM_6338_USBH_PRIV_BASE                (0xdeadbeef)
+#define BCM_6338_MPI_BASE              (0xfffe3160)
+#define BCM_6338_PCMCIA_BASE           (0xdeadbeef)
+#define BCM_6338_SDRAM_REGS_BASE       (0xfffe3100)

 #define BCM_6338_DSL_BASE              (0xfffe1000)
 #define BCM_6338_SAR_BASE              (0xfffe2000)
 #define BCM_6338_DSL_BASE              (0xfffe1000)
 #define BCM_6338_SAR_BASE              (0xfffe2000)

-#define BCM_6338_ENETDMA_BASE          (0xfffe2400)
-#define BCM_6338_USBDMA_BASE           (0xfffe2400)
+#define BCM_6338_UBUS_BASE             (0xdeadbeef)

 #define BCM_6338_ENET0_BASE            (0xfffe2800)
 #define BCM_6338_ENET0_BASE            (0xfffe2800)

-#define BCM_6338_UDC0_BASE             (0xfffe3000) /* USB_CTL_BASE */
-#define BCM_6338_MEMC_BASE             (0xfffe3100)
+#define BCM_6338_ENET1_BASE            (0xdeadbeef)
+#define BCM_6338_ENETDMA_BASE          (0xfffe2400)
+#define BCM_6338_EHCI0_BASE            (0xdeadbeef)
+#define BCM_6338_SDRAM_BASE            (0xfffe3100)
+#define BCM_6338_MEMC_BASE             (0xdeadbeef)
+#define BCM_6338_DDR_BASE              (0xdeadbeef)

 
 /*
  * 6345 register sets base address
 
 /*
  * 6345 register sets base address


@@ -211,6 +223,8 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 #else
 #ifdef CONFIG_BCM63XX_CPU_6338
        switch (set) {
 #else
 #ifdef CONFIG_BCM63XX_CPU_6338
        switch (set) {

+       case RSET_DSL_LMEM:
+               return BCM_6338_DSL_LMEM_BASE;

        case RSET_PERF:
                return BCM_6338_PERF_BASE;
        case RSET_TIMER:
        case RSET_PERF:
                return BCM_6338_PERF_BASE;
        case RSET_TIMER:


@@ -223,8 +237,34 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
                return BCM_6338_GPIO_BASE;
        case RSET_SPI:
                return BCM_6338_SPI_BASE;
                return BCM_6338_GPIO_BASE;
        case RSET_SPI:
                return BCM_6338_SPI_BASE;

+       case RSET_UDC0:
+               return BCM_6338_UDC0_BASE;
+       case RSET_OHCI0:
+               return BCM_6338_OHCI0_BASE;
+       case RSET_OHCI_PRIV:
+               return BCM_6338_OHCI_PRIV_BASE;
+       case RSET_USBH_PRIV:
+               return BCM_6338_USBH_PRIV_BASE;
+       case RSET_MPI:
+               return BCM_6338_MPI_BASE;
+       case RSET_PCMCIA:
+               return BCM_6338_PCMCIA_BASE;
+       case RSET_DSL:
+               return BCM_6338_DSL_BASE;
+       case RSET_ENET0:
+               return BCM_6338_ENET0_BASE;
+       case RSET_ENET1:
+               return BCM_6338_ENET1_BASE;
+       case RSET_ENETDMA:
+               return BCM_6338_ENETDMA_BASE;
+       case RSET_EHCI0:
+               return BCM_6338_EHCI0_BASE;
+       case RSET_SDRAM:
+               return BCM_6338_SDRAM_BASE;

        case RSET_MEMC:
                return BCM_6338_MEMC_BASE;
        case RSET_MEMC:
                return BCM_6338_MEMC_BASE;

+       case RSET_DDR:
+               return BCM_6338_DDR_BASE;

        }
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6345
        }
 #endif
 #ifdef CONFIG_BCM63XX_CPU_6345