* 6338 register sets base address
*/
+#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
#define BCM_6338_PERF_BASE (0xfffe0000)
#define BCM_6338_BB_BASE (0xfffe0100) /* bus bridge registers */
#define BCM_6338_TIMER_BASE (0xfffe0200)
#define BCM_6338_USBDMA_BASE (0xfffe2400)
#define BCM_6338_ENET0_BASE (0xfffe2800)
#define BCM_6338_UDC0_BASE (0xfffe3000) /* USB_CTL_BASE */
-#define BCM_6338_MEMC_BASE (0xfffe3100)
+#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
+#define BCM_6338_SDRAM_BASE (0xfffe3100)
+#define BCM_6338_MEMC_BASE (0xdeadbeef)
/*
* 6345 register sets base address
#else
#ifdef CONFIG_BCM63XX_CPU_6338
switch (set) {
+ case RSET_DSL_LMEM:
+ return BCM_6338_DSL_LMEM_BASE;
case RSET_PERF:
return BCM_6338_PERF_BASE;
case RSET_TIMER:
return BCM_6338_SPI_BASE;
case RSET_MEMC:
return BCM_6338_MEMC_BASE;
+ case RSET_SDRAM:
+ return BCM_6338_SDRAM_BASE;
}
#endif
#ifdef CONFIG_BCM63XX_CPU_6345