ar71xx: add AR934X specific bootstrap and reset register bits

[openwrt.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index f78ae16..99f3497 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -72,6 +72,8 @@
 
 #define AR933X_UART_BASE       (AR71XX_APB_BASE + 0x00020000)
 #define AR933X_UART_SIZE       0x14
+#define AR933X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE       0x04
 #define AR933X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
 #define AR933X_WMAC_SIZE       0x20000
 
@@ -210,6 +212,7 @@ extern enum ar71xx_soc_type ar71xx_soc;
 #define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK     0x7
 
 #define AR934X_PLL_REG_CPU_CONFIG      0x00
+#define AR934X_PLL_REG_DDR_CONFIG      0x04
 #define AR934X_PLL_REG_DDR_CTRL_CLOCK  0x8
 
 #define AR934X_CPU_PLL_CFG_OUTDIV_MSB  21
@@ -370,6 +373,13 @@ extern enum ar71xx_soc_type ar71xx_soc;
 
 #define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET       1
 
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS         BIT(2)
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS         BIT(3)
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS         BIT(4)
+#define AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL     BIT(20)
+#define AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL     BIT(21)
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL     BIT(24)
+
 extern void __iomem *ar71xx_pll_base;
 
 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
@@ -614,8 +624,21 @@ void ar71xx_ddr_flush(u32 reg);
 
 #define AR934X_RESET_REG_RESET_MODULE          0x1c
 #define AR934X_RESET_REG_BOOTSTRAP             0xb0
-/* 0 - 25MHz   1 - 40 MHz */
-#define AR934X_REF_CLK_40                      (1 << 4)
+#define AR934X_BOOTSTRAP_SW_OPTION8            BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7            BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6            BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5            BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4            BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3            BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2            BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1            BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE       BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC               BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE            BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40            BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI         BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED                BIT(1)
+#define AR934X_BOOTSTRAP_DDR1                  BIT(0)
 
 #define WDOG_CTRL_LAST_RESET           BIT(31)
 #define WDOG_CTRL_ACTION_MASK          3
@@ -678,6 +701,42 @@ void ar71xx_ddr_flush(u32 reg);
 #define AR933X_RESET_GE0_MDIO          BIT(22)
 #define AR933X_RESET_GE1_MAC           BIT(13)
 #define AR933X_RESET_GE0_MAC           BIT(9)
+#define AR933X_RESET_USB_HOST          BIT(5)
+#define AR933X_RESET_USB_PHY           BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE   BIT(3)
+
+#define AR934X_RESET_HOST              BIT(31)
+#define AR934X_RESET_SLIC              BIT(30)
+#define AR934X_RESET_HDMA              BIT(29)
+#define AR934X_RESET_EXTERNAL          BIT(28)
+#define AR934X_RESET_RTC               BIT(27)
+#define AR934X_RESET_PCIE_EP_INT       BIT(26)
+#define AR934X_RESET_CHKSUM_ACC                BIT(25)
+#define AR934X_RESET_FULL_CHIP         BIT(24)
+#define AR934X_RESET_GE1_MDIO          BIT(23)
+#define AR934X_RESET_GE0_MDIO          BIT(22)
+#define AR934X_RESET_CPU_NMI           BIT(21)
+#define AR934X_RESET_CPU_COLD          BIT(20)
+#define AR934X_RESET_HOST_RESET_INT    BIT(19)
+#define AR934X_RESET_PCIE_EP           BIT(18)
+#define AR934X_RESET_UART1             BIT(17)
+#define AR934X_RESET_DDR               BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define AR934X_RESET_NANDF             BIT(14)
+#define AR934X_RESET_GE1_MAC           BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
+#define AR934X_RESET_USB_PHY_ANALOG    BIT(11)
+#define AR934X_RESET_HOST_DMA_INT      BIT(10)
+#define AR934X_RESET_GE0_MAC           BIT(9)
+#define AR934X_RESET_ETH_SIWTCH                BIT(8)
+#define AR934X_RESET_PCIE_PHY          BIT(7)
+#define AR934X_RESET_PCIE              BIT(6)
+#define AR934X_RESET_USB_HOST          BIT(5)
+#define AR934X_RESET_USB_PHY           BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE   BIT(3)
+#define AR934X_RESET_LUT               BIT(2)
+#define AR934X_RESET_MBOX              BIT(1)
+#define AR934X_RESET_I2S               BIT(0)
 
 #define REV_ID_MAJOR_MASK      0xfff0
 #define REV_ID_MAJOR_AR71XX    0x00a0
@@ -724,6 +783,7 @@ static inline u32 ar71xx_reset_rr(unsigned reg)
 
 void ar71xx_device_stop(u32 mask);
 void ar71xx_device_start(u32 mask);
+void ar71xx_device_reset_rmw(u32 clear, u32 set);
 int ar71xx_device_stopped(u32 mask);
 
 /*
@@ -764,6 +824,23 @@ void ar71xx_flash_release(void);
 #define MII1_CTRL_IF_RGMII     0
 #define MII1_CTRL_IF_RMII      1
 
+/*
+ * AR933X GMAC
+ */
+#define AR933X_GMAC_REG_ETH_CFG                0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0       BIT(0)
+#define AR933X_ETH_CFG_MII_GE0         BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0                BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER  BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE   BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN  BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP     BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP        BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0                BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100        BIT(10)
+
 #endif /* __ASSEMBLER__ */
 
 #endif /* __ASM_MACH_AR71XX_H */