[brcm63xx] add infrastructure to register gpio-input reset button

[openwrt.git] / target / linux / brcm63xx / files / arch / mips / bcm63xx / cpu.c

diff --git a/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c b/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
index 362d109..00da282 100644 (file)
--- a/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
+++ b/target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c
@@ -34,19 +34,34 @@ static unsigned int bcm63xx_memory_size;
  */
 
 static const unsigned long bcm96338_regs_base[] = {
  */
 
 static const unsigned long bcm96338_regs_base[] = {

+       [RSET_DSL_LMEM]         = BCM_6338_DSL_LMEM_BASE,

        [RSET_PERF]             = BCM_6338_PERF_BASE,
        [RSET_TIMER]            = BCM_6338_TIMER_BASE,
        [RSET_WDT]              = BCM_6338_WDT_BASE,
        [RSET_UART0]            = BCM_6338_UART0_BASE,
        [RSET_GPIO]             = BCM_6338_GPIO_BASE,
        [RSET_SPI]              = BCM_6338_SPI_BASE,
        [RSET_PERF]             = BCM_6338_PERF_BASE,
        [RSET_TIMER]            = BCM_6338_TIMER_BASE,
        [RSET_WDT]              = BCM_6338_WDT_BASE,
        [RSET_UART0]            = BCM_6338_UART0_BASE,
        [RSET_GPIO]             = BCM_6338_GPIO_BASE,
        [RSET_SPI]              = BCM_6338_SPI_BASE,

+       [RSET_OHCI0]            = BCM_6338_OHCI0_BASE,
+       [RSET_OHCI_PRIV]        = BCM_6338_OHCI_PRIV_BASE,
+       [RSET_USBH_PRIV]        = BCM_6338_USBH_PRIV_BASE,
+       [RSET_UDC0]             = BCM_6338_UDC0_BASE,
+       [RSET_MPI]              = BCM_6338_MPI_BASE,
+       [RSET_PCMCIA]           = BCM_6338_PCMCIA_BASE,
+       [RSET_SDRAM]            = BCM_6338_SDRAM_BASE,
+       [RSET_DSL]              = BCM_6338_DSL_BASE,
+       [RSET_ENET0]            = BCM_6338_ENET0_BASE,
+       [RSET_ENET1]            = BCM_6338_ENET1_BASE,
+       [RSET_ENETDMA]          = BCM_6338_ENETDMA_BASE,

        [RSET_MEMC]             = BCM_6338_MEMC_BASE,
        [RSET_MEMC]             = BCM_6338_MEMC_BASE,

+       [RSET_DDR]              = BCM_6338_DDR_BASE,

 };
 
 static const int bcm96338_irqs[] = {
        [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
 };
 
 static const int bcm96338_irqs[] = {
        [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,

+       [IRQ_SPI]               = BCM_6338_SPI_IRQ,

        [IRQ_UART0]             = BCM_6338_UART0_IRQ,
        [IRQ_DSL]               = BCM_6338_DSL_IRQ,
        [IRQ_UART0]             = BCM_6338_UART0_IRQ,
        [IRQ_DSL]               = BCM_6338_DSL_IRQ,

+       [IRQ_UDC0]              = BCM_6338_UDC0_IRQ,

        [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
        [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
        [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
        [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
        [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
        [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,


@@ -68,6 +83,45 @@ static const unsigned long bcm96338_regs_spi[] = {
        [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
 };
 
        [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
 };
 

+/*
+ * 6345 register sets and irqs
+ */
+
+static const unsigned long bcm96345_regs_base[] = {
+       [RSET_DSL_LMEM]         = BCM_6345_DSL_LMEM_BASE,
+       [RSET_PERF]             = BCM_6345_PERF_BASE,
+       [RSET_TIMER]            = BCM_6345_TIMER_BASE,
+       [RSET_WDT]              = BCM_6345_WDT_BASE,
+       [RSET_UART0]            = BCM_6345_UART0_BASE,
+       [RSET_GPIO]             = BCM_6345_GPIO_BASE,
+       [RSET_SPI]              = BCM_6345_SPI_BASE,
+       [RSET_UDC0]             = BCM_6345_UDC0_BASE,
+       [RSET_OHCI0]            = BCM_6345_OHCI0_BASE,
+       [RSET_OHCI_PRIV]        = BCM_6345_OHCI_PRIV_BASE,
+       [RSET_USBH_PRIV]        = BCM_6345_USBH_PRIV_BASE,
+       [RSET_MPI]              = BCM_6345_MPI_BASE,
+       [RSET_PCMCIA]           = BCM_6345_PCMCIA_BASE,
+       [RSET_DSL]              = BCM_6345_DSL_BASE,
+       [RSET_ENET0]            = BCM_6345_ENET0_BASE,
+       [RSET_ENET1]            = BCM_6345_ENET1_BASE,
+       [RSET_ENETDMA]          = BCM_6345_ENETDMA_BASE,
+       [RSET_EHCI0]            = BCM_6345_EHCI0_BASE,
+       [RSET_SDRAM]            = BCM_6345_SDRAM_BASE,
+       [RSET_MEMC]             = BCM_6345_MEMC_BASE,
+       [RSET_DDR]              = BCM_6345_DDR_BASE,
+};
+
+static const int bcm96345_irqs[] = {
+       [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
+       [IRQ_UART0]             = BCM_6345_UART0_IRQ,
+       [IRQ_DSL]               = BCM_6345_DSL_IRQ,
+       [IRQ_UDC0]              = BCM_6345_UDC0_IRQ,
+       [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
+       [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,
+       [IRQ_ENET0_RXDMA]       = BCM_6345_ENET0_RXDMA_IRQ,
+       [IRQ_ENET0_TXDMA]       = BCM_6345_ENET0_TXDMA_IRQ,
+};
+

 /*
  * 6348 register sets and irqs
  */
 /*
  * 6348 register sets and irqs
  */


@@ -82,6 +136,7 @@ static const unsigned long bcm96348_regs_base[] = {
        [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
        [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
        [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
        [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
        [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
        [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,

+       [RSET_UDC0]             = BCM_6348_UDC0_BASE,

        [RSET_MPI]              = BCM_6348_MPI_BASE,
        [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
        [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
        [RSET_MPI]              = BCM_6348_MPI_BASE,
        [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
        [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,


@@ -95,8 +150,10 @@ static const unsigned long bcm96348_regs_base[] = {
 
 static const int bcm96348_irqs[] = {
        [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
 
 static const int bcm96348_irqs[] = {
        [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,

+       [IRQ_SPI]               = BCM_6348_SPI_IRQ,

        [IRQ_UART0]             = BCM_6348_UART0_IRQ,
        [IRQ_DSL]               = BCM_6348_DSL_IRQ,
        [IRQ_UART0]             = BCM_6348_UART0_IRQ,
        [IRQ_DSL]               = BCM_6348_DSL_IRQ,

+       [IRQ_UDC0]              = BCM_6348_UDC0_IRQ,

        [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
        [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
        [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
        [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
        [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
        [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,


@@ -152,6 +209,7 @@ static const unsigned long bcm96358_regs_base[] = {
 
 static const int bcm96358_irqs[] = {
        [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
 
 static const int bcm96358_irqs[] = {
        [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,

+       [IRQ_SPI]               = BCM_6358_SPI_IRQ,

        [IRQ_UART0]             = BCM_6358_UART0_IRQ,
        [IRQ_DSL]               = BCM_6358_DSL_IRQ,
        [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
        [IRQ_UART0]             = BCM_6358_UART0_IRQ,
        [IRQ_DSL]               = BCM_6358_DSL_IRQ,
        [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,


@@ -210,9 +268,11 @@ static unsigned int detect_cpu_clock(void)
 {
        unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
 
 {
        unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
 

-       if (BCMCPU_IS_6338()) {
+       if (BCMCPU_IS_6338())

                return 240000000;
                return 240000000;

-       }
+
+       if (BCMCPU_IS_6345())
+               return 140000000;

 
        /*
         * frequency depends on PLL configuration:
 
        /*
         * frequency depends on PLL configuration:


@@ -247,6 +307,9 @@ static unsigned int detect_memory_size(void)
        unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
        u32 val;
 
        unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
        u32 val;
 

+       if (BCMCPU_IS_6345())
+               return (8 * 1024 * 1024);
+

        if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
                val = bcm_sdram_readl(SDRAM_CFG_REG);
                rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
        if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
                val = bcm_sdram_readl(SDRAM_CFG_REG);
                rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;


@@ -281,12 +344,17 @@ void __init bcm63xx_cpu_init(void)
        expected_cpu_id = 0;
 
        switch (c->cputype) {
        expected_cpu_id = 0;
 
        switch (c->cputype) {

-       case CPU_BCM6338:
+       case CPU_BCM3302:

                expected_cpu_id = BCM6338_CPU_ID;
                bcm63xx_regs_base = bcm96338_regs_base;
                bcm63xx_irqs = bcm96338_irqs;
                bcm63xx_regs_spi = bcm96338_regs_spi;
                break;
                expected_cpu_id = BCM6338_CPU_ID;
                bcm63xx_regs_base = bcm96338_regs_base;
                bcm63xx_irqs = bcm96338_irqs;
                bcm63xx_regs_spi = bcm96338_regs_spi;
                break;

+       case CPU_BCM6345:
+               expected_cpu_id = BCM6345_CPU_ID;
+               bcm63xx_regs_base = bcm96345_regs_base;
+               bcm63xx_irqs = bcm96345_irqs;
+               break;

        case CPU_BCM6348:
                expected_cpu_id = BCM6348_CPU_ID;
                bcm63xx_regs_base = bcm96348_regs_base;
        case CPU_BCM6348:
                expected_cpu_id = BCM6348_CPU_ID;
                bcm63xx_regs_base = bcm96348_regs_base;