fix vlynq initialization (closes: #2135)

[openwrt.git] / target / linux / ar7-2.6 / files / arch / mips / ar7 / setup.c

diff --git a/target/linux/ar7-2.6/files/arch/mips/ar7/setup.c b/target/linux/ar7-2.6/files/arch/mips/ar7/setup.c
index 7930e90..4abc39f 100644 (file)
--- a/target/linux/ar7-2.6/files/arch/mips/ar7/setup.c
+++ b/target/linux/ar7-2.6/files/arch/mips/ar7/setup.c
@@ -109,12 +109,16 @@ void __init plat_mem_setup(void)
        set_io_port_base(io_base);
 
        prom_meminit();
+#warning FIXME: clock initialisation
        ar7_init_clocks();
 
        ioport_resource.start = 0;
        ioport_resource.end   = ~0;
        iomem_resource.start  = 0;
        iomem_resource.end    = ~0;
+
+       printk("%s, ID: 0x%04x, Revision: 0x%02x\n", get_system_type(), 
+               ar7_chip_id(), ar7_chip_rev());
 }
 
 console_initcall(ar7_init_console);