#define SW_BASE KSEG1ADDR(0x12000000)
#define SW_DEVS 6
-#define SW_IRQ 9
#define ETH_TX_TIMEOUT HZ/4
#define ETH_FCS 4;
u32 status;
} __attribute__ ((packed));
-#define ADM5120_DMA_MASK 0x00ffffff
+#define ADM5120_DMA_MASK 0x01ffffff
#define ADM5120_DMA_OWN 0x80000000 /* buffer owner */
#define ADM5120_DMA_RINGEND 0x10000000 /* Last in DMA ring */