---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -928,6 +928,36 @@ static void __cpuinit probe_pcache(void)
- c->dcache.waybit = 0;
- break;
-
-+ case CPU_JZRISC:
-+ config1 = read_c0_config1();
-+ config1 = (config1 >> 22) & 0x07;
-+ if (config1 == 0x07)
-+ config1 = 10;
-+ else
-+ config1 = config1 + 11;
-+ config1 += 2;
-+ icache_size = (1 << config1);
-+ c->icache.linesz = 32;
-+ c->icache.ways = 4;
-+ c->icache.waybit = __ffs(icache_size / c->icache.ways);
-+
-+ config1 = read_c0_config1();
-+ config1 = (config1 >> 13) & 0x07;
-+ if (config1 == 0x07)
-+ config1 = 10;
-+ else
-+ config1 = config1 + 11;
-+ config1 += 2;
-+ dcache_size = (1 << config1);
-+ c->dcache.linesz = 32;
-+ c->dcache.ways = 4;
-+ c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
-+
-+ c->dcache.flags = 0;
-+ c->options |= MIPS_CPU_PREFETCH;
-+
-+ break;
-+
- default:
- if (!(config & MIPS_CONF_M))
- panic("Don't know how to probe P-caches on this cpu.");
---- a/arch/mips/mm/cache.c
-+++ b/arch/mips/mm/cache.c
-@@ -52,6 +52,8 @@ void (*_dma_cache_wback)(unsigned long s
- void (*_dma_cache_inv)(unsigned long start, unsigned long size);
-
- EXPORT_SYMBOL(_dma_cache_wback_inv);
-+EXPORT_SYMBOL(_dma_cache_wback);
-+EXPORT_SYMBOL(_dma_cache_inv);
-
- #endif /* CONFIG_DMA_NONCOHERENT */
-