brcm47xx-2.6: reset the pci core at boot time (see #464)

[openwrt.git] / target / linux / brcm47xx-2.6 / files / drivers / ssb / driver_mips / mips.c

diff --git a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_mips/mips.c b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_mips/mips.c
index c6aaeed..7b3880a 100644 (file)
--- a/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_mips/mips.c
+++ b/target/linux/brcm47xx-2.6/files/drivers/ssb/driver_mips/mips.c
@@ -165,12 +165,16 @@ static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
 {
        struct ssb_bus *bus = mcore->dev->bus;
 
 {
        struct ssb_bus *bus = mcore->dev->bus;
 

+       mcore->flash_buswidth = 2;

        if (bus->chipco.dev) {
                mcore->flash_window = 0x1c000000;
        if (bus->chipco.dev) {
                mcore->flash_window = 0x1c000000;

-               mcore->flash_window_size = 0x800000;
+               mcore->flash_window_size = 0x02000000;
+               if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
+                               & SSB_CHIPCO_CFG_DS16) == 0)
+                       mcore->flash_buswidth = 1;

        } else {
                mcore->flash_window = 0x1fc00000;
        } else {
                mcore->flash_window = 0x1fc00000;

-               mcore->flash_window_size = 0x400000;
+               mcore->flash_window_size = 0x00400000;

        }
 }
 
        }
 }
 


@@ -211,15 +215,14 @@ u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
        if (bus->extif.dev) {
                ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
        } else if (bus->chipco.dev) {
        if (bus->extif.dev) {
                ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
        } else if (bus->chipco.dev) {

-               if (bus->chip_id == 0x5365)
-                       /* FIXME: is this override really necessary? */
-                       return 200000000;
-
-               ssb_chipco_get_clockcontrol(&bus->chipco, &pll_type, &n, &m);
+               ssb_chipco_get_clockcpu(&bus->chipco, bus->chip_id, &rate,
+                       &pll_type, &n, &m);

        } else
                return 0;
 
        } else
                return 0;
 

-       rate = ssb_calc_clock_rate(pll_type, n, m);
+       if (rate == 0)
+               rate = ssb_calc_clock_rate(pll_type, n, m);
+

        if (pll_type == SSB_PLLTYPE_6)
                rate *= 2;
 
        if (pll_type == SSB_PLLTYPE_6)
                rate *= 2;