+/*
+ * Ralink RT288x SoC PCI register definitions
+ *
+ * Copyright (C) 2009 John Crispin <blogic@openwrt.org>
+ * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/init.h>
#include <asm/mach-ralink/rt288x.h>
-
-#define RT2880_PCI_SLOT1_BASE 0x20000000
-#define RALINK_PCI_BASE 0xA0440000
-#define RT2880_PCI_PCICFG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0000))
-#define RT2880_PCI_ARBCTL ((unsigned long*)(RALINK_PCI_BASE + 0x0080))
-#define RT2880_PCI_BAR0SETUP_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0010))
-#define RT2880_PCI_CONFIG_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0020))
-#define RT2880_PCI_CONFIG_DATA ((unsigned long*)(RALINK_PCI_BASE + 0x0024))
-#define RT2880_PCI_MEMBASE ((unsigned long*)(RALINK_PCI_BASE + 0x0028))
-#define RT2880_PCI_IOBASE ((unsigned long*)(RALINK_PCI_BASE + 0x002C))
-#define RT2880_PCI_IMBASEBAR0_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x0018))
-#define RT2880_PCI_ID ((unsigned long*)(RALINK_PCI_BASE + 0x0030))
-#define RT2880_PCI_CLASS ((unsigned long*)(RALINK_PCI_BASE + 0x0034))
-#define RT2880_PCI_SUBID ((unsigned long*)(RALINK_PCI_BASE + 0x0038))
-#define RT2880_PCI_PCIMSK_ADDR ((unsigned long*)(RALINK_PCI_BASE + 0x000C))
+#include <asm/mach-ralink/rt288x_regs.h>
+
+#define RT2880_PCI_MEM_BASE 0x20000000
+#define RT2880_PCI_MEM_SIZE 0x10000000
+#define RT2880_PCI_IO_BASE 0x00460000
+#define RT2880_PCI_IO_SIZE 0x00010000
+
+#define RT2880_PCI_REG_PCICFG_ADDR 0x00
+#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
+#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
+#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
+#define RT2880_PCI_REG_CONFIG_ADDR 0x20
+#define RT2880_PCI_REG_CONFIG_DATA 0x24
+#define RT2880_PCI_REG_MEMBASE 0x28
+#define RT2880_PCI_REG_IOBASE 0x2c
+#define RT2880_PCI_REG_ID 0x30
+#define RT2880_PCI_REG_CLASS 0x34
+#define RT2880_PCI_REG_SUBID 0x38
+#define RT2880_PCI_REG_ARBCTL 0x80
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
-static int config_access(unsigned char access_type, struct pci_bus *bus,
- unsigned int devfn, unsigned char where, u32 *data)
+static void __iomem *rt2880_pci_base;
+static DEFINE_SPINLOCK(rt2880_pci_lock);
+
+static u32 rt2880_pci_reg_read(u32 reg)
+{
+ return readl(rt2880_pci_base + reg);
+}
+
+static void rt2880_pci_reg_write(u32 val, u32 reg)
+{
+ writel(val, rt2880_pci_base + reg);
+}
+
+static void config_access(unsigned char access_type, struct pci_bus *bus,
+ unsigned int devfn, unsigned char where, u32 *data)
{
unsigned int slot = PCI_SLOT(devfn);
unsigned int address;
address = (bus->number << 16) | (slot << 11) | (func << 8) |
(where & 0xfc) | 0x80000000;
- writel(address, RT2880_PCI_CONFIG_ADDR);
+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
if (access_type == PCI_ACCESS_WRITE)
- writel(*data, RT2880_PCI_CONFIG_DATA);
+ rt2880_pci_reg_write(*data, RT2880_PCI_REG_CONFIG_DATA);
else
- *data = readl(RT2880_PCI_CONFIG_DATA);
-
- return 0;
+ *data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
}
static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
+ unsigned long flags;
u32 data = 0;
- if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
- return PCIBIOS_DEVICE_NOT_FOUND;
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
+ config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
if (size == 1)
*val = (data >> ((where & 3) << 3)) & 0xff;
static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
+ unsigned long flags;
u32 data = 0;
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
if (size == 4) {
data = val;
} else {
- if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
- return PCIBIOS_DEVICE_NOT_FOUND;
+ config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
if (size == 1)
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
(val << ((where & 3) << 3));
}
- if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
- return PCIBIOS_DEVICE_NOT_FOUND;
+ config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data);
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
return PCIBIOS_SUCCESSFUL;
}
static struct resource rt2880_pci_io_resource = {
.name = "PCI MEM space",
- .start = 0x20000000,
- .end = 0x2FFFFFFF,
+ .start = RT2880_PCI_MEM_BASE,
+ .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
.flags = IORESOURCE_MEM,
};
static struct resource rt2880_pci_mem_resource = {
.name = "PCI IO space",
- .start = 0x00460000,
- .end = 0x0046FFFF,
+ .start = RT2880_PCI_IO_BASE,
+ .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
.flags = IORESOURCE_IO,
};
.io_resource = &rt2880_pci_mem_resource,
};
-void inline read_config(unsigned long bus, unsigned long dev,
- unsigned long func, unsigned long reg,
- unsigned long *val)
+static inline void read_config(unsigned long bus, unsigned long dev,
+ unsigned long func, unsigned long reg,
+ unsigned long *val)
{
unsigned long address;
+ unsigned long flags;
address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
0x80000000;
- writel(address, RT2880_PCI_CONFIG_ADDR);
- *val = readl(RT2880_PCI_CONFIG_DATA);
+
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
+ *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
}
-void inline write_config(unsigned long bus, unsigned long dev,
- unsigned long func, unsigned long reg,
- unsigned long val)
+static inline void write_config(unsigned long bus, unsigned long dev,
+ unsigned long func, unsigned long reg,
+ unsigned long val)
{
unsigned long address;
+ unsigned long flags;
address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
0x80000000;
- writel(address, RT2880_PCI_CONFIG_ADDR);
- writel(val, RT2880_PCI_CONFIG_DATA);
+
+ spin_lock_irqsave(&rt2880_pci_lock, flags);
+ rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
+ rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
+ spin_unlock_irqrestore(&rt2880_pci_lock, flags);
}
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
unsigned long val = 0;
int i;
- writel(0, RT2880_PCI_PCICFG_ADDR);
+ rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
+
+ rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
for(i = 0; i < 0xfffff; i++) {}
- writel(0x79, RT2880_PCI_ARBCTL);
- writel(0x07FF0001, RT2880_PCI_BAR0SETUP_ADDR);
- writel(RT2880_PCI_SLOT1_BASE, RT2880_PCI_MEMBASE);
- writel(0x00460000, RT2880_PCI_IOBASE);
- writel(0x08000000, RT2880_PCI_IMBASEBAR0_ADDR);
- writel(0x08021814, RT2880_PCI_ID);
- writel(0x00800001, RT2880_PCI_CLASS);
- writel(0x28801814, RT2880_PCI_SUBID);
- writel(0x000c0000, RT2880_PCI_PCIMSK_ADDR);
+ rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
+ rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
+ rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
+ rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
+ rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
+ rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
+ rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
+ rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
+ rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
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