[xburst] time.c: Timer enable registers are only 8bit width.

[openwrt.git] / target / linux / xburst / files-2.6.32 / arch / mips / jz4740 / clock.c

diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
index 12a54ed..a780706 100644 (file)
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
+++ b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/clock.c
@@ -55,8 +55,8 @@
 #define JZ_CLOCK_GATE_RTC      BIT(2)
 #define JZ_CLOCK_GATE_I2C      BIT(3)
 #define JZ_CLOCK_GATE_SPI      BIT(4)
 #define JZ_CLOCK_GATE_RTC      BIT(2)
 #define JZ_CLOCK_GATE_I2C      BIT(3)
 #define JZ_CLOCK_GATE_SPI      BIT(4)

-#define JZ_CLOCK_GATE_AIC_PCLK BIT(5)
-#define JZ_CLOCK_GATE_AIC      BIT(6)
+#define JZ_CLOCK_GATE_AIC      BIT(5)
+#define JZ_CLOCK_GATE_I2S      BIT(6)

 #define JZ_CLOCK_GATE_MMC      BIT(7)
 #define JZ_CLOCK_GATE_ADC      BIT(8)
 #define JZ_CLOCK_GATE_CIM      BIT(9)
 #define JZ_CLOCK_GATE_MMC      BIT(7)
 #define JZ_CLOCK_GATE_ADC      BIT(8)
 #define JZ_CLOCK_GATE_CIM      BIT(9)


@@ -626,7 +626,7 @@ static struct divided_clk jz4740_clock_divided_clks[] = {
                .clk = {
                        .name = "i2s",
                        .parent = &jz_clk_ext.clk,
                .clk = {
                        .name = "i2s",
                        .parent = &jz_clk_ext.clk,

-                       .gate_bit = JZ_CLOCK_GATE_AIC,
+                       .gate_bit = JZ_CLOCK_GATE_I2S,

                        .ops = &jz_clk_i2s_ops,
                },
                .reg = JZ_REG_CLOCK_I2S,
                        .ops = &jz_clk_i2s_ops,
                },
                .reg = JZ_REG_CLOCK_I2S,


@@ -721,6 +721,12 @@ static struct clk jz4740_clock_simple_clks[] = {
                .gate_bit = JZ_CLOCK_GATE_I2C,
                .ops = &jz_clk_simple_ops,
        },
                .gate_bit = JZ_CLOCK_GATE_I2C,
                .ops = &jz_clk_simple_ops,
        },

+       {
+               .name = "aic",
+               .parent = &jz_clk_ext.clk,
+               .gate_bit = JZ_CLOCK_GATE_AIC,
+               .ops = &jz_clk_simple_ops,
+       },

 };
 
 static struct static_clk jz_clk_rtc = {
 };
 
 static struct static_clk jz_clk_rtc = {