#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
-#define AG71XX_TX_FIFO_LEN 2048
#define AG71XX_TX_MTU_LEN 1540
#define AG71XX_RX_PKT_RESERVE 64
#define AG71XX_RX_PKT_SIZE \
(AG71XX_RX_PKT_RESERVE + ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
-#define AG71XX_TX_RING_SIZE 64
-#define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
-#define AG71XX_TX_THRES_WAKEUP \
- (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
+#define AG71XX_TX_RING_SIZE_DEFAULT 64
+#define AG71XX_RX_RING_SIZE_DEFAULT 128
-#define AG71XX_RX_RING_SIZE 128
+#define AG71XX_TX_RING_SIZE_MAX 256
+#define AG71XX_RX_RING_SIZE_MAX 256
#ifdef CONFIG_AG71XX_DEBUG
#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
struct napi_struct napi;
u32 msg_enable;
+ struct ag71xx_desc *stop_desc;
+ dma_addr_t stop_desc_dma;
+
struct ag71xx_ring rx_ring;
struct ag71xx_ring tx_ring;
#define AG71XX_REG_INT_ENABLE 0x0198
#define AG71XX_REG_INT_STATUS 0x019c
+#define AG71XX_REG_FIFO_DEPTH 0x01a8
+#define AG71XX_REG_RX_SM 0x01b0
+#define AG71XX_REG_TX_SM 0x01b4
+
#define MAC_CFG1_TXE BIT(0) /* Tx Enable */
#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
#define MAC_CFG1_RXE BIT(2) /* Rx Enable */
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
+ case AG71XX_REG_MII_CFG:
break;
default: