ramips: remove 2.6.36 stuff

[openwrt.git] / target / linux / ar7 / patches-2.6.32 / 930-titan-platform.patch

diff --git a/target/linux/ar7/patches-2.6.32/930-titan-platform.patch b/target/linux/ar7/patches-2.6.32/930-titan-platform.patch
index cf6966d..b7ecfc2 100644 (file)
--- a/target/linux/ar7/patches-2.6.32/930-titan-platform.patch
+++ b/target/linux/ar7/patches-2.6.32/930-titan-platform.patch
@@ -1,6 +1,6 @@
 --- a/arch/mips/ar7/platform.c
 +++ b/arch/mips/ar7/platform.c
 --- a/arch/mips/ar7/platform.c
 +++ b/arch/mips/ar7/platform.c

-@@ -131,6 +131,36 @@ static struct resource cpmac_high_res[] 
+@@ -131,6 +131,36 @@ static struct resource cpmac_high_res[]

        },
  };
  
        },
  };
  


@@ -37,7 +37,7 @@
  static struct resource vlynq_low_res[] = {
        {
                .name = "regs",
  static struct resource vlynq_low_res[] = {
        {
                .name = "regs",

-@@ -185,6 +215,60 @@ static struct resource vlynq_high_res[] 
+@@ -185,6 +215,60 @@ static struct resource vlynq_high_res[]

        },
  };
  
        },
  };
  


@@ -192,7 +192,7 @@
  
  static struct gpio_led default_leds[] = {
        {
  
  static struct gpio_led default_leds[] = {
        {

-@@ -300,6 +450,11 @@ static struct gpio_led default_leds[] = 
+@@ -300,6 +450,11 @@ static struct gpio_led default_leds[] =

        },
  };
  
        },
  };
  


@@ -632,7 +632,7 @@
 + *  GPIO Control
 + **********************************************************************/
 +
 + *  GPIO Control
 + **********************************************************************/
 +

-+typedef struct 
++typedef struct

 +{
 +    int pinSelReg;
 +    int shift;
 +{
 +    int pinSelReg;
 +    int shift;


@@ -721,7 +721,7 @@
 +    GPIO_CFG  gpio_cfg;
 +    volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE;
 +    volatile TITAN_GPIO_CONTROL_T   *gpio_cntl     = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
 +    GPIO_CFG  gpio_cfg;
 +    volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE;
 +    volatile TITAN_GPIO_CONTROL_T   *gpio_cntl     = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);

-+      
++

 +    if (gpio_pin > 51 )
 +        return(-1);
 +
 +    if (gpio_pin > 51 )
 +        return(-1);
 +