bcm63xx: add driver for the internal hw trng on bcm6368

[openwrt.git] / target / linux / brcm63xx / patches-3.0 / 240-spi.patch

diff --git a/target/linux/brcm63xx/patches-3.0/240-spi.patch b/target/linux/brcm63xx/patches-3.0/240-spi.patch
index 835cf87..cb009aa 100644 (file)
--- a/target/linux/brcm63xx/patches-3.0/240-spi.patch
+++ b/target/linux/brcm63xx/patches-3.0/240-spi.patch
@@ -135,15 +135,17 @@
  #define RSET_UART_SIZE                        24
  #define RSET_UDC_SIZE                 256
  #define RSET_OHCI_SIZE                        256
-@@ -214,7 +215,7 @@ enum bcm63xx_regs_set {
+@@ -214,8 +215,8 @@ enum bcm63xx_regs_set {
  #define BCM_6358_UART0_BASE           (0xfffe0100)
  #define BCM_6358_UART1_BASE           (0xfffe0120)
  #define BCM_6358_GPIO_BASE            (0xfffe0080)
 -#define BCM_6358_SPI_BASE             (0xdeadbeef)
+-#define BCM_6358_UDC0_BASE            (0xfffe0800)
 +#define BCM_6358_SPI_BASE             (0xfffe0800)
- #define BCM_6358_UDC0_BASE            (0xfffe0400)
++#define BCM_6358_UDC0_BASE            (0xdeadbeef)
  #define BCM_6358_OHCI0_BASE           (0xfffe1400)
  #define BCM_6358_OHCI_PRIV_BASE               (0xdeadbeef)
+ #define BCM_6358_USBH_PRIV_BASE               (0xfffe1500)
 @@ -441,6 +442,7 @@ static inline unsigned long bcm63xx_regs
   */
  enum bcm63xx_irq {
@@ -152,15 +154,15 @@
        IRQ_UART0,
        IRQ_UART1,
        IRQ_DSL,
-@@ -507,6 +509,7 @@ enum bcm63xx_irq {
+@@ -506,6 +508,7 @@ enum bcm63xx_irq {
   * 6348 irqs
   */
  #define BCM_6348_TIMER_IRQ            (IRQ_INTERNAL_BASE + 0)
 +#define BCM_6348_SPI_IRQ              (IRQ_INTERNAL_BASE + 1)
  #define BCM_6348_UART0_IRQ            (IRQ_INTERNAL_BASE + 2)
  #define BCM_6348_DSL_IRQ              (IRQ_INTERNAL_BASE + 4)
- #define BCM_6348_UDC0_IRQ             (IRQ_INTERNAL_BASE + 6)
-@@ -531,6 +534,7 @@ enum bcm63xx_irq {
+ #define BCM_6348_ENET1_IRQ            (IRQ_INTERNAL_BASE + 7)
+@@ -523,6 +526,7 @@ enum bcm63xx_irq {
   * 6358 irqs
   */
  #define BCM_6358_TIMER_IRQ            (IRQ_INTERNAL_BASE + 0)
@@ -170,7 +172,7 @@
  #define BCM_6358_OHCI0_IRQ            (IRQ_INTERNAL_BASE + 5)
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -771,4 +771,116 @@
+@@ -805,4 +805,116 @@
  #define DMIPSPLLCFG_N2_SHIFT          29
  #define DMIPSPLLCFG_N2_MASK           (0x7 << DMIPSPLLCFG_N2_SHIFT)
  
@@ -195,17 +197,17 @@
 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
 +
 +/* BCM 6348 SPI core */
-+#define SPI_BCM_6348_SPI_INT_MASK_ST  0x00
-+#define SPI_BCM_6348_SPI_INT_STATUS   0x01
-+#define SPI_BCM_6348_SPI_CMD          0x02    /* 16-bits register */
-+#define SPI_BCM_6348_SPI_FILL_BYTE    0x04
-+#define SPI_BCM_6348_SPI_CLK_CFG      0x05
-+#define SPI_BCM_6348_SPI_ST           0x06
-+#define SPI_BCM_6348_SPI_INT_MASK     0x07
-+#define SPI_BCM_6348_SPI_RX_TAIL      0x08
-+#define SPI_BCM_6348_SPI_MSG_TAIL     0x10
-+#define SPI_BCM_6348_SPI_MSG_DATA     0x40
-+#define SPI_BCM_6348_SPI_MSG_CTL      0x42
++#define SPI_BCM_6348_SPI_CMD          0x00    /* 16-bits register */
++#define SPI_BCM_6348_SPI_INT_STATUS   0x02
++#define SPI_BCM_6348_SPI_INT_MASK_ST  0x03
++#define SPI_BCM_6348_SPI_INT_MASK     0x04
++#define SPI_BCM_6348_SPI_ST           0x05
++#define SPI_BCM_6348_SPI_CLK_CFG      0x06
++#define SPI_BCM_6348_SPI_FILL_BYTE    0x07
++#define SPI_BCM_6348_SPI_MSG_TAIL     0x09
++#define SPI_BCM_6348_SPI_RX_TAIL      0x0b
++#define SPI_BCM_6348_SPI_MSG_CTL      0x40
++#define SPI_BCM_6348_SPI_MSG_DATA     0x41
 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE        0x3f
 +#define SPI_BCM_6348_SPI_RX_DATA      0x80
 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
@@ -244,10 +246,10 @@
 +#define SPI_MSG_TYPE_SHIFT            14
 +
 +/* Command */
-+#define SPI_CMD_NOOP                  0x01
-+#define SPI_CMD_SOFT_RESET            0x02
-+#define SPI_CMD_HARD_RESET            0x04
-+#define SPI_CMD_START_IMMEDIATE               0x08
++#define SPI_CMD_NOOP                  0x00
++#define SPI_CMD_SOFT_RESET            0x01
++#define SPI_CMD_HARD_RESET            0x02
++#define SPI_CMD_START_IMMEDIATE               0x03
 +#define SPI_CMD_COMMAND_SHIFT         0
 +#define SPI_CMD_COMMAND_MASK          0x000f
 +#define SPI_CMD_DEVICE_ID_SHIFT               4
@@ -847,7 +849,7 @@
 +
 +#define __GEN_SPI_RSET_BASE(__cpu, __rset)                            \
 +      case SPI_## __rset:                                             \
-+              return SPI_BCM_## __cpu ##_SPI_## __rset ##;
++              return SPI_BCM_## __cpu ##_SPI_## __rset;
 +
 +#define __GEN_SPI_RSET(__cpu)                                         \
 +      switch (reg) {                                                  \
@@ -904,27 +906,27 @@
 @@ -1,6 +1,6 @@
  obj-y         += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
                   dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o \
--                 dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o
-+                 dev-usb-ohci.o dev-usb-ehci.o dev-usb-udc.o dev-spi.o
+-                 dev-usb-ohci.o dev-usb-ehci.o
++                 dev-usb-ohci.o dev-usb-ehci.o dev-spi.o
  obj-$(CONFIG_EARLY_PRINTK)    += early_printk.o
  
  obj-y         += boards/
 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
-@@ -30,6 +30,7 @@
+@@ -29,6 +29,7 @@
+ #include <bcm63xx_dev_pcmcia.h>
  #include <bcm63xx_dev_usb_ohci.h>
  #include <bcm63xx_dev_usb_ehci.h>
- #include <bcm63xx_dev_usb_udc.h>
 +#include <bcm63xx_dev_spi.h>
  #include <board_bcm963xx.h>
  
  #define PFX   "board_bcm963xx: "
-@@ -939,6 +940,8 @@ int __init board_register_devices(void)
+@@ -927,6 +928,8 @@ int __init board_register_devices(void)
        if (board.num_spis)
                spi_register_board_info(board.spis, board.num_spis);
  
 +      bcm63xx_spi_register();
 +
        /* read base address of boot chip select (0) */
-       if (BCMCPU_IS_6345())
-               val = 0x1fc00000;
+       val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+       val &= MPI_CSBASE_BASE_MASK;