+#define AR934X_PLL_REG_CPU_CONFIG 0x00
+#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8
+
+#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21
+#define AR934X_CPU_PLL_CFG_OUTDIV_LSB 19
+#define AR934X_CPU_PLL_CFG_OUTDIV_MASK 0x00380000
+
+#define AR934X_CPU_PLL_CFG_OUTDIV_GET(x) \
+ (((x) & AR934X_CPU_PLL_CFG_OUTDIV_MASK) >> \
+ AR934X_CPU_PLL_CFG_OUTDIV_LSB)
+
+#define AR934X_DDR_PLL_CFG_OUTDIV_MSB 25
+#define AR934X_DDR_PLL_CFG_OUTDIV_LSB 23
+#define AR934X_DDR_PLL_CFG_OUTDIV_MASK 0x03800000
+
+#define AR934X_DDR_PLL_CFG_OUTDIV_GET(x) \
+ (((x) & AR934X_DDR_PLL_CFG_OUTDIV_MASK) >> \
+ AR934X_DDR_PLL_CFG_OUTDIV_LSB)
+
+#define AR934X_DDR_PLL_CFG_OUTDIV_SET(x) \
+ (((x) << AR934X_DDR_PLL_CFG_OUTDIV_LSB) & \
+ AR934X_DDR_PLL_CFG_OUTDIV_MASK)
+
+#define AR934X_CPU_PLL_CFG_REFDIV_MSB 16
+#define AR934X_CPU_PLL_CFG_REFDIV_LSB 12
+#define AR934X_CPU_PLL_CFG_REFDIV_MASK 0x0001f000
+
+#define AR934X_CPU_PLL_CFG_REFDIV_GET(x) \
+ (((x) & AR934X_CPU_PLL_CFG_REFDIV_MASK) >> \
+ AR934X_CPU_PLL_CFG_REFDIV_LSB)
+
+#define AR934X_CPU_PLL_CFG_REFDIV_SET(x) \
+ (((x) << AR934X_CPU_PLL_CFG_REFDIV_LSB) & \
+ AR934X_CPU_PLL_CFG_REFDIV_MASK)
+
+#define AR934X_CPU_PLL_CFG_REFDIV_RESET 2
+
+#define AR934X_CPU_PLL_CFG_NINT_MSB 11
+#define AR934X_CPU_PLL_CFG_NINT_LSB 6
+#define AR934X_CPU_PLL_CFG_NINT_MASK 0x00000fc0
+
+#define AR934X_CPU_PLL_CFG_NINT_GET(x) \
+ (((x) & AR934X_CPU_PLL_CFG_NINT_MASK) >> \
+ AR934X_CPU_PLL_CFG_NINT_LSB)
+
+#define AR934X_CPU_PLL_CFG_NINT_SET(x) \
+ (((x) << AR934X_CPU_PLL_CFG_NINT_LSB) & \
+ AR934X_CPU_PLL_CFG_NINT_MASK)
+
+#define AR934X_CPU_PLL_CFG_NINT_RESET 20
+
+#define AR934X_CPU_PLL_CFG_NFRAC_MSB 5
+#define AR934X_CPU_PLL_CFG_NFRAC_LSB 0
+#define AR934X_CPU_PLL_CFG_NFRAC_MASK 0x0000003f
+
+#define AR934X_CPU_PLL_CFG_NFRAC_GET(x) \
+ (((x) & AR934X_CPU_PLL_CFG_NFRAC_MASK) >> \
+ AR934X_CPU_PLL_CFG_NFRAC_LSB)
+
+#define AR934X_CPU_PLL_CFG_NFRAC_SET(x) \
+ (((x) << AR934X_CPU_PLL_CFG_NFRAC_LSB) & \
+ AR934X_CPU_PLL_CFG_NFRAC_MASK)
+
+#define AR934X_DDR_PLL_CFG_REFDIV_MSB 20
+#define AR934X_DDR_PLL_CFG_REFDIV_LSB 16
+#define AR934X_DDR_PLL_CFG_REFDIV_MASK 0x001f0000
+
+#define AR934X_DDR_PLL_CFG_REFDIV_GET(x) \
+ (((x) & AR934X_DDR_PLL_CFG_REFDIV_MASK) >> \
+ AR934X_DDR_PLL_CFG_REFDIV_LSB)
+
+#define AR934X_DDR_PLL_CFG_REFDIV_SET(x) \
+ (((x) << AR934X_DDR_PLL_CFG_REFDIV_LSB) & \
+ AR934X_DDR_PLL_CFG_REFDIV_MASK)
+
+#define AR934X_DDR_PLL_CFG_REFDIV_RESET 2
+
+#define AR934X_DDR_PLL_CFG_NINT_MSB 15
+#define AR934X_DDR_PLL_CFG_NINT_LSB 10
+#define AR934X_DDR_PLL_CFG_NINT_MASK 0x0000fc00
+
+#define AR934X_DDR_PLL_CFG_NINT_GET(x) \
+ (((x) & AR934X_DDR_PLL_CFG_NINT_MASK) >> \
+ AR934X_DDR_PLL_CFG_NINT_LSB)
+
+#define AR934X_DDR_PLL_CFG_NINT_SET(x) \
+ (((x) << AR934X_DDR_PLL_CFG_NINT_LSB) & \
+ AR934X_DDR_PLL_CFG_NINT_MASK)
+
+#define AR934X_DDR_PLL_CFG_NINT_RESET 20
+
+#define AR934X_DDR_PLL_CFG_NFRAC_MSB 9
+#define AR934X_DDR_PLL_CFG_NFRAC_LSB 0
+#define AR934X_DDR_PLL_CFG_NFRAC_MASK 0x000003ff
+
+#define AR934X_DDR_PLL_CFG_NFRAC_GET(x) \
+ (((x) & AR934X_DDR_PLL_CFG_NFRAC_MASK) >> \
+ AR934X_DDR_PLL_CFG_NFRAC_LSB)
+
+#define AR934X_DDR_PLL_CFG_NFRAC_SET(x) \
+ (((x) << AR934X_DDR_PLL_CFG_NFRAC_LSB) & \
+ AR934X_DDR_PLL_CFG_NFRAC_MASK)
+
+#define AR934X_DDR_PLL_CFG_NFRAC_RESET 512
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MSB 19
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB 15
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x000f8000
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(x) \
+ (((x) & AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK) >> \
+ AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB)
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SET(x) \
+ (((x) << AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_LSB) & \
+ AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK)
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_RESET 0
+
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MSB 14
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB 10
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x00007c00
+
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(x) \
+ (((x) & AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK) >> \
+ AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB)
+
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SET(x) \
+ (((x) << AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_LSB) & \
+ AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK)
+
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_RESET 0
+
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MSB 9
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB 5
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x000003e0
+
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(x) \
+ (((x) & AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK) >> \
+ AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB)
+
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SET(x) \
+ (((x) << AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_LSB) & \
+ AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK)
+
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_RESET 0
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MSB 24
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB 24
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK 0x01000000
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(x) \
+ (((x) & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK) >> \
+ AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB)
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_SET(x) \
+ (((x) << AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_LSB) & \
+ AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_MASK)
+
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1
+