static void ar934x_set_speed_ge0(int speed)
{
- /* TODO */
+ void __iomem *base;
+ u32 val = ath79_get_eth_pll(0, speed);
+
+ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+ __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
+ iounmap(base);
}
static void ath79_set_speed_dummy(int speed)
#define AR933X_PLL_VAL_100 0x00001099
#define AR933X_PLL_VAL_10 0x00991099
-#define AR934X_PLL_VAL_1000 0x00110000
-#define AR934X_PLL_VAL_100 0x00001099
-#define AR934X_PLL_VAL_10 0x00991099
+#define AR934X_PLL_VAL_1000 0x16000000
+#define AR934X_PLL_VAL_100 0x00000101
+#define AR934X_PLL_VAL_10 0x00001616
static void __init ath79_init_eth_pll_data(unsigned int id)
{
pdata->set_speed = ath79_set_speed_dummy;
pdata->switch_data = &ath79_switch_data;
+
+ /* reset the built-in switch */
+ ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
+ ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
}
pdata->ddr_flush = ath79_ddr_no_flush;