-#define PLL_SEC_CONFIG 0x18050004
-#define PLL_ETH0_INT_CLOCK 0x18050010
-#define PLL_ETH1_INT_CLOCK 0x18050014
-#define PLL_ETH_EXT_CLOCK 0x18050018
-
-#define ag71xx_pll_shift(_ag) (((_ag)->pdev->id) ? 19 : 17)
-#define ag71xx_pll_offset(_ag) (((_ag)->pdev->id) ? PLL_ETH1_INT_CLOCK \
- : PLL_ETH0_INT_CLOCK)
-
-static void ag71xx_set_pll(struct ag71xx *ag, u32 pll_val)
-{
- void __iomem *pll_reg = ioremap_nocache(ag71xx_pll_offset(ag), 4);
- void __iomem *pll_cfg = ioremap_nocache(PLL_SEC_CONFIG, 4);
- u32 s;
- u32 t;
-
- s = ag71xx_pll_shift(ag);
-
- t = __raw_readl(pll_cfg);
- t &= ~(3 << s);
- t |= (2 << s);
- __raw_writel(t, pll_cfg);
- udelay(100);
-
- __raw_writel(pll_val, pll_reg);
-
- t |= (3 << s);
- __raw_writel(t, pll_cfg);
- udelay(100);
-
- t &= ~(3 << s);
- __raw_writel(t, pll_cfg);
- udelay(100);
- DBG("%s: pll_reg %#x: %#x\n", ag->dev->name,
- (unsigned int)pll_reg, __raw_readl(pll_reg));
-
- iounmap(pll_cfg);
- iounmap(pll_reg);
-}
-
-static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
-{
- switch (ag->speed) {
- case SPEED_1000:
- return "1000";
- case SPEED_100:
- return "100";
- case SPEED_10:
- return "10";
- }
-
- return "?";
-}
-
-#if 1
-#define PLL_VAL_1000 0x00110000
-#define PLL_VAL_100 0x00001099
-#define PLL_VAL_10 0x00991099
-#else
-#define PLL_VAL_1000 0x01111000
-#define PLL_VAL_100 0x09991000
-#define PLL_VAL_10 0x09991999
-#endif
-
-static void ag71xx_phy_link_update(struct ag71xx *ag)
-{
- u32 cfg2;
- u32 ifctl;
- u32 pll;
- u32 fifo5;
- u32 mii_speed;
-
- if (!ag->link) {
- netif_carrier_off(ag->dev);
- printk(KERN_INFO "%s: link down\n", ag->dev->name);
- return;
- }
-
- cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
- cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
- cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
-
- ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
- ifctl &= ~(MAC_IFCTL_SPEED);
-
- fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
- fifo5 &= ~FIFO_CFG5_BYTE_PER_CLK;
-
- switch (ag->speed) {
- case SPEED_1000:
- mii_speed = MII_CTRL_SPEED_1000;
- cfg2 |= MAC_CFG2_IF_1000;
- pll = PLL_VAL_1000;
- fifo5 |= FIFO_CFG5_BYTE_PER_CLK;
- break;
- case SPEED_100:
- mii_speed = MII_CTRL_SPEED_100;
- cfg2 |= MAC_CFG2_IF_10_100;
- ifctl |= MAC_IFCTL_SPEED;
- pll = PLL_VAL_100;
- break;
- case SPEED_10:
- mii_speed = MII_CTRL_SPEED_10;
- cfg2 |= MAC_CFG2_IF_10_100;
- pll = PLL_VAL_10;
- break;
- default:
- BUG();
- return;
- }
-
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
- ag71xx_set_pll(ag, pll);
- ag71xx_mii_ctrl_set_speed(ag, mii_speed);
-
- ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
- ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
- ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
-
- netif_carrier_on(ag->dev);
- printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
- ag->dev->name,
- ag71xx_speed_str(ag),
- (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
-
- DBG("%s: fifo1=%#x, fifo2=%#x, fifo3=%#x, fifo4=%#x, fifo5=%#x\n",
- ag->dev->name,
- ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
- ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2),
- ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
- ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
- ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
-
- DBG("%s: mac_cfg2=%#x, ifctl=%#x, mii_ctrl=%#x\n",
- ag->dev->name,
- ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
- ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
- ag71xx_mii_ctrl_rr(ag));
-}
-