-#define REV_ID_MASK 0xff
-#define REV_ID_CHIP_MASK 0xf3
-#define REV_ID_CHIP_AR7130 0xa0
-#define REV_ID_CHIP_AR7141 0xa1
-#define REV_ID_CHIP_AR7161 0xa2
-#define REV_ID_CHIP_AR9130 0xb0
-#define REV_ID_CHIP_AR9132 0xb1
-
-#define REV_ID_REVISION_MASK 0x3
-#define REV_ID_REVISION_SHIFT 2
+#define AR724X_RESET_GE1_MDIO BIT(23)
+#define AR724X_RESET_GE0_MDIO BIT(22)
+#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
+#define AR724X_RESET_PCIE_PHY BIT(7)
+#define AR724X_RESET_PCIE BIT(6)
+#define AR724X_RESET_USB_HOST BIT(5)
+#define AR724X_RESET_USB_PHY BIT(4)
+#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define REV_ID_MAJOR_MASK 0xfff0
+#define REV_ID_MAJOR_AR71XX 0x00a0
+#define REV_ID_MAJOR_AR913X 0x00b0
+#define REV_ID_MAJOR_AR7240 0x00c0
+#define REV_ID_MAJOR_AR7241 0x0100
+#define REV_ID_MAJOR_AR7242 0x1100
+
+#define AR71XX_REV_ID_MINOR_MASK 0x3
+#define AR71XX_REV_ID_MINOR_AR7130 0x0
+#define AR71XX_REV_ID_MINOR_AR7141 0x1
+#define AR71XX_REV_ID_MINOR_AR7161 0x2
+#define AR71XX_REV_ID_REVISION_MASK 0x3
+#define AR71XX_REV_ID_REVISION_SHIFT 2
+
+#define AR91XX_REV_ID_MINOR_MASK 0x3
+#define AR91XX_REV_ID_MINOR_AR9130 0x0
+#define AR91XX_REV_ID_MINOR_AR9132 0x1
+#define AR91XX_REV_ID_REVISION_MASK 0x3
+#define AR91XX_REV_ID_REVISION_SHIFT 2
+
+#define AR724X_REV_ID_REVISION_MASK 0x3