#define PLL_REG_ETH_EXT_CLK 0x18
#define PLL_REG_PCI_CLK 0x1c
-#define PLL_DIV_SHIFT 3
-#define PLL_DIV_MASK 0x1f
-#define CPU_DIV_SHIFT 16
-#define CPU_DIV_MASK 0x3
-#define DDR_DIV_SHIFT 18
-#define DDR_DIV_MASK 0x3
-#define AHB_DIV_SHIFT 20
-#define AHB_DIV_MASK 0x7
+#define AR71XX_PLL_DIV_SHIFT 3
+#define AR71XX_PLL_DIV_MASK 0x1f
+#define AR71XX_CPU_DIV_SHIFT 16
+#define AR71XX_CPU_DIV_MASK 0x3
+#define AR71XX_DDR_DIV_SHIFT 18
+#define AR71XX_DDR_DIV_MASK 0x3
+#define AR71XX_AHB_DIV_SHIFT 20
+#define AR71XX_AHB_DIV_MASK 0x7
+
+#define AR91XX_PLL_DIV_SHIFT 0
+#define AR91XX_PLL_DIV_MASK 0x3ff
+#define AR91XX_DDR_DIV_SHIFT 22
+#define AR91XX_DDR_DIV_MASK 0x3
+#define AR91XX_AHB_DIV_SHIFT 19
+#define AR91XX_AHB_DIV_MASK 0x1
extern void __iomem *ar71xx_pll_base;
#define RESET_REG_PERFC1 0x34
#define RESET_REG_REV_ID 0x90
+#define WDOG_CTRL_LAST_RESET BIT(31)
+#define WDOG_CTRL_ACTION_MASK 3
+#define WDOG_CTRL_ACTION_NONE 0 /* no action */
+#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
+#define WDOG_CTRL_ACTION_NMI 2 /* NMI */
+#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
+
#define MISC_INT_DMA BIT(7)
#define MISC_INT_OHCI BIT(6)
#define MISC_INT_PERFC BIT(5)
#define REV_ID_CHIP_AR7130 0xa0
#define REV_ID_CHIP_AR7141 0xa1
#define REV_ID_CHIP_AR7161 0xa2
+#define REV_ID_CHIP_AR9130 0xb0
#define REV_ID_REVISION_MASK 0x3
#define REV_ID_REVISION_SHIFT 2
#define MII1_CTRL_IF_RGMII 0
#define MII1_CTRL_IF_RMII 1
-#include <asm/bootinfo.h>
-#include <linux/init.h>
-
-#define ar71xx_print_cmdline() do { \
- printk(KERN_DEBUG "%s:%d arcs_cmdline:'%s'\n", \
- __FUNCTION__, __LINE__, arcs_cmdline); \
- printk(KERN_DEBUG "%s:%d boot_command_line:'%s'\n", \
- __FUNCTION__, __LINE__, boot_command_line); \
- } while (0)
-
#endif /* __ASSEMBLER__ */
#endif /* __ASM_MACH_AR71XX_H */