-#define MEMCTRL_SR0S_MASK BITMASK(3) /* SRAM0 size */
-#define MEMCTRL_SR0S_SHIFT 8
-#define MEMCTRL_SR1S_MASK BITMAKS(3) /* SRAM1 size */
-#define MEMCTRL_SR1S_SHIFT 16
+
+#define MEMCTRL_SRS0_SHIFT 8 /* shift for SRAM0 size */
+#define MEMCTRL_SRS1_SHIFT 16 /* shift for SRAM1 size */
+#define MEMCTRL_SRS_MASK BITMASK(3) /* SRAM size mask */
+#define MEMCTRL_SRS_DISABLED 0x00 /* Disabled */
+#define MEMCTRL_SRS_512K 0x01 /* 512KB*/
+#define MEMCTRL_SRS_1M 0x02 /* 1MB */
+#define MEMCTRL_SRS_2M 0x03 /* 2MB */
+#define MEMCTRL_SRS_4M 0x04 /* 4MB */