[adm5120] fix mac address setup on RouterBOARDs

[openwrt.git] / target / linux / adm5120 / files / include / asm-mips / mach-adm5120 / adm5120_switch.h

diff --git a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
index d185ce5..f96c7d5 100644 (file)
--- a/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
+++ b/target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_switch.h
@@ -164,12 +164,12 @@
 #define MAC_WT0_MWD_SHIFT      1
 #define MAC_WT0_MWD            BIT(1)  /* MAC write done */
 #define MAC_WT0_WFB            BIT(2)  /* Write Filter Bit */
 #define MAC_WT0_MWD_SHIFT      1
 #define MAC_WT0_MWD            BIT(1)  /* MAC write done */
 #define MAC_WT0_WFB            BIT(2)  /* Write Filter Bit */

-#define MAC_WT0_WVN_SHIFT      3
+#define MAC_WT0_WVN_SHIFT      3       /* Write Vlan Number shift */

 #define MAC_WT0_WVE            BIT(6)  /* Write VLAN enable */
 #define MAC_WT0_WPMN_SHIFT     7
 #define MAC_WT0_WAF_SHIFT      13      /* Write Age Field shift */
 #define MAC_WT0_WAF_EMPTY      0
 #define MAC_WT0_WVE            BIT(6)  /* Write VLAN enable */
 #define MAC_WT0_WPMN_SHIFT     7
 #define MAC_WT0_WAF_SHIFT      13      /* Write Age Field shift */
 #define MAC_WT0_WAF_EMPTY      0

-#define MAC_WT0_WAF_STATIC     7
+#define MAC_WT0_WAF_STATIC     7       /* age: static */

 #define MAC_WT0_MAC0_SHIFT     16
 #define MAC_WT0_MAC1_SHIFT     24
 
 #define MAC_WT0_MAC0_SHIFT     16
 #define MAC_WT0_MAC1_SHIFT     24
 


@@ -247,6 +247,11 @@
 #define GPIO_CONF0_OE_MASK     (0xFF << GPIO_CONF0_OE_SHIFT)
 #define GPIO_CONF0_OV_MASK     (0xFF << GPIO_CONF0_OV_SHIFT)
 
 #define GPIO_CONF0_OE_MASK     (0xFF << GPIO_CONF0_OE_SHIFT)
 #define GPIO_CONF0_OV_MASK     (0xFF << GPIO_CONF0_OV_SHIFT)
 

+/* GPIO_CONF2 register bits */
+#define GPIO_CONF2_CSX0                BIT(4)  /* enable CSX0:INTX0 on GPIO 1:2 */
+#define GPIO_CONF2_CSX1                BIT(5)  /* enable CSX1:INTX1 on GPIO 3:4 */
+#define GPIO_CONF2_EW          BIT(6)  /* enable wait state pin for CSX0/1 */
+

 /* INT_STATUS/INT_MASK register bits */
 #define SWITCH_INT_SHD         BIT(0)  /* Send High Done */
 #define SWITCH_INT_SLD         BIT(1)  /* Send Low Done */
 /* INT_STATUS/INT_MASK register bits */
 #define SWITCH_INT_SHD         BIT(0)  /* Send High Done */
 #define SWITCH_INT_SLD         BIT(1)  /* Send Low Done */