[xburst] time.c: Timer enable registers are only 8bit width.

[openwrt.git] / target / linux / xburst / files-2.6.32 / arch / mips / jz4740 / irq.c

diff --git a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/irq.c b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/irq.c
index a6f4bbf..5555026 100644 (file)
--- a/target/linux/xburst/files-2.6.32/arch/mips/jz4740/irq.c
+++ b/target/linux/xburst/files-2.6.32/arch/mips/jz4740/irq.c
@@ -88,7 +88,8 @@ static irqreturn_t jz4740_cascade(int irq, void *data)
 
 static struct irqaction jz4740_cascade_action = {
        .handler = jz4740_cascade,
-       .name = "JZ4740 cascade interrupt"
+       .name = "JZ4740 cascade interrupt",
+       .flags = IRQF_DISABLED,
 };
 
 void __init arch_init_irq(void)
@@ -110,7 +111,7 @@ asmlinkage void plat_irq_dispatch(void)
 {
        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
        if (pending & STATUSF_IP2)
-               jz4740_cascade(2, NULL);
+               do_IRQ(2);
        else if(pending & STATUSF_IP3)
                do_IRQ(3);
        else
@@ -122,11 +123,13 @@ void jz4740_intc_suspend(void)
 {
        jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
        writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
+       writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
 }
 
 void jz4740_intc_resume(void)
 {
        writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
+       writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
 }
 
 #ifdef CONFIG_DEBUG_FS