+ /* Initialize the ports */
+ bus = priv->phy->bus;
+ for (i = 0; i < 5; i++) {
+ if ((i == 4) &&
+ priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
+ /* work around for phy4 rgmii mode */
+ bus->write(bus, i, MII_ATH_DBG_ADDR, 0x12);
+ bus->write(bus, i, MII_ATH_DBG_DATA, 0x480c);
+ /* rx delay */
+ bus->write(bus, i, MII_ATH_DBG_ADDR, 0x0);
+ bus->write(bus, i, MII_ATH_DBG_DATA, 0x824e);
+ /* tx delay */
+ bus->write(bus, i, MII_ATH_DBG_ADDR, 0x5);
+ bus->write(bus, i, MII_ATH_DBG_DATA, 0x3d47);
+ msleep(1000);
+ }
+
+ /* initialize the port itself */
+ bus->write(bus, i, MII_ADVERTISE,
+ ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
+ bus->write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
+ bus->write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+ msleep(1000);
+ }
+ initialized = true;