- DEBUG(MTD_DEBUG_LEVEL2,
-- "mtd .name = %s, .size = 0x%.8x (%uM) "
-- ".erasesize = 0x%.8x (%uK) .numeraseregions = %d\n",
-+ "mtd .name = %s, .size = 0x%.8x (%uMiB) "
-+ ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
- flash->mtd.name,
- flash->mtd.size, flash->mtd.size / (1024*1024),
- flash->mtd.erasesize, flash->mtd.erasesize / 1024,
-@@ -488,7 +612,7 @@ static int __devinit m25p_probe(struct spi_device *spi)
- for (i = 0; i < flash->mtd.numeraseregions; i++)
- DEBUG(MTD_DEBUG_LEVEL2,
- "mtd.eraseregions[%d] = { .offset = 0x%.8x, "
-- ".erasesize = 0x%.8x (%uK), "
-+ ".erasesize = 0x%.8x (%uKiB), "
- ".numblocks = %d }\n",
- i, flash->mtd.eraseregions[i].offset,
- flash->mtd.eraseregions[i].erasesize,
-@@ -516,14 +640,14 @@ static int __devinit m25p_probe(struct spi_device *spi)
- }
-
- if (nr_parts > 0) {
-- for (i = 0; i < data->nr_parts; i++) {
-+ for (i = 0; i < nr_parts; i++) {
- DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = "
- "{.name = %s, .offset = 0x%.8x, "
-- ".size = 0x%.8x (%uK) }\n",
-- i, data->parts[i].name,
-- data->parts[i].offset,
-- data->parts[i].size,
-- data->parts[i].size / 1024);
-+ ".size = 0x%.8x (%uKiB) }\n",
-+ i, parts[i].name,
-+ parts[i].offset,
-+ parts[i].size,
-+ parts[i].size / 1024);
- }
- flash->partitioned = 1;
- return add_mtd_partitions(&flash->mtd, parts, nr_parts);
-@@ -560,6 +684,11 @@ static struct spi_driver m25p80_driver = {
- },
- .probe = m25p_probe,
- .remove = __devexit_p(m25p_remove),
-+
-+ /* REVISIT: many of these chips have deep power-down modes, which
-+ * should clearly be entered on suspend() to minimize power use.
-+ * And also when they're otherwise idle...
-+ */
- };
-
-
-diff --git a/drivers/mtd/devices/mtd_dataflash.c b/drivers/mtd/devices/mtd_dataflash.c
-index a987e91..a5ed6d2 100644
---- a/drivers/mtd/devices/mtd_dataflash.c
-+++ b/drivers/mtd/devices/mtd_dataflash.c
-@@ -14,6 +14,7 @@
- #include <linux/slab.h>
- #include <linux/delay.h>
- #include <linux/device.h>
-+#include <linux/mutex.h>
- #include <linux/spi/spi.h>
- #include <linux/spi/flash.h>
-
-@@ -89,7 +90,7 @@ struct dataflash {
- unsigned short page_offset; /* offset in flash address */
- unsigned int page_size; /* of bytes per page */
-
-- struct semaphore lock;
-+ struct mutex lock;
- struct spi_device *spi;
-
- struct mtd_info mtd;
-@@ -167,7 +168,7 @@ static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
- x.len = 4;
- spi_message_add_tail(&x, &msg);
-
-- down(&priv->lock);
-+ mutex_lock(&priv->lock);
- while (instr->len > 0) {
- unsigned int pageaddr;
- int status;
-@@ -210,7 +211,7 @@ static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
- instr->len -= priv->page_size;
- }
- }
-- up(&priv->lock);
-+ mutex_unlock(&priv->lock);
-
- /* Inform MTD subsystem that erase is complete */
- instr->state = MTD_ERASE_DONE;
-@@ -266,7 +267,7 @@ static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len,
- x[1].len = len;
- spi_message_add_tail(&x[1], &msg);
-
-- down(&priv->lock);
-+ mutex_lock(&priv->lock);
-
- /* Continuous read, max clock = f(car) which may be less than
- * the peak rate available. Some chips support commands with
-@@ -279,7 +280,7 @@ static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len,
- /* plus 4 "don't care" bytes */
-
- status = spi_sync(priv->spi, &msg);
-- up(&priv->lock);
-+ mutex_unlock(&priv->lock);
-
- if (status >= 0) {
- *retlen = msg.actual_length - 8;
-@@ -336,7 +337,7 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len,
- else
- writelen = len;
-
-- down(&priv->lock);
-+ mutex_lock(&priv->lock);
- while (remaining > 0) {
- DEBUG(MTD_DEBUG_LEVEL3, "write @ %i:%i len=%i\n",
- pageaddr, offset, writelen);
-@@ -441,7 +442,7 @@ static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len,
- else
- writelen = remaining;
- }
-- up(&priv->lock);
-+ mutex_unlock(&priv->lock);
-
- return status;
- }
-@@ -463,7 +464,7 @@ add_dataflash(struct spi_device *spi, char *name,
- if (!priv)
- return -ENOMEM;
-
-- init_MUTEX(&priv->lock);
-+ mutex_init(&priv->lock);
- priv->spi = spi;
- priv->page_size = pagesize;
- priv->page_offset = pageoffset;
-diff --git a/drivers/mtd/devices/pmc551.c b/drivers/mtd/devices/pmc551.c
-index e8f686f..7060a08 100644
---- a/drivers/mtd/devices/pmc551.c
-+++ b/drivers/mtd/devices/pmc551.c
-@@ -30,8 +30,8 @@
- *
- * Notes:
- * Due to what I assume is more buggy SROM, the 64M PMC551 I
-- * have available claims that all 4 of it's DRAM banks have 64M
-- * of ram configured (making a grand total of 256M onboard).
-+ * have available claims that all 4 of its DRAM banks have 64MiB
-+ * of ram configured (making a grand total of 256MiB onboard).
- * This is slightly annoying since the BAR0 size reflects the
- * aperture size, not the dram size, and the V370PDC supplies no
- * other method for memory size discovery. This problem is
-@@ -70,7 +70,7 @@
- * made the memory unusable, added a fix to code to touch up
- * the DRAM some.
- *
-- * Bugs/FIXME's:
-+ * Bugs/FIXMEs:
- * * MUST fix the init function to not spin on a register
- * waiting for it to set .. this does not safely handle busted
- * devices that never reset the register correctly which will
-@@ -562,10 +562,10 @@ static u32 fixup_pmc551(struct pci_dev *dev)
- /*
- * Some screen fun
- */
-- printk(KERN_DEBUG "pmc551: %d%c (0x%x) of %sprefetchable memory at "
-+ printk(KERN_DEBUG "pmc551: %d%sB (0x%x) of %sprefetchable memory at "
- "0x%llx\n", (size < 1024) ? size : (size < 1048576) ?
- size >> 10 : size >> 20,
-- (size < 1024) ? 'B' : (size < 1048576) ? 'K' : 'M', size,
-+ (size < 1024) ? "" : (size < 1048576) ? "Ki" : "Mi", size,
- ((dcmd & (0x1 << 3)) == 0) ? "non-" : "",
- (unsigned long long)pci_resource_start(dev, 0));
-
-@@ -649,14 +649,10 @@ MODULE_DESCRIPTION(PMC551_VERSION);
- * Stuff these outside the ifdef so as to not bust compiled in driver support
- */
- static int msize = 0;
--#if defined(CONFIG_MTD_PMC551_APERTURE_SIZE)
--static int asize = CONFIG_MTD_PMC551_APERTURE_SIZE;
--#else
- static int asize = 0;
--#endif
-
- module_param(msize, int, 0);
--MODULE_PARM_DESC(msize, "memory size in Megabytes [1 - 1024]");
-+MODULE_PARM_DESC(msize, "memory size in MiB [1 - 1024]");
- module_param(asize, int, 0);
- MODULE_PARM_DESC(asize, "aperture size, must be <= memsize [1-1024]");
-
-@@ -799,8 +795,7 @@ static int __init init_pmc551(void)
- mtd->owner = THIS_MODULE;
-
- if (add_mtd_device(mtd)) {
-- printk(KERN_NOTICE "pmc551: Failed to register new "
-- "device\n");
-+ printk(KERN_NOTICE "pmc551: Failed to register new device\n");
- pci_iounmap(PCI_Device, priv->start);
- kfree(mtd->priv);
- kfree(mtd);
-@@ -811,13 +806,13 @@ static int __init init_pmc551(void)
- pci_dev_get(PCI_Device);
-
- printk(KERN_NOTICE "Registered pmc551 memory device.\n");
-- printk(KERN_NOTICE "Mapped %dM of memory from 0x%p to 0x%p\n",
-+ printk(KERN_NOTICE "Mapped %dMiB of memory from 0x%p to 0x%p\n",
- priv->asize >> 20,
- priv->start, priv->start + priv->asize);
-- printk(KERN_NOTICE "Total memory is %d%c\n",
-+ printk(KERN_NOTICE "Total memory is %d%sB\n",
- (length < 1024) ? length :
- (length < 1048576) ? length >> 10 : length >> 20,
-- (length < 1024) ? 'B' : (length < 1048576) ? 'K' : 'M');
-+ (length < 1024) ? "" : (length < 1048576) ? "Ki" : "Mi");
- priv->nextpmc551 = pmc551list;
- pmc551list = mtd;
- found++;
-@@ -850,7 +845,7 @@ static void __exit cleanup_pmc551(void)
- pmc551list = priv->nextpmc551;
-
- if (priv->start) {
-- printk(KERN_DEBUG "pmc551: unmapping %dM starting at "
-+ printk(KERN_DEBUG "pmc551: unmapping %dMiB starting at "
- "0x%p\n", priv->asize >> 20, priv->start);
- pci_iounmap(priv->dev, priv->start);
- }
-diff --git a/drivers/mtd/maps/nettel.c b/drivers/mtd/maps/nettel.c
-index 7b96cd0..0c9b305 100644
---- a/drivers/mtd/maps/nettel.c
-+++ b/drivers/mtd/maps/nettel.c
-@@ -158,68 +158,11 @@ static struct notifier_block nettel_notifier_block = {
- nettel_reboot_notifier, NULL, 0
- };
-
--/*
-- * Erase the configuration file system.
-- * Used to support the software reset button.
-- */
--static void nettel_erasecallback(struct erase_info *done)
--{
-- wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
-- wake_up(wait_q);
--}
--
--static struct erase_info nettel_erase;
--
--int nettel_eraseconfig(void)
--{
-- struct mtd_info *mtd;
-- DECLARE_WAITQUEUE(wait, current);
-- wait_queue_head_t wait_q;
-- int ret;
--
-- init_waitqueue_head(&wait_q);
-- mtd = get_mtd_device(NULL, 2);
-- if (!IS_ERR(mtd)) {
-- nettel_erase.mtd = mtd;
-- nettel_erase.callback = nettel_erasecallback;
-- nettel_erase.callback = NULL;
-- nettel_erase.addr = 0;
-- nettel_erase.len = mtd->size;
-- nettel_erase.priv = (u_long) &wait_q;
-- nettel_erase.priv = 0;
--
-- set_current_state(TASK_INTERRUPTIBLE);
-- add_wait_queue(&wait_q, &wait);
--
-- ret = mtd->erase(mtd, &nettel_erase);
-- if (ret) {
-- set_current_state(TASK_RUNNING);
-- remove_wait_queue(&wait_q, &wait);
-- put_mtd_device(mtd);
-- return(ret);
-- }
--
-- schedule(); /* Wait for erase to finish. */
-- remove_wait_queue(&wait_q, &wait);
--
-- put_mtd_device(mtd);
-- }
--
-- return(0);
--}
--
--#else
--
--int nettel_eraseconfig(void)
--{
-- return(0);
--}
--
- #endif
-
- /****************************************************************************/
-
--int __init nettel_init(void)
-+static int __init nettel_init(void)
- {
- volatile unsigned long *amdpar;
- unsigned long amdaddr, maxsize;
-@@ -421,10 +364,6 @@ int __init nettel_init(void)
-
- intel_mtd->owner = THIS_MODULE;
-
--#ifndef CONFIG_BLK_DEV_INITRD
-- ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 1);
--#endif
--
- num_intel_partitions = sizeof(nettel_intel_partitions) /
- sizeof(nettel_intel_partitions[0]);
-
-@@ -477,7 +416,7 @@ out_unmap2:
-
- /****************************************************************************/
-
--void __exit nettel_cleanup(void)
-+static void __exit nettel_cleanup(void)
- {
- #ifdef CONFIG_MTD_CFI_INTELEXT
- unregister_reboot_notifier(&nettel_notifier_block);
-diff --git a/drivers/mtd/maps/pmcmsp-ramroot.c b/drivers/mtd/maps/pmcmsp-ramroot.c
-index 18049bc..30de5c0 100644
---- a/drivers/mtd/maps/pmcmsp-ramroot.c
-+++ b/drivers/mtd/maps/pmcmsp-ramroot.c
-@@ -79,7 +79,6 @@ static int __init init_rrmap(void)
- rr_mtd->owner = THIS_MODULE;
-
- add_mtd_device(rr_mtd);
-- ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, rr_mtd->index);
-
- return 0;
- }
-diff --git a/drivers/mtd/mtd_blkdevs.c b/drivers/mtd/mtd_blkdevs.c
-index ef89780..74d9d30 100644
---- a/drivers/mtd/mtd_blkdevs.c
-+++ b/drivers/mtd/mtd_blkdevs.c
-@@ -24,10 +24,9 @@
- #include <linux/kthread.h>
- #include <asm/uaccess.h>
-
--static LIST_HEAD(blktrans_majors);
-+#include "mtdcore.h"
-
--extern struct mutex mtd_table_mutex;
--extern struct mtd_info *mtd_table[];
-+static LIST_HEAD(blktrans_majors);
-
- struct mtd_blkcore_priv {
- struct task_struct *thread;
-@@ -202,7 +201,7 @@ static int blktrans_ioctl(struct inode *inode, struct file *file,
- }
- }
-
--struct block_device_operations mtd_blktrans_ops = {
-+static struct block_device_operations mtd_blktrans_ops = {
- .owner = THIS_MODULE,
- .open = blktrans_open,
- .release = blktrans_release,
-diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c
-index d091b24..22ed96c 100644
---- a/drivers/mtd/mtdchar.c
-+++ b/drivers/mtd/mtdchar.c
-@@ -136,7 +136,8 @@ static int mtd_close(struct inode *inode, struct file *file)
-
- DEBUG(MTD_DEBUG_LEVEL0, "MTD_close\n");
-
-- if (mtd->sync)
-+ /* Only sync if opened RW */
-+ if ((file->f_mode & 2) && mtd->sync)
- mtd->sync(mtd);
-
- put_mtd_device(mtd);
-diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
-index c153b64..6c2645e 100644
---- a/drivers/mtd/mtdcore.c
-+++ b/drivers/mtd/mtdcore.c
-@@ -22,6 +22,8 @@
-
- #include <linux/mtd/mtd.h>
-
-+#include "mtdcore.h"
-+
- /* These are exported solely for the purpose of mtd_blkdevs.c. You
- should not use them for _anything_ else */
- DEFINE_MUTEX(mtd_table_mutex);
-diff --git a/drivers/mtd/mtdcore.h b/drivers/mtd/mtdcore.h
-new file mode 100644
-index 0000000..a33251f
---- /dev/null
-+++ b/drivers/mtd/mtdcore.h
-@@ -0,0 +1,11 @@
-+/* linux/drivers/mtd/mtdcore.h
-+ *
-+ * Header file for driver private mtdcore exports
-+ *
-+ */
-+
-+/* These are exported solely for the purpose of mtd_blkdevs.c. You
-+ should not use them for _anything_ else */
-+
-+extern struct mutex mtd_table_mutex;
-+extern struct mtd_info *mtd_table[MAX_MTD_DEVICES];
-diff --git a/drivers/mtd/mtdoops.c b/drivers/mtd/mtdoops.c
-new file mode 100644
-index 0000000..cfc28ab
---- /dev/null
-+++ b/drivers/mtd/mtdoops.c
-@@ -0,0 +1,365 @@
-+/*
-+ * MTD Oops/Panic logger
-+ *
-+ * Copyright (C) 2007 Nokia Corporation. All rights reserved.
-+ *
-+ * Author: Richard Purdie <rpurdie@openedhand.com>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
-+ * 02110-1301 USA
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/console.h>
-+#include <linux/vmalloc.h>
-+#include <linux/workqueue.h>
-+#include <linux/sched.h>
-+#include <linux/wait.h>
-+#include <linux/mtd/mtd.h>
-+
-+#define OOPS_PAGE_SIZE 4096
-+
-+static struct mtdoops_context {
-+ int mtd_index;
-+ struct work_struct work;
-+ struct mtd_info *mtd;
-+ int oops_pages;
-+ int nextpage;
-+ int nextcount;
-+
-+ void *oops_buf;
-+ int ready;
-+ int writecount;
-+} oops_cxt;
-+
-+static void mtdoops_erase_callback(struct erase_info *done)
-+{
-+ wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
-+ wake_up(wait_q);
-+}
-+
-+static int mtdoops_erase_block(struct mtd_info *mtd, int offset)
-+{
-+ struct erase_info erase;
-+ DECLARE_WAITQUEUE(wait, current);
-+ wait_queue_head_t wait_q;
-+ int ret;
-+
-+ init_waitqueue_head(&wait_q);
-+ erase.mtd = mtd;
-+ erase.callback = mtdoops_erase_callback;
-+ erase.addr = offset;
-+ if (mtd->erasesize < OOPS_PAGE_SIZE)
-+ erase.len = OOPS_PAGE_SIZE;
-+ else
-+ erase.len = mtd->erasesize;
-+ erase.priv = (u_long)&wait_q;
-+
-+ set_current_state(TASK_INTERRUPTIBLE);
-+ add_wait_queue(&wait_q, &wait);
-+
-+ ret = mtd->erase(mtd, &erase);
-+ if (ret) {
-+ set_current_state(TASK_RUNNING);
-+ remove_wait_queue(&wait_q, &wait);
-+ printk (KERN_WARNING "mtdoops: erase of region [0x%x, 0x%x] "
-+ "on \"%s\" failed\n",
-+ erase.addr, erase.len, mtd->name);
-+ return ret;
-+ }
-+
-+ schedule(); /* Wait for erase to finish. */
-+ remove_wait_queue(&wait_q, &wait);
-+
-+ return 0;
-+}
-+
-+static int mtdoops_inc_counter(struct mtdoops_context *cxt)
-+{
-+ struct mtd_info *mtd = cxt->mtd;
-+ size_t retlen;
-+ u32 count;
-+ int ret;
-+
-+ cxt->nextpage++;
-+ if (cxt->nextpage > cxt->oops_pages)
-+ cxt->nextpage = 0;
-+ cxt->nextcount++;
-+ if (cxt->nextcount == 0xffffffff)
-+ cxt->nextcount = 0;
-+
-+ ret = mtd->read(mtd, cxt->nextpage * OOPS_PAGE_SIZE, 4,
-+ &retlen, (u_char *) &count);
-+ if ((retlen != 4) || (ret < 0)) {
-+ printk(KERN_ERR "mtdoops: Read failure at %d (%d of 4 read)"
-+ ", err %d.\n", cxt->nextpage * OOPS_PAGE_SIZE,
-+ retlen, ret);
-+ return 1;
-+ }
-+
-+ /* See if we need to erase the next block */
-+ if (count != 0xffffffff)
-+ return 1;
-+
-+ printk(KERN_DEBUG "mtdoops: Ready %d, %d (no erase)\n",
-+ cxt->nextpage, cxt->nextcount);
-+ cxt->ready = 1;
-+ return 0;
-+}
-+
-+static void mtdoops_prepare(struct mtdoops_context *cxt)
-+{
-+ struct mtd_info *mtd = cxt->mtd;
-+ int i = 0, j, ret, mod;
-+
-+ /* We were unregistered */
-+ if (!mtd)
-+ return;
-+
-+ mod = (cxt->nextpage * OOPS_PAGE_SIZE) % mtd->erasesize;
-+ if (mod != 0) {
-+ cxt->nextpage = cxt->nextpage + ((mtd->erasesize - mod) / OOPS_PAGE_SIZE);
-+ if (cxt->nextpage > cxt->oops_pages)
-+ cxt->nextpage = 0;
-+ }
-+
-+ while (mtd->block_isbad &&
-+ mtd->block_isbad(mtd, cxt->nextpage * OOPS_PAGE_SIZE)) {
-+badblock:
-+ printk(KERN_WARNING "mtdoops: Bad block at %08x\n",
-+ cxt->nextpage * OOPS_PAGE_SIZE);
-+ i++;
-+ cxt->nextpage = cxt->nextpage + (mtd->erasesize / OOPS_PAGE_SIZE);
-+ if (cxt->nextpage > cxt->oops_pages)
-+ cxt->nextpage = 0;
-+ if (i == (cxt->oops_pages / (mtd->erasesize / OOPS_PAGE_SIZE))) {
-+ printk(KERN_ERR "mtdoops: All blocks bad!\n");
-+ return;
-+ }
-+ }
-+
-+ for (j = 0, ret = -1; (j < 3) && (ret < 0); j++)
-+ ret = mtdoops_erase_block(mtd, cxt->nextpage * OOPS_PAGE_SIZE);
-+
-+ if (ret < 0) {
-+ if (mtd->block_markbad)
-+ mtd->block_markbad(mtd, cxt->nextpage * OOPS_PAGE_SIZE);
-+ goto badblock;
-+ }
-+
-+ printk(KERN_DEBUG "mtdoops: Ready %d, %d \n", cxt->nextpage, cxt->nextcount);
-+
-+ cxt->ready = 1;
-+}
-+
-+static void mtdoops_workfunc(struct work_struct *work)
-+{
-+ struct mtdoops_context *cxt =
-+ container_of(work, struct mtdoops_context, work);
-+
-+ mtdoops_prepare(cxt);
-+}
-+
-+static int find_next_position(struct mtdoops_context *cxt)
-+{
-+ struct mtd_info *mtd = cxt->mtd;
-+ int page, maxpos = 0;
-+ u32 count, maxcount = 0xffffffff;
-+ size_t retlen;
-+
-+ for (page = 0; page < cxt->oops_pages; page++) {
-+ mtd->read(mtd, page * OOPS_PAGE_SIZE, 4, &retlen, (u_char *) &count);
-+ if (count == 0xffffffff)
-+ continue;
-+ if (maxcount == 0xffffffff) {
-+ maxcount = count;
-+ maxpos = page;
-+ } else if ((count < 0x40000000) && (maxcount > 0xc0000000)) {
-+ maxcount = count;
-+ maxpos = page;
-+ } else if ((count > maxcount) && (count < 0xc0000000)) {
-+ maxcount = count;
-+ maxpos = page;
-+ } else if ((count > maxcount) && (count > 0xc0000000)
-+ && (maxcount > 0x80000000)) {
-+ maxcount = count;
-+ maxpos = page;
-+ }
-+ }
-+ if (maxcount == 0xffffffff) {
-+ cxt->nextpage = 0;
-+ cxt->nextcount = 1;
-+ cxt->ready = 1;
-+ printk(KERN_DEBUG "mtdoops: Ready %d, %d (first init)\n",
-+ cxt->nextpage, cxt->nextcount);
-+ return 0;
-+ }
-+
-+ cxt->nextpage = maxpos;
-+ cxt->nextcount = maxcount;
-+
-+ return mtdoops_inc_counter(cxt);
-+}
-+
-+
-+static void mtdoops_notify_add(struct mtd_info *mtd)
-+{
-+ struct mtdoops_context *cxt = &oops_cxt;
-+ int ret;
-+
-+ if ((mtd->index != cxt->mtd_index) || cxt->mtd_index < 0)
-+ return;
-+
-+ if (mtd->size < (mtd->erasesize * 2)) {
-+ printk(KERN_ERR "MTD partition %d not big enough for mtdoops\n",
-+ mtd->index);
-+ return;
-+ }
-+
-+ cxt->mtd = mtd;
-+ cxt->oops_pages = mtd->size / OOPS_PAGE_SIZE;
-+
-+ ret = find_next_position(cxt);
-+ if (ret == 1)
-+ mtdoops_prepare(cxt);
-+
-+ printk(KERN_DEBUG "mtdoops: Attached to MTD device %d\n", mtd->index);
-+}
-+
-+static void mtdoops_notify_remove(struct mtd_info *mtd)
-+{
-+ struct mtdoops_context *cxt = &oops_cxt;
-+
-+ if ((mtd->index != cxt->mtd_index) || cxt->mtd_index < 0)
-+ return;
-+
-+ cxt->mtd = NULL;
-+ flush_scheduled_work();
-+}
-+
-+
-+static void
-+mtdoops_console_write(struct console *co, const char *s, unsigned int count)
-+{
-+ struct mtdoops_context *cxt = co->data;
-+ struct mtd_info *mtd = cxt->mtd;
-+ int i, ret;
-+
-+ if (!cxt->ready || !mtd)
-+ return;
-+
-+ if (!oops_in_progress && cxt->writecount != 0) {
-+ size_t retlen;
-+ if (cxt->writecount < OOPS_PAGE_SIZE)
-+ memset(cxt->oops_buf + cxt->writecount, 0xff,
-+ OOPS_PAGE_SIZE - cxt->writecount);
-+
-+ ret = mtd->write(mtd, cxt->nextpage * OOPS_PAGE_SIZE,
-+ OOPS_PAGE_SIZE, &retlen, cxt->oops_buf);
-+ cxt->ready = 0;
-+ cxt->writecount = 0;
-+
-+ if ((retlen != OOPS_PAGE_SIZE) || (ret < 0))
-+ printk(KERN_ERR "mtdoops: Write failure at %d (%d of %d"
-+ " written), err %d.\n",
-+ cxt->nextpage * OOPS_PAGE_SIZE, retlen,
-+ OOPS_PAGE_SIZE, ret);
-+
-+ ret = mtdoops_inc_counter(cxt);
-+ if (ret == 1)
-+ schedule_work(&cxt->work);
-+ }
-+
-+ if (!oops_in_progress)
-+ return;
-+
-+ if (cxt->writecount == 0) {
-+ u32 *stamp = cxt->oops_buf;
-+ *stamp = cxt->nextcount;
-+ cxt->writecount = 4;
-+ }
-+
-+ if ((count + cxt->writecount) > OOPS_PAGE_SIZE)
-+ count = OOPS_PAGE_SIZE - cxt->writecount;
-+
-+ for (i = 0; i < count; i++, s++)
-+ *((char *)(cxt->oops_buf) + cxt->writecount + i) = *s;
-+
-+ cxt->writecount = cxt->writecount + count;
-+}
-+
-+static int __init mtdoops_console_setup(struct console *co, char *options)
-+{
-+ struct mtdoops_context *cxt = co->data;
-+
-+ if (cxt->mtd_index != -1)
-+ return -EBUSY;
-+ if (co->index == -1)
-+ return -EINVAL;
-+
-+ cxt->mtd_index = co->index;
-+ return 0;
-+}
-+
-+static struct mtd_notifier mtdoops_notifier = {
-+ .add = mtdoops_notify_add,
-+ .remove = mtdoops_notify_remove,
-+};
-+
-+static struct console mtdoops_console = {
-+ .name = "ttyMTD",
-+ .write = mtdoops_console_write,
-+ .setup = mtdoops_console_setup,
-+ .flags = CON_PRINTBUFFER,
-+ .index = -1,
-+ .data = &oops_cxt,
-+};
-+
-+static int __init mtdoops_console_init(void)
-+{
-+ struct mtdoops_context *cxt = &oops_cxt;
-+
-+ cxt->mtd_index = -1;
-+ cxt->oops_buf = vmalloc(OOPS_PAGE_SIZE);
-+
-+ if (!cxt->oops_buf) {
-+ printk(KERN_ERR "Failed to allocate oops buffer workspace\n");
-+ return -ENOMEM;
-+ }
-+
-+ INIT_WORK(&cxt->work, mtdoops_workfunc);
-+
-+ register_console(&mtdoops_console);
-+ register_mtd_user(&mtdoops_notifier);
-+ return 0;
-+}
-+
-+static void __exit mtdoops_console_exit(void)
-+{
-+ struct mtdoops_context *cxt = &oops_cxt;
-+
-+ unregister_mtd_user(&mtdoops_notifier);
-+ unregister_console(&mtdoops_console);
-+ vfree(cxt->oops_buf);
-+}
-+
-+
-+subsys_initcall(mtdoops_console_init);
-+module_exit(mtdoops_console_exit);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Richard Purdie <rpurdie@openedhand.com>");
-+MODULE_DESCRIPTION("MTD Oops/Panic console logger/driver");
-diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
-index f1d60b6..df25cab 100644
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -134,10 +134,10 @@ config MTD_NAND_S3C2410_HWECC
-
- config MTD_NAND_NDFC
- tristate "NDFC NanD Flash Controller"
-- depends on 44x
-+ depends on 4xx
- select MTD_NAND_ECC_SMC
- help
-- NDFC Nand Flash Controllers are integrated in EP44x SoCs
-+ NDFC Nand Flash Controllers are integrated in IBM/AMCC's 4xx SoCs
-
- config MTD_NAND_S3C2410_CLKSTOP
- bool "S3C2410 NAND IDLE clock stop"
-@@ -237,7 +237,7 @@ config MTD_NAND_CAFE
- select REED_SOLOMON
- select REED_SOLOMON_DEC16
- help
-- Use NAND flash attached to the CAFÉ chip designed for the $100
-+ Use NAND flash attached to the CAFÉ chip designed for the OLPC
- laptop.
-
- config MTD_NAND_CS553X
-diff --git a/drivers/mtd/nand/cafe_nand.c b/drivers/mtd/nand/cafe_nand.c
-index cff969d..cca69b3 100644
---- a/drivers/mtd/nand/cafe_nand.c
-+++ b/drivers/mtd/nand/cafe_nand.c
-@@ -821,14 +821,53 @@ static struct pci_device_id cafe_nand_tbl[] = {
-
- MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
-
-+static int cafe_nand_resume(struct pci_dev *pdev)
-+{
-+ uint32_t timing1, timing2, timing3;
-+ uint32_t ctrl;
-+ struct mtd_info *mtd = pci_get_drvdata(pdev);
-+ struct cafe_priv *cafe = mtd->priv;
-+
-+ timing1 = timing2 = timing3 = 0xffffffff;
-+ /* Start off by resetting the NAND controller completely */
-+ cafe_writel(cafe, 1, NAND_RESET);
-+ cafe_writel(cafe, 0, NAND_RESET);
-+ cafe_writel(cafe, timing1, NAND_TIMING1);
-+ cafe_writel(cafe, timing2, NAND_TIMING2);
-+ cafe_writel(cafe, timing3, NAND_TIMING3);
-+ cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
-+
-+ /* Disable master reset, enable NAND clock */
-+ ctrl = cafe_readl(cafe, GLOBAL_CTRL);
-+ ctrl &= 0xffffeff0;
-+ ctrl |= 0x00007000;
-+ cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
-+ cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
-+ cafe_writel(cafe, 0, NAND_DMA_CTRL);
-+ cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
-+ cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
-+
-+ /* Set up DMA address */
-+ cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
-+ if (sizeof(cafe->dmaaddr) > 4)
-+ /* Shift in two parts to shut the compiler up */
-+ cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
-+ else
-+ cafe_writel(cafe, 0, NAND_DMA_ADDR1);
-+
-+ /* Enable NAND IRQ in global IRQ mask register */
-+ cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
-+ return 0;
-+}
-+
- static struct pci_driver cafe_nand_pci_driver = {
- .name = "CAFÉ NAND",
- .id_table = cafe_nand_tbl,
- .probe = cafe_nand_probe,
- .remove = __devexit_p(cafe_nand_remove),
-+ .resume = cafe_nand_resume,
- #ifdef CONFIG_PMx
- .suspend = cafe_nand_suspend,
-- .resume = cafe_nand_resume,
- #endif
- };
-
-diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
-index fd7a8d5..1c0e89f 100644
---- a/drivers/mtd/nand/ndfc.c
-+++ b/drivers/mtd/nand/ndfc.c
-@@ -24,7 +24,11 @@
- #include <linux/platform_device.h>
-
- #include <asm/io.h>
-+#ifdef CONFIG_40x
-+#include <asm/ibm405.h>
-+#else
- #include <asm/ibm44x.h>
-+#endif
-
- struct ndfc_nand_mtd {
- struct mtd_info mtd;
-@@ -230,7 +234,11 @@ static int ndfc_nand_probe(struct platform_device *pdev)
- struct ndfc_controller *ndfc = &ndfc_ctrl;
- unsigned long long phys = settings->ndfc_erpn | res->start;
-
-+#ifndef CONFIG_PHYS_64BIT
-+ ndfc->ndfcbase = ioremap((phys_addr_t)phys, res->end - res->start + 1);
-+#else
- ndfc->ndfcbase = ioremap64(phys, res->end - res->start + 1);
-+#endif
- if (!ndfc->ndfcbase) {
- printk(KERN_ERR "NDFC: ioremap failed\n");
- return -EIO;
-diff --git a/drivers/mtd/onenand/Kconfig b/drivers/mtd/onenand/Kconfig
-index c257d39..cb41cbc 100644
---- a/drivers/mtd/onenand/Kconfig
-+++ b/drivers/mtd/onenand/Kconfig
-@@ -40,4 +40,27 @@ config MTD_ONENAND_OTP
-
- OTP block is fully-guaranteed to be a valid block.
-
-+config MTD_ONENAND_2X_PROGRAM
-+ bool "OneNAND 2X program support"
-+ help
-+ The 2X Program is an extension of Program Operation.
-+ Since the device is equipped with two DataRAMs, and two-plane NAND
-+ Flash memory array, these two component enables simultaneous program
-+ of 4KiB. Plane1 has only even blocks such as block0, block2, block4
-+ while Plane2 has only odd blocks such as block1, block3, block5.
-+ So MTD regards it as 4KiB page size and 256KiB block size
-+
-+ Now the following chips support it. (KFXXX16Q2M)
-+ Demux: KFG2G16Q2M, KFH4G16Q2M, KFW8G16Q2M,
-+ Mux: KFM2G16Q2M, KFN4G16Q2M,
-+
-+ And more recent chips
-+
-+config MTD_ONENAND_SIM
-+ tristate "OneNAND simulator support"
-+ depends on MTD_PARTITIONS
-+ help
-+ The simulator may simulate various OneNAND flash chips for the
-+ OneNAND MTD layer.
-+
- endif # MTD_ONENAND
-diff --git a/drivers/mtd/onenand/Makefile b/drivers/mtd/onenand/Makefile
-index 269cfe4..4d2eacf 100644
---- a/drivers/mtd/onenand/Makefile
-+++ b/drivers/mtd/onenand/Makefile
-@@ -8,4 +8,7 @@ obj-$(CONFIG_MTD_ONENAND) += onenand.o
- # Board specific.
- obj-$(CONFIG_MTD_ONENAND_GENERIC) += generic.o
-
-+# Simulator
-+obj-$(CONFIG_MTD_ONENAND_SIM) += onenand_sim.o
-+
- onenand-objs = onenand_base.o onenand_bbt.o
-diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
-index 0537fac..7d194cf 100644
---- a/drivers/mtd/onenand/onenand_base.c
-+++ b/drivers/mtd/onenand/onenand_base.c
-@@ -206,6 +206,15 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le
- default:
- block = (int) (addr >> this->erase_shift);
- page = (int) (addr >> this->page_shift);
-+
-+ if (ONENAND_IS_2PLANE(this)) {
-+ /* Make the even block number */
-+ block &= ~1;
-+ /* Is it the odd plane? */
-+ if (addr & this->writesize)
-+ block++;
-+ page >>= 1;
-+ }
- page &= this->page_mask;
- break;
- }
-@@ -216,8 +225,12 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le
- value = onenand_bufferram_address(this, block);
- this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2);
-
-- /* Switch to the next data buffer */
-- ONENAND_SET_NEXT_BUFFERRAM(this);
-+ if (ONENAND_IS_2PLANE(this))
-+ /* It is always BufferRAM0 */
-+ ONENAND_SET_BUFFERRAM0(this);
-+ else
-+ /* Switch to the next data buffer */
-+ ONENAND_SET_NEXT_BUFFERRAM(this);
-
- return 0;
- }
-@@ -247,6 +260,8 @@ static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t le
- break;
-
- default:
-+ if (ONENAND_IS_2PLANE(this) && cmd == ONENAND_CMD_PROG)
-+ cmd = ONENAND_CMD_2X_PROG;
- dataram = ONENAND_CURRENT_BUFFERRAM(this);
- break;
- }
-@@ -445,8 +460,9 @@ static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
- struct onenand_chip *this = mtd->priv;
-
- if (ONENAND_CURRENT_BUFFERRAM(this)) {
-+ /* Note: the 'this->writesize' is a real page size */
- if (area == ONENAND_DATARAM)
-- return mtd->writesize;
-+ return this->writesize;
- if (area == ONENAND_SPARERAM)
- return mtd->oobsize;
- }
-@@ -572,6 +588,30 @@ static int onenand_write_bufferram(struct mtd_info *mtd, int area,
- }
-
- /**
-+ * onenand_get_2x_blockpage - [GENERIC] Get blockpage at 2x program mode
-+ * @param mtd MTD data structure
-+ * @param addr address to check
-+ * @return blockpage address
-+ *
-+ * Get blockpage address at 2x program mode
-+ */
-+static int onenand_get_2x_blockpage(struct mtd_info *mtd, loff_t addr)
-+{
-+ struct onenand_chip *this = mtd->priv;
-+ int blockpage, block, page;
-+
-+ /* Calculate the even block number */
-+ block = (int) (addr >> this->erase_shift) & ~1;
-+ /* Is it the odd plane? */
-+ if (addr & this->writesize)
-+ block++;
-+ page = (int) (addr >> (this->page_shift + 1)) & this->page_mask;
-+ blockpage = (block << 7) | page;
-+
-+ return blockpage;
-+}
-+
-+/**
- * onenand_check_bufferram - [GENERIC] Check BufferRAM information
- * @param mtd MTD data structure
- * @param addr address to check
-@@ -585,7 +625,10 @@ static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr)
- int blockpage, found = 0;
- unsigned int i;
-
-- blockpage = (int) (addr >> this->page_shift);
-+ if (ONENAND_IS_2PLANE(this))
-+ blockpage = onenand_get_2x_blockpage(mtd, addr);
-+ else
-+ blockpage = (int) (addr >> this->page_shift);
-
- /* Is there valid data? */
- i = ONENAND_CURRENT_BUFFERRAM(this);
-@@ -625,7 +668,10 @@ static void onenand_update_bufferram(struct mtd_info *mtd, loff_t addr,
- int blockpage;
- unsigned int i;
-
-- blockpage = (int) (addr >> this->page_shift);
-+ if (ONENAND_IS_2PLANE(this))
-+ blockpage = onenand_get_2x_blockpage(mtd, addr);
-+ else
-+ blockpage = (int) (addr >> this->page_shift);
-
- /* Invalidate another BufferRAM */
- i = ONENAND_NEXT_BUFFERRAM(this);
-@@ -734,6 +780,7 @@ static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
- int read = 0, column;
- int thislen;
- int ret = 0, boundary = 0;
-+ int writesize = this->writesize;
-
- DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len);
-
-@@ -754,22 +801,22 @@ static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
- /* Do first load to bufferRAM */
- if (read < len) {
- if (!onenand_check_bufferram(mtd, from)) {
-- this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize);
-+ this->command(mtd, ONENAND_CMD_READ, from, writesize);
- ret = this->wait(mtd, FL_READING);
- onenand_update_bufferram(mtd, from, !ret);
- }
- }
-
-- thislen = min_t(int, mtd->writesize, len - read);
-- column = from & (mtd->writesize - 1);
-- if (column + thislen > mtd->writesize)
-- thislen = mtd->writesize - column;
-+ thislen = min_t(int, writesize, len - read);
-+ column = from & (writesize - 1);
-+ if (column + thislen > writesize)
-+ thislen = writesize - column;
-
- while (!ret) {
- /* If there is more to load then start next load */
- from += thislen;
- if (read + thislen < len) {
-- this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize);
-+ this->command(mtd, ONENAND_CMD_READ, from, writesize);
- /*
- * Chip boundary handling in DDP
- * Now we issued chip 1 read and pointed chip 1
-@@ -794,7 +841,7 @@ static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
- this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2);
- ONENAND_SET_NEXT_BUFFERRAM(this);
- buf += thislen;
-- thislen = min_t(int, mtd->writesize, len - read);
-+ thislen = min_t(int, writesize, len - read);
- column = 0;
- cond_resched();
- /* Now wait for load */
-@@ -1079,7 +1126,7 @@ int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from,
- /* Read more? */
- if (read < len) {
- /* Update Page size */
-- from += mtd->writesize;
-+ from += this->writesize;
- column = 0;
- }
- }
-@@ -1135,12 +1182,12 @@ static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr,
- int thislen, column;
-
- while (len != 0) {
-- thislen = min_t(int, mtd->writesize, len);
-- column = addr & (mtd->writesize - 1);
-- if (column + thislen > mtd->writesize)
-- thislen = mtd->writesize - column;
-+ thislen = min_t(int, this->writesize, len);
-+ column = addr & (this->writesize - 1);
-+ if (column + thislen > this->writesize)
-+ thislen = this->writesize - column;
-
-- this->command(mtd, ONENAND_CMD_READ, addr, mtd->writesize);
-+ this->command(mtd, ONENAND_CMD_READ, addr, this->writesize);
-
- onenand_update_bufferram(mtd, addr, 0);
-
-@@ -1236,6 +1283,10 @@ static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
-
- /* In partial page write we don't update bufferram */
- onenand_update_bufferram(mtd, to, !ret && !subpage);
-+ if (ONENAND_IS_2PLANE(this)) {
-+ ONENAND_SET_BUFFERRAM1(this);
-+ onenand_update_bufferram(mtd, to + this->writesize, !ret && !subpage);
-+ }
-
- if (ret) {
- printk(KERN_ERR "onenand_write: write filaed %d\n", ret);
-@@ -1384,6 +1435,10 @@ static int onenand_do_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
- this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize);
-
- onenand_update_bufferram(mtd, to, 0);
-+ if (ONENAND_IS_2PLANE(this)) {
-+ ONENAND_SET_BUFFERRAM1(this);
-+ onenand_update_bufferram(mtd, to + this->writesize, 0);
-+ }
-
- ret = this->wait(mtd, FL_WRITING);
- if (ret) {
-@@ -2107,6 +2162,7 @@ static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
- *
- * Check and set OneNAND features
- * - lock scheme
-+ * - two plane
- */
- static void onenand_check_features(struct mtd_info *mtd)
- {
-@@ -2118,19 +2174,35 @@ static void onenand_check_features(struct mtd_info *mtd)
- process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT;
-
- /* Lock scheme */
-- if (density >= ONENAND_DEVICE_DENSITY_1Gb) {
-+ switch (density) {
-+ case ONENAND_DEVICE_DENSITY_4Gb:
-+ this->options |= ONENAND_HAS_2PLANE;
-+
-+ case ONENAND_DEVICE_DENSITY_2Gb:
-+ /* 2Gb DDP don't have 2 plane */
-+ if (!ONENAND_IS_DDP(this))
-+ this->options |= ONENAND_HAS_2PLANE;
-+ this->options |= ONENAND_HAS_UNLOCK_ALL;
-+
-+ case ONENAND_DEVICE_DENSITY_1Gb:
- /* A-Die has all block unlock */
-- if (process) {
-- printk(KERN_DEBUG "Chip support all block unlock\n");
-+ if (process)
- this->options |= ONENAND_HAS_UNLOCK_ALL;
-- }
-- } else {
-- /* Some OneNAND has continues lock scheme */
-- if (!process) {
-- printk(KERN_DEBUG "Lock scheme is Continues Lock\n");
-+ break;
-+
-+ default:
-+ /* Some OneNAND has continuous lock scheme */
-+ if (!process)
- this->options |= ONENAND_HAS_CONT_LOCK;
-- }
-+ break;
- }
-+
-+ if (this->options & ONENAND_HAS_CONT_LOCK)
-+ printk(KERN_DEBUG "Lock scheme is Continuous Lock\n");
-+ if (this->options & ONENAND_HAS_UNLOCK_ALL)
-+ printk(KERN_DEBUG "Chip support all block unlock\n");
-+ if (this->options & ONENAND_HAS_2PLANE)
-+ printk(KERN_DEBUG "Chip has 2 plane\n");
- }
-
- /**
-@@ -2257,6 +2329,8 @@ static int onenand_probe(struct mtd_info *mtd)
- this->erase_shift = ffs(mtd->erasesize) - 1;
- this->page_shift = ffs(mtd->writesize) - 1;
- this->page_mask = (1 << (this->erase_shift - this->page_shift)) - 1;
-+ /* It's real page size */
-+ this->writesize = mtd->writesize;
-
- /* REVIST: Multichip handling */
-
-@@ -2265,6 +2339,17 @@ static int onenand_probe(struct mtd_info *mtd)
- /* Check OneNAND features */
- onenand_check_features(mtd);
-
-+ /*
-+ * We emulate the 4KiB page and 256KiB erase block size
-+ * But oobsize is still 64 bytes.
-+ * It is only valid if you turn on 2X program support,
-+ * Otherwise it will be ignored by compiler.
-+ */
-+ if (ONENAND_IS_2PLANE(this)) {
-+ mtd->writesize <<= 1;
-+ mtd->erasesize <<= 1;
-+ }
-+
- return 0;
- }
-
-diff --git a/drivers/mtd/onenand/onenand_sim.c b/drivers/mtd/onenand/onenand_sim.c
-new file mode 100644
-index 0000000..b806673
---- /dev/null
-+++ b/drivers/mtd/onenand/onenand_sim.c
-@@ -0,0 +1,495 @@
-+/*
-+ * linux/drivers/mtd/onenand/onenand_sim.c
-+ *
-+ * The OneNAND simulator
-+ *
-+ * Copyright © 2005-2007 Samsung Electronics
-+ * Kyungmin Park <kyungmin.park@samsung.com>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+#include <linux/vmalloc.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/onenand.h>
-+
-+#include <linux/io.h>
-+
-+#ifndef CONFIG_ONENAND_SIM_MANUFACTURER
-+#define CONFIG_ONENAND_SIM_MANUFACTURER 0xec
-+#endif
-+#ifndef CONFIG_ONENAND_SIM_DEVICE_ID
-+#define CONFIG_ONENAND_SIM_DEVICE_ID 0x04
-+#endif
-+#ifndef CONFIG_ONENAND_SIM_VERSION_ID
-+#define CONFIG_ONENAND_SIM_VERSION_ID 0x1e
-+#endif
-+
-+static int manuf_id = CONFIG_ONENAND_SIM_MANUFACTURER;
-+static int device_id = CONFIG_ONENAND_SIM_DEVICE_ID;
-+static int version_id = CONFIG_ONENAND_SIM_VERSION_ID;
-+
-+struct onenand_flash {
-+ void __iomem *base;
-+ void __iomem *data;
-+};
-+
-+#define ONENAND_CORE(flash) (flash->data)
-+#define ONENAND_CORE_SPARE(flash, this, offset) \
-+ ((flash->data) + (this->chipsize) + (offset >> 5))
-+
-+#define ONENAND_MAIN_AREA(this, offset) \
-+ (this->base + ONENAND_DATARAM + offset)
-+
-+#define ONENAND_SPARE_AREA(this, offset) \
-+ (this->base + ONENAND_SPARERAM + offset)
-+
-+#define ONENAND_GET_WP_STATUS(this) \
-+ (readw(this->base + ONENAND_REG_WP_STATUS))
-+
-+#define ONENAND_SET_WP_STATUS(v, this) \
-+ (writew(v, this->base + ONENAND_REG_WP_STATUS))
-+
-+/* It has all 0xff chars */
-+#define MAX_ONENAND_PAGESIZE (2048 + 64)
-+static unsigned char *ffchars;
-+
-+static struct mtd_partition os_partitions[] = {
-+ {
-+ .name = "OneNAND simulator partition",
-+ .offset = 0,
-+ .size = MTDPART_SIZ_FULL,
-+ },
-+};
-+
-+/*
-+ * OneNAND simulator mtd
-+ */
-+struct onenand_info {
-+ struct mtd_info mtd;
-+ struct mtd_partition *parts;
-+ struct onenand_chip onenand;
-+ struct onenand_flash flash;
-+};
-+
-+struct onenand_info *info;
-+
-+#define DPRINTK(format, args...) \
-+do { \
-+ printk(KERN_DEBUG "%s[%d]: " format "\n", __func__, \
-+ __LINE__, ##args); \
-+} while (0)
-+
-+/**
-+ * onenand_lock_handle - Handle Lock scheme
-+ * @param this OneNAND device structure
-+ * @param cmd The command to be sent
-+ *
-+ * Send lock command to OneNAND device.
-+ * The lock scheme is depends on chip type.
-+ */
-+static void onenand_lock_handle(struct onenand_chip *this, int cmd)
-+{
-+ int block_lock_scheme;
-+ int status;
-+
-+ status = ONENAND_GET_WP_STATUS(this);
-+ block_lock_scheme = !(this->options & ONENAND_HAS_CONT_LOCK);
-+
-+ switch (cmd) {
-+ case ONENAND_CMD_UNLOCK:
-+ if (block_lock_scheme)
-+ ONENAND_SET_WP_STATUS(ONENAND_WP_US, this);
-+ else
-+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_US, this);
-+ break;
-+
-+ case ONENAND_CMD_LOCK:
-+ if (block_lock_scheme)
-+ ONENAND_SET_WP_STATUS(ONENAND_WP_LS, this);
-+ else
-+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_LS, this);
-+ break;
-+
-+ case ONENAND_CMD_LOCK_TIGHT:
-+ if (block_lock_scheme)
-+ ONENAND_SET_WP_STATUS(ONENAND_WP_LTS, this);
-+ else
-+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_LTS, this);
-+ break;
-+
-+ default:
-+ break;
-+ }
-+}
-+
-+/**
-+ * onenand_bootram_handle - Handle BootRAM area
-+ * @param this OneNAND device structure
-+ * @param cmd The command to be sent
-+ *
-+ * Emulate BootRAM area. It is possible to do basic operation using BootRAM.
-+ */
-+static void onenand_bootram_handle(struct onenand_chip *this, int cmd)
-+{
-+ switch (cmd) {
-+ case ONENAND_CMD_READID:
-+ writew(manuf_id, this->base);
-+ writew(device_id, this->base + 2);
-+ writew(version_id, this->base + 4);
-+ break;
-+
-+ default:
-+ /* REVIST: Handle other commands */
-+ break;
-+ }
-+}
-+
-+/**
-+ * onenand_update_interrupt - Set interrupt register
-+ * @param this OneNAND device structure
-+ * @param cmd The command to be sent
-+ *
-+ * Update interrupt register. The status is depends on command.
-+ */
-+static void onenand_update_interrupt(struct onenand_chip *this, int cmd)
-+{
-+ int interrupt = ONENAND_INT_MASTER;
-+
-+ switch (cmd) {
-+ case ONENAND_CMD_READ:
-+ case ONENAND_CMD_READOOB:
-+ interrupt |= ONENAND_INT_READ;
-+ break;
-+
-+ case ONENAND_CMD_PROG:
-+ case ONENAND_CMD_PROGOOB:
-+ interrupt |= ONENAND_INT_WRITE;
-+ break;
-+
-+ case ONENAND_CMD_ERASE:
-+ interrupt |= ONENAND_INT_ERASE;
-+ break;
-+
-+ case ONENAND_CMD_RESET:
-+ interrupt |= ONENAND_INT_RESET;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ writew(interrupt, this->base + ONENAND_REG_INTERRUPT);
-+}
-+
-+/**
-+ * onenand_check_overwrite - Check over-write if happend
-+ * @param dest The destination pointer
-+ * @param src The source pointer
-+ * @param count The length to be check
-+ * @return 0 on same, otherwise 1
-+ *
-+ * Compare the source with destination
-+ */
-+static int onenand_check_overwrite(void *dest, void *src, size_t count)
-+{
-+ unsigned int *s = (unsigned int *) src;
-+ unsigned int *d = (unsigned int *) dest;
-+ int i;
-+
-+ count >>= 2;
-+ for (i = 0; i < count; i++)
-+ if ((*s++ ^ *d++) != 0)
-+ return 1;
-+
-+ return 0;
-+}
-+
-+/**
-+ * onenand_data_handle - Handle OneNAND Core and DataRAM
-+ * @param this OneNAND device structure
-+ * @param cmd The command to be sent
-+ * @param dataram Which dataram used
-+ * @param offset The offset to OneNAND Core
-+ *
-+ * Copy data from OneNAND Core to DataRAM (read)
-+ * Copy data from DataRAM to OneNAND Core (write)
-+ * Erase the OneNAND Core (erase)
-+ */
-+static void onenand_data_handle(struct onenand_chip *this, int cmd,
-+ int dataram, unsigned int offset)
-+{
-+ struct mtd_info *mtd = &info->mtd;
-+ struct onenand_flash *flash = this->priv;
-+ int main_offset, spare_offset;
-+ void __iomem *src;
-+ void __iomem *dest;
-+ unsigned int i;
-+
-+ if (dataram) {
-+ main_offset = mtd->writesize;
-+ spare_offset = mtd->oobsize;
-+ } else {
-+ main_offset = 0;
-+ spare_offset = 0;
-+ }
-+
-+ switch (cmd) {
-+ case ONENAND_CMD_READ:
-+ src = ONENAND_CORE(flash) + offset;
-+ dest = ONENAND_MAIN_AREA(this, main_offset);
-+ memcpy(dest, src, mtd->writesize);
-+ /* Fall through */
-+
-+ case ONENAND_CMD_READOOB:
-+ src = ONENAND_CORE_SPARE(flash, this, offset);
-+ dest = ONENAND_SPARE_AREA(this, spare_offset);
-+ memcpy(dest, src, mtd->oobsize);
-+ break;
-+
-+ case ONENAND_CMD_PROG:
-+ src = ONENAND_MAIN_AREA(this, main_offset);
-+ dest = ONENAND_CORE(flash) + offset;
-+ /* To handle partial write */
-+ for (i = 0; i < (1 << mtd->subpage_sft); i++) {
-+ int off = i * this->subpagesize;
-+ if (!memcmp(src + off, ffchars, this->subpagesize))
-+ continue;
-+ if (memcmp(dest + off, ffchars, this->subpagesize) &&
-+ onenand_check_overwrite(dest + off, src + off, this->subpagesize))
-+ printk(KERN_ERR "over-write happend at 0x%08x\n", offset);
-+ memcpy(dest + off, src + off, this->subpagesize);
-+ }
-+ /* Fall through */
-+
-+ case ONENAND_CMD_PROGOOB:
-+ src = ONENAND_SPARE_AREA(this, spare_offset);
-+ /* Check all data is 0xff chars */
-+ if (!memcmp(src, ffchars, mtd->oobsize))
-+ break;
-+
-+ dest = ONENAND_CORE_SPARE(flash, this, offset);
-+ if (memcmp(dest, ffchars, mtd->oobsize) &&
-+ onenand_check_overwrite(dest, src, mtd->oobsize))
-+ printk(KERN_ERR "OOB: over-write happend at 0x%08x\n",
-+ offset);
-+ memcpy(dest, src, mtd->oobsize);
-+ break;
-+
-+ case ONENAND_CMD_ERASE:
-+ memset(ONENAND_CORE(flash) + offset, 0xff, mtd->erasesize);
-+ memset(ONENAND_CORE_SPARE(flash, this, offset), 0xff,
-+ (mtd->erasesize >> 5));
-+ break;
-+
-+ default:
-+ break;
-+ }
-+}
-+
-+/**
-+ * onenand_command_handle - Handle command
-+ * @param this OneNAND device structure
-+ * @param cmd The command to be sent
-+ *
-+ * Emulate OneNAND command.
-+ */
-+static void onenand_command_handle(struct onenand_chip *this, int cmd)
-+{
-+ unsigned long offset = 0;
-+ int block = -1, page = -1, bufferram = -1;
-+ int dataram = 0;
-+
-+ switch (cmd) {
-+ case ONENAND_CMD_UNLOCK:
-+ case ONENAND_CMD_LOCK:
-+ case ONENAND_CMD_LOCK_TIGHT:
-+ case ONENAND_CMD_UNLOCK_ALL:
-+ onenand_lock_handle(this, cmd);
-+ break;
-+
-+ case ONENAND_CMD_BUFFERRAM:
-+ /* Do nothing */
-+ return;
-+
-+ default:
-+ block = (int) readw(this->base + ONENAND_REG_START_ADDRESS1);
-+ if (block & (1 << ONENAND_DDP_SHIFT)) {
-+ block &= ~(1 << ONENAND_DDP_SHIFT);
-+ /* The half of chip block */
-+ block += this->chipsize >> (this->erase_shift + 1);
-+ }
-+ if (cmd == ONENAND_CMD_ERASE)
-+ break;
-+
-+ page = (int) readw(this->base + ONENAND_REG_START_ADDRESS8);
-+ page = (page >> ONENAND_FPA_SHIFT);
-+ bufferram = (int) readw(this->base + ONENAND_REG_START_BUFFER);
-+ bufferram >>= ONENAND_BSA_SHIFT;
-+ bufferram &= ONENAND_BSA_DATARAM1;
-+ dataram = (bufferram == ONENAND_BSA_DATARAM1) ? 1 : 0;
-+ break;
-+ }
-+
-+ if (block != -1)
-+ offset += block << this->erase_shift;
-+
-+ if (page != -1)
-+ offset += page << this->page_shift;
-+
-+ onenand_data_handle(this, cmd, dataram, offset);
-+
-+ onenand_update_interrupt(this, cmd);
-+}
-+
-+/**
-+ * onenand_writew - [OneNAND Interface] Emulate write operation
-+ * @param value value to write
-+ * @param addr address to write
-+ *
-+ * Write OneNAND register with value
-+ */
-+static void onenand_writew(unsigned short value, void __iomem * addr)
-+{
-+ struct onenand_chip *this = info->mtd.priv;
-+
-+ /* BootRAM handling */
-+ if (addr < this->base + ONENAND_DATARAM) {
-+ onenand_bootram_handle(this, value);
-+ return;
-+ }
-+ /* Command handling */
-+ if (addr == this->base + ONENAND_REG_COMMAND)
-+ onenand_command_handle(this, value);
-+
-+ writew(value, addr);
-+}
-+
-+/**
-+ * flash_init - Initialize OneNAND simulator
-+ * @param flash OneNAND simulaotr data strucutres
-+ *
-+ * Initialize OneNAND simulator.
-+ */
-+static int __init flash_init(struct onenand_flash *flash)
-+{
-+ int density, size;
-+ int buffer_size;
-+
-+ flash->base = kzalloc(131072, GFP_KERNEL);
-+ if (!flash->base) {
-+ printk(KERN_ERR "Unable to allocate base address.\n");
-+ return -ENOMEM;
-+ }
-+
-+ density = device_id >> ONENAND_DEVICE_DENSITY_SHIFT;
-+ size = ((16 << 20) << density);
-+
-+ ONENAND_CORE(flash) = vmalloc(size + (size >> 5));
-+ if (!ONENAND_CORE(flash)) {
-+ printk(KERN_ERR "Unable to allocate nand core address.\n");
-+ kfree(flash->base);
-+ return -ENOMEM;
-+ }
-+
-+ memset(ONENAND_CORE(flash), 0xff, size + (size >> 5));
-+
-+ /* Setup registers */
-+ writew(manuf_id, flash->base + ONENAND_REG_MANUFACTURER_ID);
-+ writew(device_id, flash->base + ONENAND_REG_DEVICE_ID);
-+ writew(version_id, flash->base + ONENAND_REG_VERSION_ID);
-+
-+ if (density < 2)
-+ buffer_size = 0x0400; /* 1KiB page */
-+ else
-+ buffer_size = 0x0800; /* 2KiB page */
-+ writew(buffer_size, flash->base + ONENAND_REG_DATA_BUFFER_SIZE);
-+
-+ return 0;
-+}
-+
-+/**
-+ * flash_exit - Clean up OneNAND simulator
-+ * @param flash OneNAND simulaotr data strucutres
-+ *
-+ * Clean up OneNAND simulator.
-+ */
-+static void flash_exit(struct onenand_flash *flash)
-+{
-+ vfree(ONENAND_CORE(flash));
-+ kfree(flash->base);
-+ kfree(flash);
-+}
-+
-+static int __init onenand_sim_init(void)
-+{
-+ /* Allocate all 0xff chars pointer */
-+ ffchars = kmalloc(MAX_ONENAND_PAGESIZE, GFP_KERNEL);
-+ if (!ffchars) {
-+ printk(KERN_ERR "Unable to allocate ff chars.\n");
-+ return -ENOMEM;
-+ }
-+ memset(ffchars, 0xff, MAX_ONENAND_PAGESIZE);
-+
-+ /* Allocate OneNAND simulator mtd pointer */
-+ info = kzalloc(sizeof(struct onenand_info), GFP_KERNEL);
-+ if (!info) {
-+ printk(KERN_ERR "Unable to allocate core structures.\n");
-+ kfree(ffchars);
-+ return -ENOMEM;
-+ }
-+
-+ /* Override write_word function */
-+ info->onenand.write_word = onenand_writew;
-+
-+ if (flash_init(&info->flash)) {
-+ printk(KERN_ERR "Unable to allocat flash.\n");
-+ kfree(ffchars);
-+ kfree(info);
-+ return -ENOMEM;
-+ }
-+
-+ info->parts = os_partitions;
-+
-+ info->onenand.base = info->flash.base;
-+ info->onenand.priv = &info->flash;
-+
-+ info->mtd.name = "OneNAND simulator";
-+ info->mtd.priv = &info->onenand;
-+ info->mtd.owner = THIS_MODULE;
-+
-+ if (onenand_scan(&info->mtd, 1)) {
-+ flash_exit(&info->flash);
-+ kfree(ffchars);
-+ kfree(info);
-+ return -ENXIO;
-+ }
-+
-+ add_mtd_partitions(&info->mtd, info->parts, ARRAY_SIZE(os_partitions));
-+
-+ return 0;
-+}
-+
-+static void __exit onenand_sim_exit(void)
-+{
-+ struct onenand_chip *this = info->mtd.priv;
-+ struct onenand_flash *flash = this->priv;
-+
-+ onenand_release(&info->mtd);
-+ flash_exit(flash);
-+ kfree(ffchars);
-+ kfree(info);
-+}
-+
-+module_init(onenand_sim_init);
-+module_exit(onenand_sim_exit);
-+
-+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
-+MODULE_DESCRIPTION("The OneNAND flash simulator");
-+MODULE_LICENSE("GPL");
-diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
-index 1938d6d..cc01dbd 100644
---- a/drivers/net/forcedeth.c
-+++ b/drivers/net/forcedeth.c
-@@ -3556,10 +3556,12 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
- }
- if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
- if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
-+ pci_intx(np->pci_dev, 0);
- np->msi_flags |= NV_MSI_ENABLED;
- if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
- printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
- pci_disable_msi(np->pci_dev);
-+ pci_intx(np->pci_dev, 1);
- np->msi_flags &= ~NV_MSI_ENABLED;
- goto out_err;
- }
-@@ -3601,6 +3603,7 @@ static void nv_free_irq(struct net_device *dev)
- free_irq(np->pci_dev->irq, dev);
- if (np->msi_flags & NV_MSI_ENABLED) {
- pci_disable_msi(np->pci_dev);
-+ pci_intx(np->pci_dev, 1);
- np->msi_flags &= ~NV_MSI_ENABLED;
- }
- }
-diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
-index 7dcaa09..eb69d4d 100644
---- a/drivers/pci/quirks.c
-+++ b/drivers/pci/quirks.c
-@@ -1390,6 +1390,17 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
- DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
-
- /*
-+ * According to Tom Sylla, the Geode does not support PCI power management
-+ * transition, so we shouldn't need the D3hot delay.
-+ */
-+static void __init quirk_geode_pci_pm(struct pci_dev *dev)
-+{
-+ pci_pm_d3_delay = 0;
-+}
-+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, quirk_geode_pci_pm);
-+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_geode_pci_pm);
-+
-+/*
- * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
- * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
- * Re-allocate the region if needed...
-diff --git a/drivers/sysprof/Kconfig b/drivers/sysprof/Kconfig
-new file mode 100644
-index 0000000..b99c13a
---- /dev/null
-+++ b/drivers/sysprof/Kconfig
-@@ -0,0 +1,12 @@
-+
-+menu "Sysprof"
-+
-+config SYSPROF
-+ tristate "Sysprof support"
-+ help
-+ Say M here to include the sysprof-module.
-+
-+ Sysprof is a sampling profiler that uses a kernel module,
-+ sysprof-module, to generate stacktraces which are then interpreted by
-+ the userspace program "sysprof".
-+endmenu
-diff --git a/drivers/sysprof/Makefile b/drivers/sysprof/Makefile
-new file mode 100644
-index 0000000..cd465e9
---- /dev/null
-+++ b/drivers/sysprof/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_SYSPROF) += sysprof-module.o
-diff --git a/drivers/sysprof/config.h b/drivers/sysprof/config.h
-new file mode 100644
-index 0000000..bb62689
---- /dev/null
-+++ b/drivers/sysprof/config.h
-@@ -0,0 +1,23 @@
-+/* config.h. Generated by configure. */
-+/* config.h.in. Generated from configure.ac by autoheader. */
-+
-+/* Look for global separate debug info in this path */
-+#define DEBUGDIR "/usr/local/lib/debug"
-+
-+/* Define to 1 if you have the `iberty' library (-liberty). */
-+/* #undef HAVE_LIBIBERTY */
-+
-+/* Define to the address where bug reports for this package should be sent. */
-+#define PACKAGE_BUGREPORT ""
-+
-+/* Define to the full name of this package. */
-+#define PACKAGE_NAME "sysprof"
-+
-+/* Define to the full name and version of this package. */
-+#define PACKAGE_STRING "sysprof 1.0.8"
-+
-+/* Define to the one symbol short name of this package. */
-+#define PACKAGE_TARNAME "sysprof"
-+
-+/* Define to the version of this package. */
-+#define PACKAGE_VERSION "1.0.8"
-diff --git a/drivers/sysprof/sysprof-module.c b/drivers/sysprof/sysprof-module.c
-new file mode 100644
-index 0000000..36e0b51
---- /dev/null
-+++ b/drivers/sysprof/sysprof-module.c
-@@ -0,0 +1,271 @@
-+/* -*- c-basic-offset: 8 -*- */
-+
-+/* Sysprof -- Sampling, systemwide CPU profiler
-+ * Copyright 2004, Red Hat, Inc.
-+ * Copyright 2004, 2005, Soeren Sandmann
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+#ifdef CONFIG_SMP
-+# define __SMP__
-+#endif
-+#include <asm/atomic.h>
-+#include <linux/kernel.h> /* Needed for KERN_ALERT */
-+#include <linux/module.h> /* Needed by all modules */
-+#include <linux/sched.h>
-+
-+#include <linux/proc_fs.h>
-+#include <asm/uaccess.h>
-+#include <linux/poll.h>
-+#include <linux/highmem.h>
-+#include <linux/pagemap.h>
-+#include <linux/profile.h>
-+
-+#include "sysprof-module.h"
-+
-+#include "config.h"
-+
-+#include <linux/version.h>
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
-+#include <linux/config.h>
-+#endif
-+
-+#if !CONFIG_PROFILING
-+# error Sysprof needs a kernel with profiling support compiled in.
-+#endif
-+
-+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
-+# error Sysprof needs a Linux 2.6.11 kernel or later
-+#endif
-+#include <linux/kallsyms.h>
-+
-+MODULE_LICENSE("GPL");
-+MODULE_AUTHOR("Soeren Sandmann (sandmann@daimi.au.dk)");
-+
-+#define SAMPLES_PER_SECOND (200)
-+#define INTERVAL ((HZ <= SAMPLES_PER_SECOND)? 1 : (HZ / SAMPLES_PER_SECOND))
-+#define N_TRACES 256
-+
-+static SysprofStackTrace stack_traces[N_TRACES];
-+static SysprofStackTrace * head = &stack_traces[0];
-+static SysprofStackTrace * tail = &stack_traces[0];
-+DECLARE_WAIT_QUEUE_HEAD (wait_for_trace);
-+DECLARE_WAIT_QUEUE_HEAD (wait_for_exit);
-+
-+/* Macro the names of the registers that are used on each architecture */
-+#if defined(CONFIG_X86_64)
-+# define REG_FRAME_PTR rbp
-+# define REG_INS_PTR rip
-+# define REG_STACK_PTR rsp
-+#elif defined(CONFIG_X86)
-+# define REG_FRAME_PTR ebp
-+# define REG_INS_PTR eip
-+# define REG_STACK_PTR esp
-+#else
-+# error Sysprof only supports the i386 and x86-64 architectures
-+#endif
-+
-+typedef struct userspace_reader userspace_reader;
-+struct userspace_reader
-+{
-+ struct task_struct *task;
-+ unsigned long cache_address;
-+ unsigned long *cache;
-+};
-+
-+typedef struct StackFrame StackFrame;
-+struct StackFrame {
-+ unsigned long next;
-+ unsigned long return_address;
-+};
-+
-+struct work_struct work;
-+
-+static int
-+read_frame (void *frame_pointer, StackFrame *frame)
-+{
-+#if 0
-+ /* This is commented out because we seem to be called with
-+ * (current_thread_info()->addr_limit.seg)) == 0
-+ * which means access_ok() _always_ fails.
-+ *
-+ * Not sure why (or if) this isn't the case for oprofile
-+ */
-+ if (!access_ok(VERIFY_READ, frame_pointer, sizeof(StackFrame)))
-+ return 1;
-+#endif
-+
-+ if (__copy_from_user_inatomic (
-+ frame, frame_pointer, sizeof (StackFrame)))
-+ return 1;
-+
-+ return 0;
-+}
-+
-+DEFINE_PER_CPU(int, n_samples);
-+
-+static int
-+timer_notify (struct pt_regs *regs)
-+{
-+ SysprofStackTrace *trace = head;
-+ int i;
-+ int is_user;
-+ static atomic_t in_timer_notify = ATOMIC_INIT(1);
-+ int n;
-+
-+ n = ++get_cpu_var(n_samples);
-+ put_cpu_var(n_samples);
-+
-+ if (n % INTERVAL != 0)
-+ return 0;
-+
-+ /* 0: locked, 1: unlocked */
-+
-+ if (!atomic_dec_and_test(&in_timer_notify))
-+ goto out;
-+
-+ is_user = user_mode(regs);
-+
-+ if (!current || current->pid == 0)
-+ goto out;
-+
-+ if (is_user && current->state != TASK_RUNNING)
-+ goto out;
-+
-+ if (!is_user)
-+ {
-+ /* kernel */
-+
-+ trace->pid = current->pid;
-+ trace->truncated = 0;
-+ trace->n_addresses = 1;
-+
-+ /* 0x1 is taken by sysprof to mean "in kernel" */
-+ trace->addresses[0] = (void *)0x1;
-+ }
-+ else
-+ {
-+ StackFrame *frame_pointer;
-+ StackFrame frame;
-+ memset(trace, 0, sizeof (SysprofStackTrace));
-+
-+ trace->pid = current->pid;
-+ trace->truncated = 0;
-+
-+ i = 0;
-+
-+ trace->addresses[i++] = (void *)regs->REG_INS_PTR;
-+
-+ frame_pointer = (void *)regs->REG_FRAME_PTR;
-+
-+ while (read_frame (frame_pointer, &frame) == 0 &&
-+ i < SYSPROF_MAX_ADDRESSES &&
-+ (unsigned long)frame_pointer >= regs->REG_STACK_PTR)
-+ {
-+ trace->addresses[i++] = (void *)frame.return_address;
-+ frame_pointer = (StackFrame *)frame.next;
-+ }
-+
-+ trace->n_addresses = i;
-+
-+ if (i == SYSPROF_MAX_ADDRESSES)
-+ trace->truncated = 1;
-+ else
-+ trace->truncated = 0;
-+ }
-+
-+ if (head++ == &stack_traces[N_TRACES - 1])
-+ head = &stack_traces[0];
-+
-+ wake_up (&wait_for_trace);
-+
-+out:
-+ atomic_inc(&in_timer_notify);
-+ return 0;
-+}
-+
-+static int
-+procfile_read(char *buffer,
-+ char **buffer_location,
-+ off_t offset,
-+ int buffer_len,
-+ int *eof,
-+ void *data)
-+{
-+ if (head == tail)
-+ return -EWOULDBLOCK;
-+
-+ *buffer_location = (char *)tail;
-+
-+ BUG_ON(tail->pid == 0);
-+
-+ if (tail++ == &stack_traces[N_TRACES - 1])
-+ tail = &stack_traces[0];
-+
-+ return sizeof (SysprofStackTrace);
-+}
-+
-+struct proc_dir_entry *trace_proc_file;
-+static unsigned int
-+procfile_poll(struct file *filp, poll_table *poll_table)
-+{
-+ if (head != tail)
-+ return POLLIN | POLLRDNORM;
-+
-+ poll_wait(filp, &wait_for_trace, poll_table);
-+
-+ if (head != tail)
-+ return POLLIN | POLLRDNORM;
-+
-+ return 0;
-+}
-+
-+int
-+init_module(void)
-+{
-+ static struct file_operations fops;
-+
-+ trace_proc_file =
-+ create_proc_entry ("sysprof-trace", S_IFREG | S_IRUGO, &proc_root);
-+
-+ if (!trace_proc_file)
-+ return 1;
-+
-+ fops = *trace_proc_file->proc_fops;
-+ fops.poll = procfile_poll;
-+
-+ trace_proc_file->read_proc = procfile_read;
-+ trace_proc_file->proc_fops = &fops;
-+ trace_proc_file->size = sizeof (SysprofStackTrace);
-+
-+ register_timer_hook (timer_notify);
-+
-+ printk(KERN_ALERT "sysprof: loaded (%s)\n", PACKAGE_VERSION);
-+
-+ return 0;
-+}
-+
-+void
-+cleanup_module(void)
-+{
-+ unregister_timer_hook (timer_notify);
-+
-+ remove_proc_entry("sysprof-trace", &proc_root);
-+
-+ printk(KERN_ALERT "sysprof: unloaded\n");
-+}
-+
-diff --git a/drivers/sysprof/sysprof-module.h b/drivers/sysprof/sysprof-module.h
-new file mode 100644
-index 0000000..66a11ae
---- /dev/null
-+++ b/drivers/sysprof/sysprof-module.h
-@@ -0,0 +1,37 @@
-+/* Sysprof -- Sampling, systemwide CPU profiler
-+ * Copyright 2004, Red Hat, Inc.
-+ * Copyright 2004, 2005, Soeren Sandmann
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+#ifndef SYSPROF_MODULE_H
-+#define SYSPROF_MODULE_H
-+
-+typedef struct SysprofStackTrace SysprofStackTrace;
-+
-+#define SYSPROF_MAX_ADDRESSES 512
-+
-+struct SysprofStackTrace
-+{
-+ int pid; /* -1 if in kernel */
-+ int truncated;
-+ int n_addresses; /* note: this can be 1 if the process was compiled
-+ * with -fomit-frame-pointer or is otherwise weird
-+ */
-+ void *addresses[SYSPROF_MAX_ADDRESSES];
-+};
-+
-+#endif
-diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
-index 5216c11..3e3df7e 100644
---- a/drivers/video/Kconfig
-+++ b/drivers/video/Kconfig
-@@ -594,7 +594,7 @@ config FB_TGA
-
- config FB_VESA
- bool "VESA VGA graphics support"
-- depends on (FB = y) && X86
-+ depends on (FB = y) && X86 && !VGA_NOPROBE
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
-@@ -1028,7 +1028,7 @@ config FB_CARILLO_RANCH
-
- config FB_INTEL
- tristate "Intel 830M/845G/852GM/855GM/865G/915G/945G support (EXPERIMENTAL)"
-- depends on FB && EXPERIMENTAL && PCI && X86
-+ depends on FB && EXPERIMENTAL && PCI && X86 && !VGA_NOPROBE
- select AGP
- select AGP_INTEL
- select FB_MODE_HELPERS
-@@ -1383,7 +1383,7 @@ config FB_SAVAGE_ACCEL
-
- config FB_SIS
- tristate "SiS/XGI display support"
-- depends on FB && PCI
-+ depends on FB && PCI && !VGA_NOPROBE
- select FB_CFB_FILLRECT
- select FB_CFB_COPYAREA
- select FB_CFB_IMAGEBLIT
-@@ -1822,6 +1822,15 @@ config FB_PS3_DEFAULT_SIZE_M
- The default value can be overridden on the kernel command line
- using the "ps3fb" option (e.g. "ps3fb=9M");
-
-+config FB_OLPC_DCON
-+ tristate "One Laptop Per Child Display CONtroller support"
-+ depends on OLPC
-+ select I2C
-+ ---help---
-+ Add support for the OLPC DCON controller. This controller is only
-+ available on OLPC platforms. Unless you have one of these
-+ platforms, you will want to say 'N'.
-+
- config FB_XILINX
- tristate "Xilinx frame buffer support"
- depends on FB && XILINX_VIRTEX
-diff --git a/drivers/video/Makefile b/drivers/video/Makefile
-index 06eec7b..fc535fb 100644
---- a/drivers/video/Makefile
-+++ b/drivers/video/Makefile
-@@ -111,6 +111,7 @@ obj-$(CONFIG_FB_PNX4008_DUM_RGB) += pnx4008/
- obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o
- obj-$(CONFIG_FB_PS3) += ps3fb.o
- obj-$(CONFIG_FB_SM501) += sm501fb.o
-+obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon.o
- obj-$(CONFIG_FB_XILINX) += xilinxfb.o
- obj-$(CONFIG_FB_OMAP) += omap/
-
-diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
-index 0740272..4ac6a95 100644
---- a/drivers/video/fbmem.c
-+++ b/drivers/video/fbmem.c
-@@ -820,6 +820,53 @@ static void try_to_load(int fb)
- #endif /* CONFIG_KMOD */
-
- int
-+fb_powerup(struct fb_info *info)
-+{
-+ int ret = 0;
-+
-+ if (!info || info->state == FBINFO_STATE_RUNNING)
-+ return 0;
-+
-+ if (info->fbops->fb_powerup)
-+ ret = info->fbops->fb_powerup(info);
-+
-+ if (!ret) {
-+ acquire_console_sem();
-+ fb_set_suspend(info, 0);
-+ release_console_sem();
-+ }
-+
-+ return ret;
-+}
-+
-+int
-+fb_powerdown(struct fb_info *info)
-+{
-+ int ret = 0;
-+
-+ if (!info || info->state == FBINFO_STATE_SUSPENDED)
-+ return 0;
-+
-+ /* Tell everybody that the fbdev is going down */
-+ acquire_console_sem();
-+ fb_set_suspend(info, 1);
-+ release_console_sem();
-+
-+ if (info->fbops->fb_powerdown)
-+ ret = info->fbops->fb_powerdown(info);
-+
-+ /* If the power down failed, then un-notify */
-+
-+ if (ret) {
-+ acquire_console_sem();
-+ fb_set_suspend(info, 0);
-+ release_console_sem();
-+ }
-+
-+ return ret;
-+}
-+
-+int
- fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var)
- {
- struct fb_fix_screeninfo *fix = &info->fix;
-diff --git a/drivers/video/geode/Makefile b/drivers/video/geode/Makefile
-index 957304b..5c98da1 100644
---- a/drivers/video/geode/Makefile
-+++ b/drivers/video/geode/Makefile
-@@ -5,5 +5,5 @@ obj-$(CONFIG_FB_GEODE_GX) += gxfb.o
- obj-$(CONFIG_FB_GEODE_LX) += lxfb.o
-
- gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o
--gxfb-objs := gxfb_core.o display_gx.o video_gx.o
-+gxfb-objs := gxfb_core.o display_gx.o video_gx.o suspend_gx.o
- lxfb-objs := lxfb_core.o lxfb_ops.o
-diff --git a/drivers/video/geode/display_gx.c b/drivers/video/geode/display_gx.c
-index 0f16e4b..a432b99 100644
---- a/drivers/video/geode/display_gx.c
-+++ b/drivers/video/geode/display_gx.c
-@@ -11,26 +11,44 @@
- * Free Software Foundation; either version 2 of the License, or * (at your
- * option) any later version.
- */
-+
-+#include <linux/kernel.h>
- #include <linux/spinlock.h>
- #include <linux/fb.h>
- #include <linux/delay.h>
- #include <asm/io.h>
- #include <asm/div64.h>
- #include <asm/delay.h>
-+#include <asm/olpc.h>
-
- #include "geodefb.h"
- #include "display_gx.h"
-
--#ifdef CONFIG_FB_GEODE_GX_SET_FBSIZE
--unsigned int gx_frame_buffer_size(void)
-+static inline void rmwl(u32 val, u32 *reg)
- {
-- return CONFIG_FB_GEODE_GX_FBSIZE;
-+ u32 in = readl(reg);
-+ if (in != val)
-+ writel(val, reg);
- }
--#else
-+
- unsigned int gx_frame_buffer_size(void)
- {
- unsigned int val;
-
-+#ifdef CONFIG_OLPC
-+ if (machine_is_olpc() && !olpc_has_vsa()) {
-+ u32 hi,lo;
-+ rdmsr(GLIU0_P2D_RO0, lo, hi);
-+
-+ /* Top page number */
-+ val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
-+
-+ val -= (lo & 0x000fffff); /* Subtract bottom page number */
-+ val += 1; /* Adjust page count */
-+ return (val << 12);
-+ }
-+#endif
-+
- /* FB size is reported by a virtual register */
- /* Virtual register class = 0x02 */
- /* VG_MEM_SIZE(512Kb units) = 0x00 */
-@@ -41,7 +59,6 @@ unsigned int gx_frame_buffer_size(void)
- val = (unsigned int)(inw(0xAC1E)) & 0xFFl;
- return (val << 19);
- }
--#endif
-
- int gx_line_delta(int xres, int bpp)
- {
-@@ -63,23 +80,23 @@ static void gx_set_mode(struct fb_info *info)
- gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
- dcfg = readl(par->dc_regs + DC_DISPLAY_CFG);
-
-- /* Disable the timing generator. */
-- dcfg &= ~(DC_DCFG_TGEN);
-- writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
-+ /* Programming the clock is costly and ugly, so avoid if if we can */
-
-- /* Wait for pending memory requests before disabling the FIFO load. */
-- udelay(100);
-+ if (par->curdclk != info->var.pixclock) {
-+ /* Disable the timing generator. */
-+ dcfg &= ~(DC_DCFG_TGEN);
-+ writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
-
-- /* Disable FIFO load and compression. */
-- gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
-- writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
-+ /* Wait for pending memory requests before disabling the FIFO load. */
-+ udelay(100);
-
-- /* Setup DCLK and its divisor. */
-- par->vid_ops->set_dclk(info);
-+ /* Disable FIFO load and compression. */
-+ gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
-+ writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
-
-- /*
-- * Setup new mode.
-- */
-+ /* Setup DCLK and its divisor. */
-+ par->vid_ops->set_dclk(info);
-+ }
-
- /* Clear all unused feature bits. */
- gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE;
-@@ -90,12 +107,13 @@ static void gx_set_mode(struct fb_info *info)
- gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
-
- /* Framebuffer start offset. */
-- writel(0, par->dc_regs + DC_FB_ST_OFFSET);
-+ rmwl(0, par->dc_regs + DC_FB_ST_OFFSET);
-
- /* Line delta and line buffer length. */
-- writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH);
-- writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
-- par->dc_regs + DC_LINE_SIZE);
-+ rmwl(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH);
-+
-+ rmwl(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
-+ par->dc_regs + DC_LINE_SIZE);
-
-
- /* Enable graphics and video data and unmask address lines. */
-@@ -134,17 +152,16 @@ static void gx_set_mode(struct fb_info *info)
- vblankend = vsyncend + info->var.upper_margin;
- vtotal = vblankend;
-
-- writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING);
-- writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING);
-- writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING);
--
-- writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING);
-- writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING);
-- writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING);
-+ rmwl((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING);
-+ rmwl((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING);
-+ rmwl((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING);
-+ rmwl((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING);
-+ rmwl((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING);
-+ rmwl((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING);
-
- /* Write final register values. */
-- writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
-- writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
-+ rmwl(dcfg, par->dc_regs + DC_DISPLAY_CFG);
-+ rmwl(gcfg, par->dc_regs + DC_GENERAL_CFG);
-
- par->vid_ops->configure_display(info);
-
-diff --git a/drivers/video/geode/display_gx.h b/drivers/video/geode/display_gx.h
-index 0af33f3..d20b877 100644
---- a/drivers/video/geode/display_gx.h
-+++ b/drivers/video/geode/display_gx.h
-@@ -20,6 +20,9 @@ extern struct geode_dc_ops gx_dc_ops;
- #define GLD_MSR_CONFIG 0xC0002001
- #define GLD_MSR_CONFIG_DM_FP 0x40
-
-+/* Used for memory dection on the OLPC */
-+#define GLIU0_P2D_RO0 0x10000029
-+
- /* Display controller registers */
-
- #define DC_UNLOCK 0x00
-diff --git a/drivers/video/geode/geode_regs.h b/drivers/video/geode/geode_regs.h
-new file mode 100644
-index 0000000..9e75505
---- /dev/null
-+++ b/drivers/video/geode/geode_regs.h
-@@ -0,0 +1,242 @@
-+/* This header file defines the registers and suspend/resume
-+ structures for the Geode GX and LX. The lxfb driver defines
-+ _GEODELX_ before including this file, which will unlock the
-+ extra registers that are only valid for LX.
-+*/
-+
-+#ifndef _GEODE_REGS_H_
-+#define _GEODE_REGS_H_
-+
-+/* MSRs */
-+
-+#define GX_VP_MSR_PAD_SELECT 0xC0002011
-+#define LX_VP_MSR_PAD_SELECT 0x48000011
-+
-+#define GEODE_MSR_GLCP_DOTPLL 0x4c000015
-+
-+#define GLCP_DOTPLL_RESET (1 << 0)
-+#define GLCP_DOTPLL_BYPASS (1 << 15)
-+#define GLCP_DOTPLL_HALFPIX (1 << 24)
-+#define GLCP_DOTPLL_LOCK (1 << 25)
-+
-+/* Registers */
-+#define VP_FP_START 0x400
-+
-+
-+#ifdef _GEODELX_
-+
-+#define GP_REG_SIZE 0x7C
-+#define DC_REG_SIZE 0xF0
-+#define VP_REG_SIZE 0x158
-+#define FP_REG_SIZE 0x70
-+
-+#else
-+
-+#define GP_REG_SIZE 0x50
-+#define DC_REG_SIZE 0x90
-+#define VP_REG_SIZE 0x138
-+#define FP_REG_SIZE 0x70
-+
-+#endif
-+
-+#define DC_PAL_SIZE 0x105
-+
-+struct geoderegs {
-+
-+ struct {
-+ u64 padsel;
-+ u64 dotpll;
-+
-+#ifdef _GEODELX_
-+ u64 dfglcfg;
-+ u64 dcspare;
-+#else
-+ u64 rstpll;
-+#endif
-+ } msr;
-+
-+ union {
-+ unsigned char b[GP_REG_SIZE];
-+ struct {
-+ u32 dst_offset; /* 0x00 */
-+ u32 src_offset; /* 0x04 */
-+ u32 stride; /* 0x08 */
-+ u32 wid_height; /* 0x0C */
-+ u32 src_color_fg; /* 0x10 */
-+ u32 src_color_bg; /* 0x14 */
-+ u32 pat_color_0; /* 0x18 */
-+ u32 pat_color_1; /* 0x1C */
-+ u32 pat_color_2; /* 0x20 */
-+ u32 pat_color_3; /* 0x24 */
-+ u32 pat_color_4; /* 0x28 */
-+ u32 pat_color_5; /* 0x2C */
-+ u32 pat_data_0; /* 0x30 */
-+ u32 pat_data_1; /* 0x34 */
-+ u32 raster_mode; /* 0x38 */
-+ u32 vector_mode; /* 0x3C */
-+ u32 blt_mode; /* 0x40 */
-+ u32 blit_status; /* 0x4C */
-+ u32 hst_src; /* 0x48 */
-+ u32 base_offset; /* 0x4C */
-+
-+#ifdef _GEODELX_
-+ u32 cmd_top; /* 0x50 */
-+ u32 cmd_bot; /* 0x54 */
-+ u32 cmd_read; /* 0x58 */
-+ u32 cmd_write; /* 0x5C */
-+ u32 ch3_offset; /* 0x60 */
-+ u32 ch3_mode_str; /* 0x64 */
-+ u32 ch3_width; /* 0x68 */
-+ u32 ch3_hsrc; /* 0x6C */
-+ u32 lut_index; /* 0x70 */
-+ u32 lut_data; /* 0x74 */
-+ u32 int_cntrl; /* 0x78 */
-+#endif
-+ } r;
-+ } gp;
-+
-+ union {
-+ unsigned char b[DC_REG_SIZE];
-+
-+ struct {
-+ u32 unlock; /* 0x00 */
-+ u32 gcfg; /* 0x04 */
-+ u32 dcfg; /* 0x08 */
-+ u32 arb; /* 0x0C */
-+ u32 fb_st_offset; /* 0x10 */
-+ u32 cb_st_offset; /* 0x14 */
-+ u32 curs_st_offset; /* 0x18 */
-+ u32 icon_st_offset; /* 0x1C */
-+ u32 vid_y_st_offset; /* 0x20 */
-+ u32 vid_u_st_offset; /* 0x24 */
-+ u32 vid_v_st_offset; /* 0x28 */
-+ u32 dctop; /* 0x2c */
-+ u32 line_size; /* 0x30 */
-+ u32 gfx_pitch; /* 0x34 */
-+ u32 vid_yuv_pitch; /* 0x38 */
-+ u32 rsvd2; /* 0x3C */
-+ u32 h_active_timing; /* 0x40 */
-+ u32 h_blank_timing; /* 0x44 */
-+ u32 h_sync_timing; /* 0x48 */
-+ u32 rsvd3; /* 0x4C */
-+ u32 v_active_timing; /* 0x50 */
-+ u32 v_blank_timing; /* 0x54 */
-+ u32 v_sync_timing; /* 0x58 */
-+ u32 fbactive; /* 0x5C */
-+ u32 dc_cursor_x; /* 0x60 */
-+ u32 dc_cursor_y; /* 0x64 */
-+ u32 dc_icon_x; /* 0x68 */
-+ u32 dc_line_cnt; /* 0x6C */
-+ u32 rsvd5; /* 0x70 - palette address */
-+ u32 rsvd6; /* 0x74 - palette data */
-+ u32 dfifo_diag; /* 0x78 */
-+ u32 cfifo_diag; /* 0x7C */
-+ u32 dc_vid_ds_delta; /* 0x80 */
-+ u32 gliu0_mem_offset; /* 0x84 */
-+ u32 dv_ctl; /* 0x88 - added by LX */
-+ u32 dv_acc; /* 0x8C */
-+
-+#ifdef _GEODELX_
-+ u32 gfx_scale;
-+ u32 irq_filt_ctl;
-+ u32 filt_coeff1;
-+ u32 filt_coeff2;
-+ u32 vbi_event_ctl;
-+ u32 vbi_odd_ctl;
-+ u32 vbi_hor;
-+ u32 vbi_ln_odd;
-+ u32 vbi_ln_event;
-+ u32 vbi_pitch;
-+ u32 clr_key;
-+ u32 clr_key_mask;
-+ u32 clr_key_x;
-+ u32 clr_key_y;
-+ u32 irq;
-+ u32 rsvd8;
-+ u32 genlk_ctrl;
-+ u32 vid_even_y_st_offset; /* 0xD8 */
-+ u32 vid_even_u_st_offset; /* 0xDC */
-+ u32 vid_even_v_st_offset; /* 0xE0 */
-+ u32 v_active_even_timing; /* 0xE4 */
-+ u32 v_blank_even_timing; /* 0xE8 */
-+ u32 v_sync_even_timing; /* 0xEC */
-+#endif
-+ } r;
-+ } dc;
-+
-+ union {
-+ unsigned char b[VP_REG_SIZE];
-+
-+ struct {
-+ u64 vcfg; /* 0x00 */
-+ u64 dcfg; /* 0x08 */
-+ u64 vx; /* 0x10 */
-+ u64 vy; /* 0x18 */
-+ u64 vs; /* 0x20 */
-+ u64 vck; /* 0x28 */
-+ u64 vcm; /* 0x30 */
-+ u64 rsvd1; /* 0x38 - Gamma address*/
-+ u64 rsvd2; /* 0x40 - Gamma data*/
-+ u64 rsvd3; /* 0x48 */
-+ u64 misc; /* 0x50 */
-+ u64 ccs; /* 0x58 */
-+ u64 rsvd4[3]; /* 0x60-0x70 */
-+ u64 vdc; /* 0x78 */
-+ u64 vco; /* 0x80 */
-+ u64 crc; /* 0x88 */
-+ u64 crc32; /* 0x90 */
-+ u64 vde; /* 0x98 */
-+ u64 cck; /* 0xA0 */
-+ u64 ccm; /* 0xA8 */
-+ u64 cc1; /* 0xB0 */
-+ u64 cc2; /* 0xB8 */
-+ u64 a1x; /* 0xC0 */
-+ u64 a1y; /* 0xC8 */
-+ u64 a1c; /* 0xD0 */
-+ u64 a1t; /* 0xD8 */
-+ u64 a2x; /* 0xE0 */
-+ u64 a2y; /* 0xE8 */
-+ u64 a2c; /* 0xF0 */
-+ u64 a2t; /* 0xF8 */
-+ u64 a3x; /* 0x100 */
-+ u64 a3y; /* 0x108 */
-+ u64 a3c; /* 0x110 */
-+ u64 a3t; /* 0x118 */
-+ u64 vrr; /* 0x120 */
-+ u64 awt; /* 0x128 */
-+ u64 vtm; /* 0x130 */
-+#ifdef _GEODELX_
-+ u64 vye; /* 0x138 */
-+ u64 a1ye; /* 0x140 */
-+ u32 a2ye; /* 0x148 */
-+ u32 a3ye; /* 0x150 */
-+#endif
-+ } r;
-+ } vp;
-+
-+ union {
-+ unsigned char b[FP_REG_SIZE];
-+
-+ struct {
-+ u64 pt1; /* 0x400 */
-+ u64 pt2; /* 0x408 */
-+ u64 pm; /* 0x410 */
-+ u64 dfc; /* 0x418 */
-+ u64 blfsr; /* 0x420 */
-+ u64 rlfsr; /* 0x428 */
-+ u64 fmi; /* 0x430 */
-+ u64 fmd; /* 0x438 */
-+ u64 rsvd; /* 0x440 */
-+ u64 dca; /* 0x448 */
-+ u64 dmd; /* 0x450 */
-+ u64 crc; /* 0x458 */
-+ u64 fbb; /* 0x460 */
-+ u64 crc32; /* 0x468 */
-+ } r;
-+ } fp;
-+
-+ u32 pal[DC_PAL_SIZE];
-+ u32 gamma[256];
-+};
-+
-+#endif
-diff --git a/drivers/video/geode/geodefb.h b/drivers/video/geode/geodefb.h
-index ae04820..0214d11 100644
---- a/drivers/video/geode/geodefb.h
-+++ b/drivers/video/geode/geodefb.h
-@@ -12,6 +12,10 @@
- #ifndef __GEODEFB_H__
- #define __GEODEFB_H__
-
-+#define FB_POWER_STATE_OFF 0
-+#define FB_POWER_STATE_SUSPEND 1
-+#define FB_POWER_STATE_ON 2
-+
- struct geodefb_info;
-
- struct geode_dc_ops {
-@@ -21,18 +25,24 @@ struct geode_dc_ops {
-
- struct geode_vid_ops {
- void (*set_dclk)(struct fb_info *);
-+ unsigned int (*get_dclk)(struct fb_info *);
- void (*configure_display)(struct fb_info *);
- int (*blank_display)(struct fb_info *, int blank_mode);
- };
-
- struct geodefb_par {
- int enable_crt;
-+ int fbactive; /* True if the current console is in KD_GRAPHICS mode */
- int panel_x; /* dimensions of an attached flat panel, non-zero => enable panel */
- int panel_y;
-+ unsigned int curdclk; /* Used by GX to avoid unnessesary clock switching */
- void __iomem *dc_regs;
- void __iomem *vid_regs;
-+ void __iomem *gp_regs;
- struct geode_dc_ops *dc_ops;
- struct geode_vid_ops *vid_ops;
-+
-+ int state;
- };
-
- #endif /* !__GEODEFB_H__ */
-diff --git a/drivers/video/geode/gxfb_core.c b/drivers/video/geode/gxfb_core.c
-index cf841ef..3eabc53 100644
---- a/drivers/video/geode/gxfb_core.c
-+++ b/drivers/video/geode/gxfb_core.c
-@@ -30,12 +30,31 @@
- #include <linux/fb.h>
- #include <linux/init.h>
- #include <linux/pci.h>
-+#include <linux/notifier.h>
-+#include <linux/vt_kern.h>
-+#include <linux/console.h>
-+#include <asm/uaccess.h>
-+#include <asm/olpc.h>
-
- #include "geodefb.h"
- #include "display_gx.h"
- #include "video_gx.h"
-
-+#define FBIOSGAMMA _IOW('F', 0x20, void *)
-+#define FBIOGGAMMA _IOW('F', 0x21, void *)
-+
-+#ifdef DEBUG
-+
-+#define FBIODUMPGP _IOW('F', 0x22, void *)
-+#define FBIODUMPDC _IOW('F', 0x23, void *)
-+#define FBIODUMPVP _IOW('F', 0x24, void *)
-+#define FBIODUMPFP _IOW('F', 0x25, void *)
-+
-+#endif
-+
- static char *mode_option;
-+static int noclear;
-+struct fb_info *gxfb_info;
-
- /* Modes relevant to the GX (taken from modedb.c) */
- static const struct fb_videomode gx_modedb[] __initdata = {
-@@ -103,8 +122,20 @@ static const struct fb_videomode gx_modedb[] __initdata = {
- { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1200x900-75 - CRT timings for the OLPC mode */
-+ { NULL, 75, 1200, 900, 8049, 104, 240, 29, 54, 136, 3,
-+ 0, FB_VMODE_NONINTERLACED, 0 }
- };
-
-+#ifdef CONFIG_OLPC
-+static const struct fb_videomode gx_dcon_modedb[] __initdata = {
-+ /* The only mode the DCON has is 1200x900 */
-+ { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3,
-+ 0, FB_VMODE_NONINTERLACED, 0 }
-+};
-+#endif
-+
-+
- static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
- {
- if (var->xres > 1600 || var->yres > 1200)
-@@ -137,7 +168,7 @@ static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
- return 0;
- }
-
--static int gxfb_set_par(struct fb_info *info)
-+int gxfb_set_par(struct fb_info *info)
- {
- struct geodefb_par *par = info->par;
-
-@@ -204,16 +235,26 @@ static int gxfb_blank(int blank_mode, struct fb_info *info)
- return par->vid_ops->blank_display(info, blank_mode);
- }
-
-+static int fbsize;
-+
- static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
- {
- struct geodefb_par *par = info->par;
-- int fb_len;
- int ret;
-
- ret = pci_enable_device(dev);
- if (ret < 0)
- return ret;
-
-+ ret = pci_request_region(dev, 1, "gxfb (graphics processor)");
-+ if (ret < 0)
-+ return ret;
-+
-+ par->gp_regs = ioremap(pci_resource_start(dev, 1),
-+ pci_resource_len(dev, 1));
-+ if (!par->gp_regs)
-+ return -ENOMEM;
-+
- ret = pci_request_region(dev, 3, "gxfb (video processor)");
- if (ret < 0)
- return ret;
-@@ -232,36 +273,118 @@ static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *de
- ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
- if (ret < 0)
- return ret;
-- if ((fb_len = gx_frame_buffer_size()) < 0)
-- return -ENOMEM;
-+
-+ /* If the fbsize wasn't specified then try to probe it */
-+
-+ if (!fbsize) {
-+ fbsize = gx_frame_buffer_size();
-+ if (fbsize == 0)
-+ return -ENOMEM;
-+ }
-+
- info->fix.smem_start = pci_resource_start(dev, 0);
-- info->fix.smem_len = fb_len;
-+ info->fix.smem_len = fbsize;
- info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
- if (!info->screen_base)
- return -ENOMEM;
-
-- /* Set the 16MB aligned base address of the graphics memory region
-+ /* Set the 16MiB aligned base address of the graphics memory region
- * in the display controller */
-
- writel(info->fix.smem_start & 0xFF000000,
- par->dc_regs + DC_GLIU0_MEM_OFFSET);
-
-- dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n",
-+ dev_info(&dev->dev, "%d KiB of video memory at 0x%lx\n",
- info->fix.smem_len / 1024, info->fix.smem_start);
-
- return 0;
- }
-
-+static int gxfb_ioctl( struct fb_info *info, unsigned int cmd,
-+ unsigned long arg)
-+{
-+ unsigned int gamma[GXFB_GAMMA_DWORDS];
-+ int ret = -EINVAL;
-+ struct geodefb_par *par = info->par;
-+ int i;
-+
-+ switch(cmd) {
-+ case FBIOSGAMMA:
-+ /* Read the gamma information from the user - 256 dwords */
-+
-+ if (copy_from_user(gamma, (void * __user) arg, GXFB_GAMMA_SIZE))
-+ return -EFAULT;
-+
-+ writel(0, par->vid_regs + GX_GAR);
-+
-+ /* Sequential writes to the data register will increment the
-+ address automatically */
-+
-+ for(i = 0; i < GXFB_GAMMA_DWORDS; i++)
-+ writel(gamma[i] & 0xFFFFFF, par->vid_regs + GX_GDR);
-+
-+ writel(readl(par->vid_regs + GX_MISC) & ~GX_MISC_GAM_EN,
-+ par->vid_regs + GX_MISC);
-+
-+ ret = 0;
-+ break;
-+
-+ case FBIOGGAMMA:
-+ if (readl(par->vid_regs + GX_MISC) & GX_MISC_GAM_EN)
-+ return -EINVAL;
-+
-+ memset(gamma, 0, GXFB_GAMMA_SIZE);
-+ writel(0, par->vid_regs + GX_GAR);
-+
-+ for(i = 0; i < GXFB_GAMMA_DWORDS;i++)
-+ gamma[i] = readl(par->vid_regs + GX_GDR);
-+
-+ if (copy_to_user((void * __user) arg, gamma, GXFB_GAMMA_SIZE))
-+ ret = -EFAULT;
-+ else
-+ ret = 0;
-+
-+ break;
-+
-+#ifdef DEBUG
-+ case FBIODUMPGP:
-+ ret = 0;
-+ dump_regs(info, 0);
-+ break;
-+
-+ case FBIODUMPDC:
-+ ret = 0;
-+ dump_regs(info, 1);
-+ break;
-+
-+ case FBIODUMPVP:
-+ ret = 0;
-+ dump_regs(info, 2);
-+ break;
-+
-+ case FBIODUMPFP:
-+ ret = 0;
-+ dump_regs(info, 3);
-+ break;
-+#endif
-+ }
-+
-+ return ret;
-+}
-+
- static struct fb_ops gxfb_ops = {
- .owner = THIS_MODULE,
- .fb_check_var = gxfb_check_var,
- .fb_set_par = gxfb_set_par,
- .fb_setcolreg = gxfb_setcolreg,
- .fb_blank = gxfb_blank,
-+ .fb_ioctl = gxfb_ioctl,
- /* No HW acceleration for now. */
- .fb_fillrect = cfb_fillrect,
- .fb_copyarea = cfb_copyarea,
- .fb_imageblit = cfb_imageblit,
-+ .fb_powerdown = gxfb_powerdown,
-+ .fb_powerup = gxfb_powerup,
- };
-
- static struct fb_info * __init gxfb_init_fbinfo(struct device *dev)
-@@ -303,23 +426,86 @@ static struct fb_info * __init gxfb_init_fbinfo(struct device *dev)
- return info;
- }
-
--static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
-+static int gxfb_console_notify(struct notifier_block *self,
-+ unsigned long action, void *data)
-+{
-+ if (gxfb_info != NULL) {
-+ struct geodefb_par *par = gxfb_info->par;
-+ par->fbactive = (action == CONSOLE_EVENT_SWITCH_TEXT) ? 0 : 1;
-+ }
-+
-+ return NOTIFY_OK;
-+}
-+
-+static struct notifier_block gxfb_console_notifier = {
-+ .notifier_call = gxfb_console_notify
-+};
-+
-+#ifdef CONFIG_PM
-+
-+static int gxfb_suspend(struct pci_dev *pdev, pm_message_t state)
-+{
-+ struct fb_info *info = pci_get_drvdata(pdev);
-+ struct geodefb_par *par = info->par;
-+
-+ if (pdev->dev.power.power_state.event == state.event)
-+ return 0;
-+
-+ if (state.event == PM_EVENT_SUSPEND) {
-+
-+ acquire_console_sem();
-+ gxfb_powerdown(info);
-+
-+ par->state = FB_POWER_STATE_OFF;
-+ fb_set_suspend(info, 1);
-+
-+ release_console_sem();
-+ }
-+
-+ pdev->dev.power.power_state = state;
-+ return 0;
-+}
-+
-+static int gxfb_resume(struct pci_dev *pdev)
-+{
-+ struct fb_info *info = pci_get_drvdata(pdev);
-+
-+ acquire_console_sem();
-+
-+ /* Turn the engine completely on */
-+
-+ if (gxfb_powerup(info))
-+ printk(KERN_ERR "gxfb: Powerup failed\n");
-+
-+ fb_set_suspend(info, 0);
-+ release_console_sem();
-+
-+ pdev->dev.power.power_state = PMSG_ON;
-+ return 0;
-+}
-+#endif
-+
-+static int __init gxfb_probe(struct pci_dev *pdev,
-+ const struct pci_device_id *id)
- {
- struct geodefb_par *par;
-- struct fb_info *info;
- int ret;
- unsigned long val;
-
-- info = gxfb_init_fbinfo(&pdev->dev);
-- if (!info)
-+ struct fb_videomode *modedb_ptr;
-+ int modedb_size;
-+
-+ gxfb_info = gxfb_init_fbinfo(&pdev->dev);
-+ if (gxfb_info == NULL)
- return -ENOMEM;
-- par = info->par;
-+
-+ par = gxfb_info->par;
-
- /* GX display controller and GX video device. */
- par->dc_ops = &gx_dc_ops;
- par->vid_ops = &gx_vid_ops;
-
-- if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
-+ if ((ret = gxfb_map_video_memory(gxfb_info, pdev)) < 0) {
- dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
- goto err;
- }
-@@ -333,32 +519,60 @@ static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *i
- else
- par->enable_crt = 1;
-
-- ret = fb_find_mode(&info->var, info, mode_option,
-- gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16);
-+ /* Get the current dotclock */
-+
-+ par->curdclk = (par->vid_ops->get_dclk) ? par->vid_ops->get_dclk(gxfb_info) : 0;
-+
-+ /* We need to determine a display mode right now, so we will
-+ * check to see if the DCON was previously detected by the BIOS
-+ * and use that to make our mode database decision.
-+ */
-+
-+ modedb_ptr = (struct fb_videomode *) gx_modedb;
-+ modedb_size = ARRAY_SIZE(gx_modedb);
-+
-+#ifdef CONFIG_OLPC
-+ if (olpc_has_dcon()) {
-+ modedb_ptr = (struct fb_videomode *) gx_dcon_modedb;
-+ modedb_size = ARRAY_SIZE(gx_dcon_modedb);
-+ }
-+#endif
-+
-+ ret = fb_find_mode(&gxfb_info->var, gxfb_info, mode_option,
-+ modedb_ptr, modedb_size, NULL, 16);
-+
- if (ret == 0 || ret == 4) {
- dev_err(&pdev->dev, "could not find valid video mode\n");
- ret = -EINVAL;
- goto err;
- }
-
-+ /* Clear the screen of garbage, unless noclear was specified,
-+ * in which case we assume the user knows what he is doing */
-+
-+ if (!noclear)
-+ memset_io(gxfb_info->screen_base, 0, gxfb_info->fix.smem_len);
-+
-+ gxfb_check_var(&gxfb_info->var, gxfb_info);
-+ gxfb_set_par(gxfb_info);
-+
-+ /* We are powered up */
-+ par->state = FB_POWER_STATE_ON;
-
-- /* Clear the frame buffer of garbage. */
-- memset_io(info->screen_base, 0, info->fix.smem_len);
-
-- gxfb_check_var(&info->var, info);
-- gxfb_set_par(info);
-+ console_event_register(&gxfb_console_notifier);
-
-- if (register_framebuffer(info) < 0) {
-+ if (register_framebuffer(gxfb_info) < 0) {
- ret = -EINVAL;
- goto err;
- }
-- pci_set_drvdata(pdev, info);
-- printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
-+ pci_set_drvdata(pdev, gxfb_info);
-+ printk(KERN_INFO "fb%d: %s frame buffer device\n", gxfb_info->node, gxfb_info->fix.id);
- return 0;
-
- err:
-- if (info->screen_base) {
-- iounmap(info->screen_base);
-+ if (gxfb_info->screen_base) {
-+ iounmap(gxfb_info->screen_base);
- pci_release_region(pdev, 0);
- }
- if (par->vid_regs) {
-@@ -370,8 +584,9 @@ static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *i
- pci_release_region(pdev, 2);
- }
-
-- if (info)
-- framebuffer_release(info);
-+ if (gxfb_info)
-+ framebuffer_release(gxfb_info);
-+
- return ret;
- }
-
-@@ -397,9 +612,7 @@ static void gxfb_remove(struct pci_dev *pdev)
- }
-
- static struct pci_device_id gxfb_id_table[] = {
-- { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO,
-- PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
-- 0xff0000, 0 },
-+ { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_GX_VIDEO) },
- { 0, }
- };
-
-@@ -410,22 +623,30 @@ static struct pci_driver gxfb_driver = {
- .id_table = gxfb_id_table,
- .probe = gxfb_probe,
- .remove = gxfb_remove,
-+#ifdef CONFIG_PM
-+ .suspend = gxfb_suspend,
-+ .resume = gxfb_resume
-+#endif
- };
-
- #ifndef MODULE
--static int __init gxfb_setup(char *options)
--{
-+static int __init gxfb_setup(char *options) {
-
- char *opt;
-
- if (!options || !*options)
- return 0;
-
-- while ((opt = strsep(&options, ",")) != NULL) {
-+ while((opt = strsep(&options, ",")) != NULL) {
- if (!*opt)
- continue;
-
-- mode_option = opt;
-+ if (!strncmp(opt, "fbsize:", 7))
-+ fbsize = simple_strtoul(opt+7, NULL, 0);
-+ else if (!strcmp(opt, "noclear"))
-+ noclear = 1;
-+ else
-+ mode_option = opt;
- }
-
- return 0;
-@@ -444,7 +665,6 @@ static int __init gxfb_init(void)
- #endif
- return pci_register_driver(&gxfb_driver);
- }
--
- static void __exit gxfb_cleanup(void)
- {
- pci_unregister_driver(&gxfb_driver);
-@@ -456,5 +676,8 @@ module_exit(gxfb_cleanup);
- module_param(mode_option, charp, 0);
- MODULE_PARM_DESC(mode_option, "video mode (<x>x<y>[-<bpp>][@<refr>])");
-
-+module_param(fbsize, int, 0);
-+MODULE_PARM_DESC(fbsize, "video memory size");
-+
- MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
- MODULE_LICENSE("GPL");
-diff --git a/drivers/video/geode/lxfb.h b/drivers/video/geode/lxfb.h
-index 6c227f9..5be8a4d 100644
---- a/drivers/video/geode/lxfb.h
-+++ b/drivers/video/geode/lxfb.h
-@@ -25,10 +25,23 @@ void lx_set_mode(struct fb_info *);
- void lx_get_gamma(struct fb_info *, unsigned int *, int);
- void lx_set_gamma(struct fb_info *, unsigned int *, int);
- unsigned int lx_framebuffer_size(void);
-+int lx_shutdown(struct fb_info *);
-+int lx_powerup(struct fb_info *);
- int lx_blank_display(struct fb_info *, int);
- void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
- unsigned int, unsigned int);
-
-+
-+
-+/* ioctl() defines */
-+
-+#define FBIOSGAMMA _IOW('F', 0x20, void *)
-+#define FBIOGGAMMA _IOW('F', 0x21, void *)
-+
-+/* General definitions */
-+#define LXFB_GAMMA_DWORDS 256 /* number of dwords in the gamma ram */
-+#define LXFB_GAMMA_SIZE (LXFB_GAMMA_DWORDS * sizeof(unsigned int))
-+
- /* MSRS */
-
- #define MSR_LX_GLD_CONFIG 0x48002001
-diff --git a/drivers/video/geode/lxfb_core.c b/drivers/video/geode/lxfb_core.c
-index 5e30b40..c9060ed 100644
---- a/drivers/video/geode/lxfb_core.c
-+++ b/drivers/video/geode/lxfb_core.c
-@@ -22,6 +22,7 @@
- #include <linux/init.h>
- #include <linux/pci.h>
- #include <linux/uaccess.h>
-+#include <asm/olpc.h>
-
- #include "lxfb.h"
-
-@@ -35,186 +36,84 @@ static int fbsize;
- */
-
- const struct fb_videomode geode_modedb[] __initdata = {
-- /* 640x480-60 */
-- { NULL, 60, 640, 480, 39682, 48, 8, 25, 2, 88, 2,
-+ /* 640x480-60 VESA */
-+ { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
-+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 640x480-75 VESA */
-+ { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
-+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 640x480-85 VESA */
-+ { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
-+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 800x600-60 VESA */
-+ { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 640x400-70 */
-- { NULL, 70, 640, 400, 39770, 40, 8, 28, 5, 96, 2,
-- FB_SYNC_HOR_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 640x480-70 */
-- { NULL, 70, 640, 480, 35014, 88, 24, 15, 2, 64, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 640x480-72 */
-- { NULL, 72, 640, 480, 32102, 120, 16, 20, 1, 40, 3,
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 800x600-75 VESA */
-+ { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 640x480-75 */
-- { NULL, 75, 640, 480, 31746, 120, 16, 16, 1, 64, 3,
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 800x600-85 VESA */
-+ { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 640x480-85 */
-- { NULL, 85, 640, 480, 27780, 80, 56, 25, 1, 56, 3,
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1024x768-60 VESA */
-+ { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
-+ 0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1024x768-75 VESA */
-+ { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 640x480-90 */
-- { NULL, 90, 640, 480, 26392, 96, 32, 22, 1, 64, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 640x480-100 */
-- { NULL, 100, 640, 480, 23167, 104, 40, 25, 1, 64, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 640x480-60 */
-- { NULL, 60, 640, 480, 39682, 48, 16, 25, 10, 88, 2,
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1024x768-85 VESA */
-+ { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 800x600-56 */
-- { NULL, 56, 800, 600, 27901, 128, 24, 22, 1, 72, 2,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 800x600-60 */
-- { NULL, 60, 800, 600, 25131, 72, 32, 23, 1, 136, 4,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 800x600-70 */
-- { NULL, 70, 800, 600, 21873, 120, 40, 21, 4, 80, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 800x600-72 */
-- { NULL, 72, 800, 600, 20052, 64, 56, 23, 37, 120, 6,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 800x600-75 */
-- { NULL, 75, 800, 600, 20202, 160, 16, 21, 1, 80, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 800x600-85 */
-- { NULL, 85, 800, 600, 17790, 152, 32, 27, 1, 64, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 800x600-90 */
-- { NULL, 90, 800, 600, 16648, 128, 40, 28, 1, 88, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 800x600-100 */
-- { NULL, 100, 800, 600, 14667, 136, 48, 27, 1, 88, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 800x600-60 */
-- { NULL, 60, 800, 600, 25131, 88, 40, 23, 1, 128, 4,
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1280x960-60 VESA */
-+ { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 1024x768-60 */
-- { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1280x960-85 VESA */
-+ { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 1024x768-70 */
-- { NULL, 70, 1024, 768, 13346, 144, 24, 29, 3, 136, 6,
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1280x1024-60 VESA */
-+ { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 1024x768-72 */
-- { NULL, 72, 1024, 768, 12702, 168, 56, 29, 4, 112, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1024x768-75 */
-- { NULL, 75, 1024, 768, 12703, 176, 16, 28, 1, 96, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1024x768-85 */
-- { NULL, 85, 1024, 768, 10581, 208, 48, 36, 1, 96, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1024x768-90 */
-- { NULL, 90, 1024, 768, 9981, 176, 64, 37, 1, 112, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1024x768-100 */
-- { NULL, 100, 1024, 768, 8825, 184, 72, 42, 1, 112, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1024x768-60 */
-- { NULL, 60, 1024, 768, 15385, 160, 24, 29, 3, 136, 6,
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1280x1024-75 VESA */
-+ { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 1152x864-60 */
-- { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1152x864-70 */
-- { NULL, 70, 1152, 864, 10254, 192, 72, 32, 8, 120, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1152x864-72 */
-- { NULL, 72, 1152, 864, 9866, 200, 72, 33, 7, 128, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1152x864-75 */
-- { NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1152x864-85 */
-- { NULL, 85, 1152, 864, 8357, 200, 72, 37, 3, 128, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1152x864-90 */
-- { NULL, 90, 1152, 864, 7719, 208, 80, 42, 9, 128, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1152x864-100 */
-- { NULL, 100, 1152, 864, 6947, 208, 80, 48, 3, 128, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1152x864-60 */
-- { NULL, 60, 1152, 864, 12251, 184, 64, 27, 1, 120, 3,
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1280x1024-85 VESA */
-+ { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 1280x1024-60 */
-- { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1280x1024-70 */
-- { NULL, 70, 1280, 1024, 7719, 224, 88, 38, 6, 136, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1280x1024-72 */
-- { NULL, 72, 1280, 1024, 7490, 224, 88, 39, 7, 136, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1280x1024-75 */
-- { NULL, 75, 1280, 1024, 7409, 248, 16, 38, 1, 144, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1280x1024-85 */
-- { NULL, 85, 1280, 1024, 6351, 224, 64, 44, 1, 160, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1280x1024-90 */
-- { NULL, 90, 1280, 1024, 5791, 240, 96, 51, 12, 144, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1280x1024-100 */
-- { NULL, 100, 1280, 1024, 5212, 240, 96, 57, 6, 144, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1280x1024-60 */
-- { NULL, 60, 1280, 1024, 9262, 248, 48, 38, 1, 112, 3,
-- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 1600x1200-60 */
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1600x1200-60 VESA */
- { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1600x1200-70 */
-- { NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1600x1200-72 */
-- { NULL, 72, 1600, 1200, 5053, 288, 112, 47, 13, 176, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1600x1200-75 */
-+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1600x1200-75 VESA */
- { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1600x1200-85 */
-+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1600x1200-85 VESA */
- { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1600x1200-90 */
-- { NULL, 90, 1600, 1200, 3981, 304, 128, 60, 1, 176, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1600x1200-100 */
-- { NULL, 100, 1600, 1200, 3563, 304, 128, 67, 1, 176, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1600x1200-60 */
-- { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
- FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-- FB_VMODE_NONINTERLACED, 0 },
-- /* 1920x1440-60 */
-- { NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 208, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1920x1440-70 */
-- { NULL, 70, 1920, 1440, 3593, 360, 152, 55, 8, 208, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1920x1440-72 */
-- { NULL, 72, 1920, 1440, 3472, 360, 152, 68, 4, 208, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1920x1440-75 */
-- { NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-- /* 1920x1440-85 */
-- { NULL, 85, 1920, 1440, 2929, 368, 152, 68, 1, 216, 3,
-- 0, FB_VMODE_NONINTERLACED, 0 },
-+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
-+ /* 1200x900-75 - CRT timings for the OLPC mode */
-+ { NULL, 75, 1200, 900, 8049, 104, 240, 29, 54, 136, 3,
-+ 0, FB_VMODE_NONINTERLACED, 0 }
- };
-
-+#ifdef CONFIG_OLPC
-+const struct fb_videomode olpc_dcon_modedb[] __initdata = {
-+ /* The only mode the DCON has is 1200x900 */
-+ { NULL, 50, 1200, 900, 17460, 24, 8, 4, 5, 8, 3,
-+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
-+ FB_VMODE_NONINTERLACED, 0 }
-+};
-+#endif
-+
- static int lxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
- {
- if (var->xres > 1920 || var->yres > 1440)
-@@ -379,16 +278,55 @@ static int __init lxfb_map_video_memory(struct fb_info *info,
- return 0;
- }
-
-+static int lxfb_set_gamma(struct fb_info *info, void * __user data)
-+{
-+ unsigned int gamma[LXFB_GAMMA_DWORDS];
-+
-+ if (copy_from_user(gamma, data, LXFB_GAMMA_SIZE))
-+ return -EFAULT;
-+
-+ lx_set_gamma(info, gamma, LXFB_GAMMA_SIZE);
-+ return 0;
-+}
-+
-+static int lxfb_get_gamma(struct fb_info *info, void * __user data)
-+{
-+ unsigned int gamma[LXFB_GAMMA_DWORDS];
-+ memset(gamma, 0, sizeof(gamma));
-+
-+ lx_get_gamma(info, gamma, LXFB_GAMMA_DWORDS);
-+
-+ return copy_to_user(data, gamma, LXFB_GAMMA_SIZE) ?
-+ -EFAULT : 0;
-+}
-+
-+static int lxfb_ioctl( struct fb_info *info, unsigned int cmd,
-+ unsigned long arg)
-+{
-+ switch(cmd) {
-+ case FBIOSGAMMA:
-+ return lxfb_set_gamma(info, (void * __user) arg);
-+
-+ case FBIOGGAMMA:
-+ return lxfb_get_gamma(info, (void * __user) arg);
-+ }
-+
-+ return -ENOTTY;
-+}
-+
- static struct fb_ops lxfb_ops = {
- .owner = THIS_MODULE,
- .fb_check_var = lxfb_check_var,
- .fb_set_par = lxfb_set_par,
- .fb_setcolreg = lxfb_setcolreg,
- .fb_blank = lxfb_blank,
-+ .fb_ioctl = lxfb_ioctl,
- /* No HW acceleration for now. */
- .fb_fillrect = cfb_fillrect,
- .fb_copyarea = cfb_copyarea,
- .fb_imageblit = cfb_imageblit,
-+ .fb_powerdown = lx_shutdown,
-+ .fb_powerup = lx_powerup,
- };
-
- static struct fb_info * __init lxfb_init_fbinfo(struct device *dev)
-@@ -431,6 +369,45 @@ static struct fb_info * __init lxfb_init_fbinfo(struct device *dev)
- return info;
- }
-
-+#ifdef CONFIG_PM
-+
-+static int lxfb_suspend(struct pci_dev *pdev, pm_message_t state)
-+{
-+ struct fb_info *info = pci_get_drvdata(pdev);
-+
-+ if (pdev->dev.power.power_state.event == state.event)
-+ return 0;
-+
-+ if (state.event == PM_EVENT_SUSPEND) {
-+
-+ acquire_console_sem();
-+ lx_shutdown(info);
-+ fb_set_suspend(info, 1);
-+ release_console_sem();
-+ }
-+
-+ pdev->dev.power.power_state = state;
-+ return 0;
-+}
-+
-+static int lxfb_resume(struct pci_dev *pdev)
-+{
-+ struct fb_info *info = pci_get_drvdata(pdev);
-+
-+ acquire_console_sem();
-+
-+ /* Turn the engine completely on */
-+
-+ lx_powerup(info);
-+ fb_set_suspend(info, 0);
-+ release_console_sem();
-+
-+ pdev->dev.power.power_state = PMSG_ON;
-+ return 0;
-+}
-+
-+#endif
-+
- static int __init lxfb_probe(struct pci_dev *pdev,
- const struct pci_device_id *id)
- {
-@@ -467,6 +444,13 @@ static int __init lxfb_probe(struct pci_dev *pdev,
- modedb_ptr = (struct fb_videomode *) geode_modedb;
- modedb_size = ARRAY_SIZE(geode_modedb);
-
-+#ifdef CONFIG_OLPC
-+ if (olpc_has_dcon()) {
-+ modedb_ptr = (struct fb_videomode *) olpc_dcon_modedb;
-+ modedb_size = ARRAY_SIZE(olpc_dcon_modedb);
-+ }
-+#endif
-+
- ret = fb_find_mode(&info->var, info, mode_option,
- modedb_ptr, modedb_size, NULL, 16);
-
-@@ -556,6 +540,10 @@ static struct pci_driver lxfb_driver = {
- .id_table = lxfb_id_table,
- .probe = lxfb_probe,
- .remove = lxfb_remove,
-+#ifdef CONFIG_PM
-+ .suspend = lxfb_suspend,
-+ .resume = lxfb_resume
-+#endif
- };
-
- #ifndef MODULE
-diff --git a/drivers/video/geode/lxfb_ops.c b/drivers/video/geode/lxfb_ops.c
-index 4fbc99b..47ed9de 100644
---- a/drivers/video/geode/lxfb_ops.c
-+++ b/drivers/video/geode/lxfb_ops.c
-@@ -13,9 +13,13 @@
- #include <linux/fb.h>
- #include <linux/uaccess.h>
- #include <linux/delay.h>
-+#include <asm/olpc.h>
-
- #include "lxfb.h"
-
-+#define _GEODELX_
-+#include "geode_regs.h"
-+
- /* TODO
- * Support panel scaling
- * Add acceleration
-@@ -290,6 +294,19 @@ unsigned int lx_framebuffer_size(void)
- {
- unsigned int val;
-
-+#ifdef CONFIG_OLPC
-+ if (machine_is_olpc() && !olpc_has_vsa()) {
-+ u32 hi,lo;
-+ rdmsr(MSR_LX_GLIU0_P2D_RO0, lo, hi);
-+
-+ /* Top page number */
-+ val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20);
-+ val -= (lo & 0x000fffff); /* Subtract bottom page number */
-+ val += 1; /* Adjust page count */
-+ return (val << 12);
-+ }
-+#endif
-+
- /* The frame buffer size is reported by a VSM in VSA II */
- /* Virtual Register Class = 0x02 */
- /* VG_MEM_SIZE (1MB units) = 0x00 */
-@@ -301,6 +318,34 @@ unsigned int lx_framebuffer_size(void)
- return (val << 20);
- }
-
-+void lx_set_gamma(struct fb_info *info, unsigned int *gamma, int len)
-+{
-+ int i;
-+ struct lxfb_par *par = info->par;
-+
-+ writel(0, par->df_regs + DF_PAR);
-+
-+ /* Sequential writes to the data register will increment the
-+ address automatically */
-+
-+ for(i = 0; i < len; i++)
-+ writel(gamma[i] & 0xFFFFFF, par->df_regs + DF_PDR);
-+
-+ writel(readl(par->df_regs + DF_MISC) & ~DF_MISC_GAM_BYPASS,
-+ par->df_regs + DF_MISC);
-+}
-+
-+void lx_get_gamma(struct fb_info *info, unsigned int *gamma, int len)
-+{
-+ int i;
-+ struct lxfb_par *par = info->par;
-+
-+ writel(0, par->df_regs + DF_PAR);
-+
-+ for(i = 0; i < len;i++)
-+ gamma[i] = readl(par->df_regs + DF_PDR);
-+}
-+
- void lx_set_mode(struct fb_info *info)
- {
- struct lxfb_par *par = info->par;
-@@ -313,6 +358,7 @@ void lx_set_mode(struct fb_info *info)
- int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
-
- /* Unlock the DC registers */
-+ readl(par->dc_regs + DC_UNLOCK);
- writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
-
- lx_graphics_disable(info);
-@@ -534,3 +580,285 @@ int lx_blank_display(struct fb_info *info, int blank_mode)
-
- return 0;
- }
-+
-+static struct geoderegs saved_regs;
-+
-+static void lx_save_regs(struct fb_info *info, struct geoderegs *regs)
-+{
-+ struct lxfb_par *par = info->par;
-+ int i;
-+
-+ /* Wait for the command buffer to empty */
-+ while(!(readl(par->gp_regs + 0x44) & (1 << 4)));
-+
-+ rdmsrl(MSR_LX_DF_PADSEL, regs->msr.padsel);
-+ rdmsrl(MSR_LX_GLCP_DOTPLL, regs->msr.dotpll);
-+ rdmsrl(MSR_LX_DF_GLCONFIG, regs->msr.dfglcfg);
-+ rdmsrl(MSR_LX_DC_SPARE, regs->msr.dcspare);
-+
-+ writel(0x4758, par->dc_regs + 0x00);
-+
-+ memcpy(regs->gp.b, par->gp_regs, GP_REG_SIZE);
-+ memcpy(regs->dc.b, par->dc_regs, DC_REG_SIZE);
-+ memcpy(regs->vp.b, par->df_regs, VP_REG_SIZE);
-+ memcpy(regs->fp.b, par->df_regs + VP_FP_START, FP_REG_SIZE);
-+
-+ /* Save the palettes */
-+ writel(0, par->dc_regs + 0x70);
-+
-+ for(i = 0; i < DC_PAL_SIZE; i++)
-+ regs->pal[i] = readl(par->dc_regs + 0x74);
-+
-+ writel(0, par->df_regs + 0x38);
-+
-+ for(i = 0; i <= 0xFF; i++)
-+ regs->gamma[i] = readl(par->df_regs + 0x40);
-+}
-+
-+static void lx_restore_regs(struct fb_info *info, struct geoderegs *regs)
-+{
-+ struct lxfb_par *par = info->par;
-+ u32 val, i;
-+
-+ /* == DOTPLL == */
-+
-+ lx_set_dotpll((u32) (regs->msr.dotpll >> 32));
-+
-+ /* MSRs */
-+
-+ wrmsrl(MSR_LX_DF_GLCONFIG, regs->msr.dfglcfg);
-+
-+ /* == GP == */
-+
-+ writel(regs->gp.r.dst_offset, par->gp_regs + 0x00);
-+ writel(regs->gp.r.src_offset, par->gp_regs + 0x04);
-+ writel(regs->gp.r.stride, par->gp_regs + 0x08);
-+ writel(regs->gp.r.wid_height, par->gp_regs + 0x0C);
-+ writel(regs->gp.r.src_color_fg, par->gp_regs + 0x10);
-+ writel(regs->gp.r.src_color_bg, par->gp_regs + 0x14);
-+ writel(regs->gp.r.pat_color_0, par->gp_regs + 0x18);
-+ writel(regs->gp.r.pat_color_1, par->gp_regs + 0x1C);
-+ writel(regs->gp.r.pat_color_2, par->gp_regs + 0x20);
-+ writel(regs->gp.r.pat_color_3, par->gp_regs + 0x24);
-+ writel(regs->gp.r.pat_color_4, par->gp_regs + 0x28);
-+ writel(regs->gp.r.pat_color_5, par->gp_regs + 0x2C);
-+ writel(regs->gp.r.pat_data_0, par->gp_regs + 0x30);
-+ writel(regs->gp.r.pat_data_1, par->gp_regs + 0x34);
-+
-+ /* Writing to these registers would cause a blt to happen */
-+ /* 0x38, 0x3c, 0x40 */
-+
-+ /* Status register (0x44) is read only */
-+
-+ writel(regs->gp.r.hst_src, par->gp_regs + 0x48);
-+ writel(regs->gp.r.base_offset, par->gp_regs + 0x4c);
-+ writel(regs->gp.r.cmd_top, par->gp_regs + 0x50);
-+ writel(regs->gp.r.cmd_bot, par->gp_regs + 0x54);
-+ writel(regs->gp.r.cmd_read, par->gp_regs + 0x58);
-+ writel(regs->gp.r.cmd_write, par->gp_regs + 0x5C);
-+ writel(regs->gp.r.ch3_offset, par->gp_regs + 0x60);
-+ writel(regs->gp.r.ch3_mode_str, par->gp_regs + 0x64);
-+ writel(regs->gp.r.ch3_width, par->gp_regs + 0x6C);
-+ writel(regs->gp.r.ch3_hsrc, par->gp_regs + 0x70);
-+
-+ /* FIXME: Restore the LUT data here */
-+
-+ writel(regs->gp.r.int_cntrl, par->gp_regs + 0x70);
-+
-+ /* == DC == */
-+
-+ /* Write the unlock value */
-+ writel(0x4758, par->dc_regs + 0x00);
-+
-+ /* Write the palette data first */
-+
-+ writel(0, par->dc_regs + 0x70);
-+
-+ for(i = 0; i < DC_PAL_SIZE; i++)
-+ writel(regs->pal[i], par->dc_regs + 0x74);
-+
-+ /* MSRs */
-+ wrmsrl(MSR_LX_DC_SPARE, regs->msr.dcspare);
-+
-+ /* Write the gcfg register without the enables */
-+ writel(regs->dc.r.gcfg & ~0x0F, par->dc_regs + 0x04);
-+
-+ /* Write the vcfg register without the enables */
-+ writel(regs->dc.r.dcfg & ~0x19, par->dc_regs + 0x08);
-+
-+ /* Write the rest of the active registers */
-+ writel(regs->dc.r.arb, par->dc_regs + 0x0C);
-+ writel(regs->dc.r.fb_st_offset, par->dc_regs + 0x10);
-+ writel(regs->dc.r.cb_st_offset, par->dc_regs + 0x14);
-+ writel(regs->dc.r.curs_st_offset, par->dc_regs + 0x18);
-+ writel(regs->dc.r.icon_st_offset, par->dc_regs + 0x1C);
-+ writel(regs->dc.r.vid_y_st_offset, par->dc_regs + 0x20);
-+ writel(regs->dc.r.vid_u_st_offset, par->dc_regs + 0x24);
-+ writel(regs->dc.r.vid_v_st_offset, par->dc_regs + 0x28);
-+ writel(regs->dc.r.dctop, par->dc_regs + 0x2c);
-+ writel(regs->dc.r.line_size, par->dc_regs + 0x30);
-+ writel(regs->dc.r.gfx_pitch, par->dc_regs + 0x34);
-+ writel(regs->dc.r.vid_yuv_pitch, par->dc_regs + 0x38);
-+ writel(regs->dc.r.h_active_timing, par->dc_regs + 0x40);
-+ writel(regs->dc.r.h_blank_timing, par->dc_regs + 0x44);
-+ writel(regs->dc.r.h_sync_timing, par->dc_regs + 0x48);
-+ writel(regs->dc.r.v_active_timing, par->dc_regs + 0x50);
-+ writel(regs->dc.r.v_blank_timing, par->dc_regs + 0x54);
-+ writel(regs->dc.r.v_sync_timing, par->dc_regs + 0x58);
-+ writel(regs->dc.r.fbactive, par->dc_regs + 0x5c);
-+ writel(regs->dc.r.dc_cursor_x, par->dc_regs + 0x60);
-+ writel(regs->dc.r.dc_cursor_y, par->dc_regs + 0x64);
-+ writel(regs->dc.r.dc_icon_x, par->dc_regs + 0x68);
-+
-+ /* Skip register 0x6C (line_cnt), 0x70/0x74 (palette),
-+ 0x78 (diagnostic), and 0x7c (diagnostic)
-+ */
-+
-+ writel(regs->dc.r.dc_vid_ds_delta, par->dc_regs + 0x80);
-+ writel(regs->dc.r.gliu0_mem_offset, par->dc_regs + 0x84);
-+ writel(regs->dc.r.dv_ctl, par->dc_regs + 0x88);
-+ writel(regs->dc.r.dv_acc, par->dc_regs + 0x8C);
-+
-+ writel(regs->dc.r.gfx_scale, par->dc_regs + 0x90);
-+ writel(regs->dc.r.irq_filt_ctl, par->dc_regs + 0x94);
-+ writel(regs->dc.r.filt_coeff1, par->dc_regs + 0x98);
-+ writel(regs->dc.r.filt_coeff2, par->dc_regs + 0x9C);
-+ writel(regs->dc.r.vbi_event_ctl, par->dc_regs + 0xA0);
-+
-+ writel(regs->dc.r.vbi_odd_ctl, par->dc_regs + 0xA4);
-+ writel(regs->dc.r.vbi_hor, par->dc_regs + 0xA8);
-+ writel(regs->dc.r.vbi_ln_odd, par->dc_regs + 0xAC);
-+ writel(regs->dc.r.vbi_ln_event, par->dc_regs + 0xB0);
-+ writel(regs->dc.r.vbi_pitch, par->dc_regs + 0xB4);
-+ writel(regs->dc.r.clr_key, par->dc_regs + 0xB8);
-+ writel(regs->dc.r.clr_key_mask, par->dc_regs + 0xBC);
-+
-+ writel(regs->dc.r.clr_key_x, par->dc_regs + 0xC0);
-+ writel(regs->dc.r.clr_key_y, par->dc_regs + 0xC4);
-+ writel(regs->dc.r.irq, par->dc_regs + 0xC8);
-+ writel(regs->dc.r.genlk_ctrl, par->dc_regs + 0xD4);
-+
-+ writel(regs->dc.r.vid_even_y_st_offset, par->dc_regs + 0xD8);
-+ writel(regs->dc.r.vid_even_u_st_offset, par->dc_regs + 0xDC);
-+ writel(regs->dc.r.vid_even_v_st_offset, par->dc_regs + 0xE0);
-+
-+ writel(regs->dc.r.v_active_even_timing, par->dc_regs + 0xE4);
-+ writel(regs->dc.r.v_blank_even_timing, par->dc_regs + 0xE8);
-+ writel(regs->dc.r.v_sync_even_timing, par->dc_regs + 0xEC);
-+
-+ /* == VP == */
-+
-+ /* MSR */
-+ wrmsrl(MSR_LX_DF_PADSEL, regs->msr.padsel);
-+
-+ /* Write gamma information first */
-+
-+ writel(0, par->df_regs + 0x38);
-+
-+ for(i = 0; i <= 0xFF; i++)
-+ writel((u32) regs->gamma[i], par->df_regs + 0x40);
-+
-+ /* Don't enable video yet */
-+ writel((u32) regs->vp.r.vcfg & ~0x01, par->df_regs + 0x00);
-+
-+ /* Don't enable the CRT yet */
-+ writel((u32) regs->vp.r.dcfg & ~0x0F, par->df_regs + 0x08);
-+
-+ /* Write the rest of the VP registers */
-+
-+ writel((u32) regs->vp.r.vx, par->df_regs + 0x10);
-+ writel((u32) regs->vp.r.vy, par->df_regs + 0x18);
-+ writel((u32) regs->vp.r.vs, par->df_regs + 0x20);
-+ writel((u32) regs->vp.r.vck, par->df_regs + 0x28);
-+ writel((u32) regs->vp.r.vcm, par->df_regs + 0x30);
-+ writel((u32) regs->vp.r.misc, par->df_regs + 0x50);
-+ writel((u32) regs->vp.r.ccs, par->df_regs + 0x58);
-+ writel((u32) regs->vp.r.vdc, par->df_regs + 0x78);
-+ writel((u32) regs->vp.r.vco, par->df_regs + 0x80);
-+ writel((u32) regs->vp.r.crc, par->df_regs + 0x88);
-+ writel((u32) regs->vp.r.vde, par->df_regs + 0x98);
-+ writel((u32) regs->vp.r.cck, par->df_regs + 0xA0);
-+ writel((u32) regs->vp.r.ccm, par->df_regs + 0xA8);
-+ writel((u32) regs->vp.r.cc1, par->df_regs + 0xB0);
-+ writel((u32) regs->vp.r.cc2, par->df_regs + 0xB8);
-+ writel((u32) regs->vp.r.a1x, par->df_regs + 0xC0);
-+ writel((u32) regs->vp.r.a1y, par->df_regs + 0xC8);
-+ writel((u32) regs->vp.r.a1c, par->df_regs + 0xD0);
-+ writel((u32) regs->vp.r.a1t, par->df_regs + 0xD8);
-+ writel((u32) regs->vp.r.a2x, par->df_regs + 0xE0);
-+ writel((u32) regs->vp.r.a2y, par->df_regs + 0xE8);
-+ writel((u32) regs->vp.r.a2c, par->df_regs + 0xF0);
-+ writel((u32) regs->vp.r.a2t, par->df_regs + 0xF8);
-+ writel((u32) regs->vp.r.a3x, par->df_regs + 0x100);
-+ writel((u32) regs->vp.r.a3y, par->df_regs + 0x108);
-+ writel((u32) regs->vp.r.a3c, par->df_regs + 0x110);
-+ writel((u32) regs->vp.r.a3t, par->df_regs + 0x118);
-+ writel((u32) regs->vp.r.vrr, par->df_regs + 0x120);
-+
-+ writel((u32) regs->vp.r.vye, par->df_regs + 0x138);
-+ writel((u32) regs->vp.r.a1ye, par->df_regs + 0x140);
-+ writel((u32) regs->vp.r.a2ye, par->df_regs + 0x148);
-+ writel((u32) regs->vp.r.a3ye, par->df_regs + 0x150);
-+
-+ /* == FP == */
-+
-+ writel((u32) regs->fp.r.pt1, par->df_regs + 0x400);
-+ writel((u32) regs->fp.r.pt2, par->df_regs + 0x408);
-+ writel((u32) regs->fp.r.dfc, par->df_regs + 0x418);
-+ writel(regs->fp.r.dca, par->df_regs + 0x448);
-+ writel(regs->fp.r.dmd, par->df_regs + 0x450);
-+ writel(regs->fp.r.crc, par->df_regs + 0x458);
-+
-+ /* Final enables */
-+
-+ val = readl(par->df_regs + 0x410);
-+
-+ /* Control the panel */
-+ if (regs->fp.r.pm & (1 << 24)) {
-+
-+ if (!(val & 0x09))
-+ writel(regs->fp.r.pm, par->df_regs + 0x410);
-+ }
-+ else {
-+ if (!(val & 0x05))
-+ writel(regs->fp.r.pm, par->df_regs + 0x410);
-+ }
-+
-+ /* Turn everything on */
-+
-+ writel(regs->dc.r.gcfg, par->dc_regs + 0x04);
-+ writel((u32) regs->vp.r.vcfg, par->df_regs + 0x00);
-+ writel((u32) regs->vp.r.dcfg, par->df_regs + 0x08);
-+ writel(regs->dc.r.dcfg, par->dc_regs + 0x08);
-+}
-+
-+static int lx_power_on = 1;
-+
-+int lx_shutdown(struct fb_info *info)
-+{
-+ struct lxfb_par *par = info->par;
-+
-+ if (lx_power_on == 0)
-+ return 0;
-+
-+ writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
-+ lx_save_regs(info, &saved_regs);
-+ lx_graphics_disable(info);
-+
-+ lx_power_on = 0;
-+ return 0;
-+}
-+
-+int lx_powerup(struct fb_info *info)
-+{
-+ struct lxfb_par *par = info->par;
-+
-+ if (lx_power_on == 1)
-+ return 0;
-+
-+ lx_restore_regs(info, &saved_regs);
-+ writel(0, par->dc_regs + DC_UNLOCK);
-+
-+ lx_power_on = 1;
-+ return 0;
-+}
-diff --git a/drivers/video/geode/suspend_gx.c b/drivers/video/geode/suspend_gx.c
-new file mode 100644
-index 0000000..43c25be
---- /dev/null
-+++ b/drivers/video/geode/suspend_gx.c
-@@ -0,0 +1,272 @@
-+#include <linux/fb.h>
-+#include <asm/io.h>
-+#include <asm/msr.h>
-+
-+#include "geodefb.h"
-+#include "video_gx.h"
-+
-+void gx_set_dotpll(struct fb_info *info, struct geoderegs *regs)
-+{
-+ int timeout = 1000;
-+
-+ u64 rstpll, dotpll;
-+
-+ rdmsrl(MSR_GLCP_SYS_RSTPLL, rstpll);
-+ rdmsrl(MSR_GLCP_DOTPLL, dotpll);
-+
-+ dotpll &= 0x00000000ffffffffull;
-+ dotpll |= regs->msr.dotpll & 0xffffffff00000000ull;
-+
-+ dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
-+ dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
-+
-+ wrmsrl(MSR_GLCP_DOTPLL, dotpll);
-+
-+ rstpll |= (regs->msr.rstpll &
-+ ( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 |
-+ MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 |
-+ MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3));
-+
-+ wrmsrl(MSR_GLCP_SYS_RSTPLL, rstpll);
-+ dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
-+ wrmsrl(MSR_GLCP_DOTPLL, dotpll);
-+
-+ do {
-+ rdmsrl(MSR_GLCP_DOTPLL, dotpll);
-+ } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
-+}
-+
-+/* FIXME: Make sure nothing is read to clear */
-+
-+void gx_save_regs(struct fb_info *info, struct geoderegs *regs)
-+{
-+ struct geodefb_par *par = info->par;
-+ int i;
-+
-+ /* Wait for the BLT engine to stop being busy */
-+ while(readl(par->gp_regs + 0x44) & 0x05);
-+
-+ rdmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel);
-+ rdmsrl(MSR_GLCP_DOTPLL, regs->msr.dotpll);
-+ rdmsrl(MSR_GLCP_SYS_RSTPLL, regs->msr.rstpll);
-+
-+ writel(0x4758, par->dc_regs + 0x00);
-+
-+ memcpy(regs->gp.b, par->gp_regs, GP_REG_SIZE);
-+ memcpy(regs->dc.b, par->dc_regs, DC_REG_SIZE);
-+ memcpy(regs->vp.b, par->vid_regs, VP_REG_SIZE);
-+ memcpy(regs->fp.b, par->vid_regs + 0x400, FP_REG_SIZE);
-+
-+ /* Save the palettes */
-+ writel(0, par->dc_regs + 0x70);
-+
-+ for(i = 0; i < DC_PAL_SIZE; i++)
-+ regs->pal[i] = readl(par->dc_regs + 0x74);
-+
-+ writel(0, par->vid_regs + 0x38);
-+
-+ for(i = 0; i < 0xFF; i++)
-+ regs->gamma[i] = readl(par->vid_regs + 0x40);
-+}
-+
-+void gx_restore_regs(struct fb_info *info, struct geoderegs *regs)
-+{
-+ struct geodefb_par *par = info->par;
-+ u32 val, i;
-+
-+ /* DOTPLL */
-+ gx_set_dotpll(info, regs);
-+
-+ /* GP */
-+
-+ writel(regs->gp.r.dst_offset, par->gp_regs + 0x00);
-+ writel(regs->gp.r.src_offset, par->gp_regs + 0x04);
-+ writel(regs->gp.r.stride, par->gp_regs + 0x08);
-+ writel(regs->gp.r.wid_height, par->gp_regs + 0x0C);
-+ writel(regs->gp.r.src_color_fg, par->gp_regs + 0x10);
-+ writel(regs->gp.r.src_color_bg, par->gp_regs + 0x14);
-+ writel(regs->gp.r.pat_color_0, par->gp_regs + 0x18);
-+ writel(regs->gp.r.pat_color_1, par->gp_regs + 0x1C);
-+ writel(regs->gp.r.pat_color_2, par->gp_regs + 0x20);
-+ writel(regs->gp.r.pat_color_3, par->gp_regs + 0x24);
-+ writel(regs->gp.r.pat_color_4, par->gp_regs + 0x28);
-+ writel(regs->gp.r.pat_color_5, par->gp_regs + 0x2C);
-+ writel(regs->gp.r.pat_data_0, par->gp_regs + 0x30);
-+ writel(regs->gp.r.pat_data_1, par->gp_regs + 0x34);
-+
-+ /* Don't write the raster / vector / blt mode regs */
-+ /* status register is read only */
-+
-+ writel(regs->gp.r.hst_src, par->gp_regs + 0x48);
-+ writel(regs->gp.r.base_offset, par->gp_regs + 0x4c);
-+
-+ /* DC */
-+
-+ /* Write the unlock value */
-+ writel(0x4758, par->dc_regs + 0x00);
-+
-+ writel(0, par->dc_regs + 0x70);
-+
-+ for(i = 0; i < DC_PAL_SIZE; i++)
-+ writel(regs->pal[i], par->dc_regs + 0x74);
-+
-+ /* Write the gcfg register without the enables */
-+ writel(regs->dc.r.gcfg & ~0x0F, par->dc_regs + 0x04);
-+
-+ /* Write the vcfg register without the enables */
-+ writel(regs->dc.r.dcfg & ~0x19, par->dc_regs + 0x08);
-+
-+ /* Write the rest of the active registers */
-+
-+ writel(regs->dc.r.fb_st_offset, par->dc_regs + 0x10);
-+ writel(regs->dc.r.cb_st_offset, par->dc_regs + 0x14);
-+ writel(regs->dc.r.curs_st_offset, par->dc_regs + 0x18);
-+ writel(regs->dc.r.icon_st_offset, par->dc_regs + 0x1C);
-+ writel(regs->dc.r.vid_y_st_offset, par->dc_regs + 0x20);
-+ writel(regs->dc.r.vid_u_st_offset, par->dc_regs + 0x24);
-+ writel(regs->dc.r.vid_v_st_offset, par->dc_regs + 0x28);
-+ writel(regs->dc.r.line_size, par->dc_regs + 0x30);
-+ writel(regs->dc.r.gfx_pitch, par->dc_regs + 0x34);
-+ writel(regs->dc.r.vid_yuv_pitch, par->dc_regs + 0x38);
-+ writel(regs->dc.r.h_active_timing, par->dc_regs + 0x40);
-+ writel(regs->dc.r.h_blank_timing, par->dc_regs + 0x44);
-+ writel(regs->dc.r.h_sync_timing, par->dc_regs + 0x48);
-+ writel(regs->dc.r.v_active_timing, par->dc_regs + 0x50);
-+ writel(regs->dc.r.v_blank_timing, par->dc_regs + 0x54);
-+ writel(regs->dc.r.v_sync_timing, par->dc_regs + 0x58);
-+ writel(regs->dc.r.dc_cursor_x, par->dc_regs + 0x60);
-+ writel(regs->dc.r.dc_cursor_y, par->dc_regs + 0x64);
-+ writel(regs->dc.r.dc_icon_x, par->dc_regs + 0x68);
-+
-+ /* Don't write the line_cnt or diag registers */
-+
-+ writel(regs->dc.r.dc_vid_ds_delta, par->dc_regs + 0x80);
-+ writel(regs->dc.r.gliu0_mem_offset, par->dc_regs + 0x84);
-+ writel(regs->dc.r.dv_acc, par->dc_regs + 0x8C);
-+
-+ /* VP */
-+
-+ /* MSR */
-+ wrmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel);
-+
-+ writel(0, par->vid_regs + 0x38);
-+
-+ for(i = 0; i < 0xFF; i++)
-+ writel((u32) regs->gamma[i], par->vid_regs + 0x40);
-+
-+ /* Don't enable video yet */
-+ writel((u32) regs->vp.r.vcfg & ~0x01, par->vid_regs + 0x00);
-+
-+ /* Don't enable the CRT yet */
-+ writel((u32) regs->vp.r.dcfg & ~0x0F, par->vid_regs + 0x08);
-+
-+ /* Write the rest of the VP registers */
-+
-+ writel((u32) regs->vp.r.vx, par->vid_regs + 0x10);
-+ writel((u32) regs->vp.r.vy, par->vid_regs + 0x18);
-+ writel((u32) regs->vp.r.vs, par->vid_regs + 0x20);
-+ writel((u32) regs->vp.r.vck, par->vid_regs + 0x28);
-+ writel((u32) regs->vp.r.vcm, par->vid_regs + 0x30);
-+ writel((u32) regs->vp.r.misc, par->vid_regs + 0x50);
-+ writel((u32) regs->vp.r.ccs, par->vid_regs + 0x58);
-+ writel((u32) regs->vp.r.vdc, par->vid_regs + 0x78);
-+ writel((u32) regs->vp.r.vco, par->vid_regs + 0x80);
-+ writel((u32) regs->vp.r.crc, par->vid_regs + 0x88);
-+ writel((u32) regs->vp.r.vde, par->vid_regs + 0x98);
-+ writel((u32) regs->vp.r.cck, par->vid_regs + 0xA0);
-+ writel((u32) regs->vp.r.ccm, par->vid_regs + 0xA8);
-+ writel((u32) regs->vp.r.cc1, par->vid_regs + 0xB0);
-+ writel((u32) regs->vp.r.cc2, par->vid_regs + 0xB8);
-+ writel((u32) regs->vp.r.a1x, par->vid_regs + 0xC0);
-+ writel((u32) regs->vp.r.a1y, par->vid_regs + 0xC8);
-+ writel((u32) regs->vp.r.a1c, par->vid_regs + 0xD0);
-+ writel((u32) regs->vp.r.a1t, par->vid_regs + 0xD8);
-+ writel((u32) regs->vp.r.a2x, par->vid_regs + 0xE0);
-+ writel((u32) regs->vp.r.a2y, par->vid_regs + 0xE8);
-+ writel((u32) regs->vp.r.a2c, par->vid_regs + 0xF0);
-+ writel((u32) regs->vp.r.a2t, par->vid_regs + 0xF8);
-+ writel((u32) regs->vp.r.a3x, par->vid_regs + 0x100);
-+ writel((u32) regs->vp.r.a3y, par->vid_regs + 0x108);
-+ writel((u32) regs->vp.r.a3c, par->vid_regs + 0x110);
-+ writel((u32) regs->vp.r.a3t, par->vid_regs + 0x118);
-+ writel((u32) regs->vp.r.vrr, par->vid_regs + 0x120);
-+
-+
-+ /* FP registers */
-+
-+ writel((u32) regs->fp.r.pt1, par->vid_regs + 0x400);
-+ writel((u32) regs->fp.r.pt2, par->vid_regs + 0x408);
-+
-+ writel((u32) regs->fp.r.dfc, par->vid_regs + 0x418);
-+ writel(regs->fp.r.blfsr, par->vid_regs + 0x420);
-+ writel(regs->fp.r.rlfsr, par->vid_regs + 0x428);
-+ writel(regs->fp.r.fmi, par->vid_regs + 0x430);
-+ writel(regs->fp.r.fmd, par->vid_regs + 0x438);
-+ writel(regs->fp.r.dca, par->vid_regs + 0x448);
-+ writel(regs->fp.r.dmd, par->vid_regs + 0x450);
-+ writel(regs->fp.r.crc, par->vid_regs + 0x458);
-+ writel(regs->fp.r.fbb, par->vid_regs + 0x460);
-+
-+ /* Final enables */
-+
-+ val = readl(par->vid_regs + 0x410);
-+
-+ /* Control the panel */
-+ if (regs->fp.r.pm & (1 << 24)) {
-+
-+ if (!(val & 0x09))
-+ writel(regs->fp.r.pm, par->vid_regs + 0x410);
-+ }
-+ else {
-+ if (!(val & 0x05))
-+ writel(regs->fp.r.pm, par->vid_regs + 0x410);
-+ }
-+
-+ /* Turn everything on */
-+
-+ writel(regs->dc.r.gcfg, par->dc_regs + 0x04);
-+ writel((u32) regs->vp.r.vcfg, par->vid_regs + 0x00);
-+ writel((u32) regs->vp.r.dcfg, par->vid_regs + 0x08);
-+ writel(regs->dc.r.dcfg, par->dc_regs + 0x08);
-+}
-+
-+
-+#ifdef DEBUG
-+
-+void dump_regs(struct fb_info *info, int mode) {
-+
-+ struct geodefb_par *par = info->par;
-+ u32 val;
-+ int i;
-+
-+ if (mode == 0) {
-+ for(i = 0; i < GP_REG_SIZE; i += 4) {
-+ val = readl(par->gp_regs + i);
-+ }
-+ }
-+
-+ if (mode == 1) {
-+ writel(0x4758, par->dc_regs + 0x00);
-+
-+ for(i = 0; i < DC_REG_SIZE; i += 4) {
-+ val = readl(par->dc_regs + i);
-+ printk("DC%x: %x\n", i, val);
-+ }
-+ }
-+
-+ if (mode == 2) {
-+ for(i = 0; i < VP_REG_SIZE; i += 8) {
-+ val = readl(par->vid_regs + i);
-+ printk("VP%x: %x\n", i, val);
-+ }
-+ }
-+
-+ if (mode == 3) {
-+ for(i = 0; i < FP_REG_SIZE; i += 8) {
-+ val = readl(par->vid_regs + 0x400 + i);
-+ printk("FP%x: %x\n", i, val);
-+ }
-+ }
-+}
-+
-+#endif
-diff --git a/drivers/video/geode/video_gx.c b/drivers/video/geode/video_gx.c
-index 7f3f18d..e282e74 100644
---- a/drivers/video/geode/video_gx.c
-+++ b/drivers/video/geode/video_gx.c
-@@ -16,10 +16,14 @@
- #include <asm/io.h>
- #include <asm/delay.h>
- #include <asm/msr.h>
-+#include <asm/olpc.h>
-
- #include "geodefb.h"
- #include "video_gx.h"
-+#include "display_gx.h"
-
-+/* This structure is used to store the saved registers during suspend */
-+static struct geoderegs gx_saved_regs;
-
- /*
- * Tables of register settings for various DOTCLKs.
-@@ -58,7 +62,7 @@ static const struct gx_pll_entry gx_pll_table_48MHz[] = {
- { 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */
- { 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */
- { 13333, 0, 0x00000052 }, /* 75.0000 */
-- { 12698, 0, 0x00000056 }, /* 78.7500 */
-+ { 12698, 0, 0x00000056 }, /* 78.7500 */
- { 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */
- { 11135, PREMULT2, 0x00000262 }, /* 89.8000 */
- { 10582, 0, 0x000002D2 }, /* 94.5000 */
-@@ -117,8 +121,9 @@ static const struct gx_pll_entry gx_pll_table_14MHz[] = {
- { 4357, 0, 0x0000057D }, /* 229.5000 */
- };
-
--static void gx_set_dclk_frequency(struct fb_info *info)
-+void gx_set_dclk_frequency(struct fb_info *info)
- {
-+ struct geodefb_par *par = info->par;
- const struct gx_pll_entry *pll_table;
- int pll_table_len;
- int i, best_i;
-@@ -173,115 +178,169 @@ static void gx_set_dclk_frequency(struct fb_info *info)
- do {
- rdmsrl(MSR_GLCP_DOTPLL, dotpll);
- } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
-+
-+ par->curdclk = pll_table[best_i].dotpll_value;
- }
-
--static void
--gx_configure_tft(struct fb_info *info)
-+/* Find out the current clock - we will use this information to avoid
-+ re-programming it if we don't need to */
-+
-+unsigned int gx_get_dclk(struct fb_info *info)
- {
-- struct geodefb_par *par = info->par;
-- unsigned long val;
-- unsigned long fp;
-+ const struct gx_pll_entry *pll_table;
-+ int pll_table_len;
-+ u64 dotpll;
-+ int i;
-
-- /* Set up the DF pad select MSR */
-+ if (cpu_data->x86_mask == 1) {
-+ pll_table = gx_pll_table_14MHz;
-+ pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
-+ } else {
-+ pll_table = gx_pll_table_48MHz;
-+ pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
-+ }
-
-- rdmsrl(GX_VP_MSR_PAD_SELECT, val);
-- val &= ~GX_VP_PAD_SELECT_MASK;
-- val |= GX_VP_PAD_SELECT_TFT;
-- wrmsrl(GX_VP_MSR_PAD_SELECT, val);
-+ rdmsrl(MSR_GLCP_DOTPLL, dotpll);
-
-- /* Turn off the panel */
-+ for(i = 0; i < pll_table_len; i++) {
-+ if (pll_table[i].dotpll_value == (u32) (dotpll >> 32))
-+ break;
-+ }
-
-- fp = readl(par->vid_regs + GX_FP_PM);
-- fp &= ~GX_FP_PM_P;
-- writel(fp, par->vid_regs + GX_FP_PM);
-+ return (i == pll_table_len) ? 0 : pll_table[i].pixclock;
-+}
-+
-+
-+#define CMP(val, mask, res) (((val) & (mask)) == (res))
-
-- /* Set timing 1 */
-+static void
-+gx_configure_tft(struct fb_info *info) {
-
-- fp = readl(par->vid_regs + GX_FP_PT1);
-- fp &= GX_FP_PT1_VSIZE_MASK;
-- fp |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT;
-- writel(fp, par->vid_regs + GX_FP_PT1);
-+ struct geodefb_par *par = info->par;
-+ u32 val, fp = 0, fp1, fp2, sync = 0;
-
-- /* Timing 2 */
-- /* Set bits that are always on for TFT */
-+ /* Set up the DF pad select MSR */
-
-- fp = 0x0F100000;
-+ rdmsrl(GX_VP_MSR_PAD_SELECT, val);
-
-- /* Add sync polarity */
-+ if ((val & GX_VP_PAD_SELECT_MASK) != GX_VP_PAD_SELECT_TFT) {
-+ val &= ~GX_VP_PAD_SELECT_MASK;
-+ val |= GX_VP_PAD_SELECT_TFT;
-+ wrmsrl(GX_VP_MSR_PAD_SELECT, val);
-+ }
-
- if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
-- fp |= GX_FP_PT2_VSP;
-+ sync |= GX_FP_PT2_VSP;
-
- if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
-- fp |= GX_FP_PT2_HSP;
-+ sync |= GX_FP_PT2_HSP;
-
-- writel(fp, par->vid_regs + GX_FP_PT2);
-+ /* We only need to turn off the panel if something changed */
-
-- /* Set the dither control */
-- writel(0x70, par->vid_regs + GX_FP_DFC);
-+ fp1 = readl(par->vid_regs + GX_FP_PT1);
-+ fp2 = readl(par->vid_regs + GX_FP_PT2);
-+
-+ if (!CMP(fp1, GX_FP_PT1_VSIZE_MASK, info->var.yres << GX_FP_PT1_VSIZE_SHIFT) ||
-+ (fp2 != (0x0F100000 | sync))) {
-
-- /* Enable the FP data and power (in case the BIOS didn't) */
-+ /* Turn off the panel */
-
-- fp = readl(par->vid_regs + GX_DCFG);
-- fp |= GX_DCFG_FP_PWR_EN | GX_DCFG_FP_DATA_EN;
-- writel(fp, par->vid_regs + GX_DCFG);
-+#ifdef NOTUSED
-+ /* Do we really need to turn off the panel? */
-+ /* Possibly - we have a glitch somewhere */
-
-- /* Unblank the panel */
-+ fp = readl(par->vid_regs + GX_FP_PM);
-+ fp &= ~GX_FP_PM_P;
-+ writel(fp, par->vid_regs + GX_FP_PM);
-+#endif
-+
-+ /* Timing 1 */
-+ fp1 &= GX_FP_PT1_VSIZE_MASK;
-+ fp1 |= info->var.yres << GX_FP_PT1_VSIZE_SHIFT;
-+ writel(fp, par->vid_regs + GX_FP_PT1);
-+
-+ /* Timing 2 */
-+ writel(0x0F100000 | sync, par->vid_regs + GX_FP_PT2);
-+ }
-+
-+ /* Set the dither control */
-+ if (readl(par->vid_regs + GX_FP_DFC) != 0x70) {
-+ writel(0x70, par->vid_regs + GX_FP_DFC);
-+ }
-+
-+ /* Turn on the panel */
-
- fp = readl(par->vid_regs + GX_FP_PM);
-- fp |= GX_FP_PM_P;
-- writel(fp, par->vid_regs + GX_FP_PM);
-+
-+ if (!(fp & 0x09))
-+ writel(fp | GX_FP_PM_P, par->vid_regs + GX_FP_PM);
- }
-
-+#define DCFG_DEFAULT_VAL GX_DCFG_CRT_SYNC_SKW_DFLT | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN | \
-+GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN
-+
- static void gx_configure_display(struct fb_info *info)
- {
- struct geodefb_par *par = info->par;
-- u32 dcfg, misc;
-+ u32 dcfg, misc, sync = 0;
-
- /* Set up the MISC register */
--
- misc = readl(par->vid_regs + GX_MISC);
-
-- /* Power up the DAC */
-- misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN);
-+ /* We leave gamma enabled if it was already enabled.
-+ Although the hardware enables it without setting
-+ up the gamma table, the BIOS or bootloader ought
-+ to have either disabled it or loaded a table by now */
-
-- /* Disable gamma correction */
-- misc |= GX_MISC_GAM_EN;
-
-- writel(misc, par->vid_regs + GX_MISC);
-
-- /* Write the display configuration */
-- dcfg = readl(par->vid_regs + GX_DCFG);
-+ if (par->enable_crt) {
-+ /* Power up the CRT DACs */
-+ if (misc & ( GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN)) {
-+ misc &= ~(GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN);
-+ writel(misc, par->vid_regs + GX_MISC);
-+ }
-
-- /* Disable hsync and vsync */
-- dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
-- writel(dcfg, par->vid_regs + GX_DCFG);
-+ if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
-+ sync |= GX_DCFG_CRT_HSYNC_POL;
-
-- /* Clear bits from existing mode. */
-- dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
-- | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL
-- | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
-+ if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
-+ sync |= GX_DCFG_CRT_VSYNC_POL;
-+ }
-+ else {
-+ /* Turn off the CRT DACs in FP mode - we don't need them */
-+ if ((misc & (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN))) {
-+ misc |= (GX_MISC_A_PWRDN | GX_MISC_DAC_PWRDN);
-+ writel(misc, par->vid_regs + GX_MISC);
-+ }
-+ }
-
-- /* Set default sync skew. */
-- dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT;
-+ /* Write the display configuration */
-+ dcfg = readl(par->vid_regs + GX_DCFG);
-
-- /* Enable hsync and vsync. */
-- dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN;
-+ if (!CMP(dcfg, DCFG_DEFAULT_VAL | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL,
-+ DCFG_DEFAULT_VAL | sync)) {
-
-- /* Sync polarities. */
-- if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
-- dcfg |= GX_DCFG_CRT_HSYNC_POL;
-- if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
-- dcfg |= GX_DCFG_CRT_VSYNC_POL;
-+ /* Disable hsync and vsync */
-+ dcfg &= ~(GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
-+ writel(dcfg, par->vid_regs + GX_DCFG);
-
-- /* Enable the display logic */
-- /* Set up the DACS to blank normally */
-+ /* Clear bits from existing mode. */
-+ dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
-+ | GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL
-+ | GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
-
-- dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN;
-+ /* Set default sync skew. */
-+ dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT;
-
-- /* Enable the external DAC VREF? */
-+ /* Enable hsync and vsync. */
-+ dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN;
-
-- writel(dcfg, par->vid_regs + GX_DCFG);
-+ /* Enable the display logic */
-+ dcfg |= GX_DCFG_CRT_EN | GX_DCFG_DAC_BL_EN;
-+
-+ writel(dcfg, par->vid_regs + GX_DCFG);
-+ }
-
- /* Set up the flat panel (if it is enabled) */
-
-@@ -289,6 +348,100 @@ static void gx_configure_display(struct fb_info *info)
- gx_configure_tft(info);
- }
-
-+int gxfb_powerdown(struct fb_info *info)
-+{
-+ struct geodefb_par *par = info->par;
-+
-+ /* We're already suspended */
-+
-+ if (par->state != FB_POWER_STATE_ON)
-+ return 0;
-+
-+ /* Save the registers */
-+ gx_save_regs(info, &gx_saved_regs);
-+
-+ /* Shut down the engine */
-+
-+ writel(gx_saved_regs.vp.r.vcfg & ~0x01, par->vid_regs + GX_VCFG);
-+ writel(gx_saved_regs.vp.r.dcfg & ~0x0F, par->vid_regs + GX_DCFG);
-+
-+ /* Turn off the flat panel unless we are attached to a DCON */
-+ if (!olpc_has_dcon())
-+ writel(gx_saved_regs.fp.r.pm & ~GX_FP_PM_P, par->vid_regs + GX_FP_PM);
-+
-+ writel(0x4758, par->dc_regs + DC_UNLOCK);
-+
-+ writel(gx_saved_regs.dc.r.gcfg & ~0x0F,
-+ par->dc_regs + DC_GENERAL_CFG);
-+
-+ writel(gx_saved_regs.dc.r.dcfg & ~0x19,
-+ par->dc_regs + DC_DISPLAY_CFG);
-+
-+ par->state = FB_POWER_STATE_SUSPEND;
-+
-+ return 0;
-+}
-+
-+int gxfb_powerup(struct fb_info *info)
-+{
-+ struct geodefb_par *par = info->par;
-+ u32 val;
-+
-+ if (par->state == FB_POWER_STATE_SUSPEND) {
-+
-+ writel(gx_saved_regs.dc.r.dcfg,
-+ par->dc_regs + DC_DISPLAY_CFG);
-+
-+ writel(gx_saved_regs.vp.r.vcfg, par->vid_regs + GX_VCFG);
-+ writel(gx_saved_regs.vp.r.dcfg, par->vid_regs + GX_DCFG);
-+
-+ val = readl(par->vid_regs + GX_FP_PM);
-+
-+ /* power up the panel if it needs it; we don't always power it down */
-+ if (!(val & 0x09)) {
-+ writel(gx_saved_regs.fp.r.pm, par->vid_regs + GX_FP_PM);
-+ mdelay(64);
-+ }
-+ }
-+
-+ /* If the panel is currently on its way up, then wait up to 100ms
-+ for it */
-+
-+ if (readl(par->vid_regs + GX_FP_PM) & 0x08) {
-+ int i;
-+
-+ for(i = 0; i < 10; i++) {
-+ if (readl(par->vid_regs + GX_FP_PM) & 0x01)
-+ break;
-+
-+ mdelay(10);
-+ }
-+
-+ if (i == 10)
-+ printk(KERN_ERR "gxfb: Panel power up timed out\n");
-+ }
-+
-+ if (par->state == FB_POWER_STATE_ON)
-+ return 0;
-+
-+ switch(par->state) {
-+ case FB_POWER_STATE_OFF:
-+ gx_restore_regs(info, &gx_saved_regs);
-+ break;
-+
-+ case FB_POWER_STATE_SUSPEND:
-+ /* Do this because it will turn on the FIFO which will
-+ start the line count */
-+ writel(gx_saved_regs.dc.r.gcfg,
-+ par->dc_regs + DC_GENERAL_CFG);
-+ writel(0x0, par->dc_regs + DC_UNLOCK);
-+ break;
-+ }
-+
-+ par->state = FB_POWER_STATE_ON;
-+ return 0;
-+}
-+
- static int gx_blank_display(struct fb_info *info, int blank_mode)
- {
- struct geodefb_par *par = info->par;
-@@ -315,6 +468,7 @@ static int gx_blank_display(struct fb_info *info, int blank_mode)
- default:
- return -EINVAL;
- }
-+
- dcfg = readl(par->vid_regs + GX_DCFG);
- dcfg &= ~(GX_DCFG_DAC_BL_EN
- | GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN);
-@@ -326,7 +480,7 @@ static int gx_blank_display(struct fb_info *info, int blank_mode)
- dcfg |= GX_DCFG_VSYNC_EN;
- writel(dcfg, par->vid_regs + GX_DCFG);
-
-- /* Power on/off flat panel. */
-+ /* Power on/off flat panel */
-
- if (par->enable_crt == 0) {
- fp_pm = readl(par->vid_regs + GX_FP_PM);
-@@ -340,8 +494,37 @@ static int gx_blank_display(struct fb_info *info, int blank_mode)
- return 0;
- }
-
-+extern struct fb_info *gxfb_info;
-+
-+/* This function controls the flatpanel power sequencing - this is used
-+ by the OLPC power management engine to enable the FP sequencing much
-+ earlier in the resume process
-+*/
-+
-+void gxfb_flatpanel_control(int state)
-+{
-+ struct geodefb_par *par = gxfb_info->par;
-+ u32 val, fp = readl(par->vid_regs + GX_FP_PM);
-+ val = fp;
-+
-+ /* Turn on the panel if it isn't aleady */
-+
-+ if (state) {
-+ if (!(val & 0x01))
-+ val |= GX_FP_PM_P;
-+ }
-+ else {
-+ if (!(val & 0x02))
-+ val &= ~GX_FP_PM_P;
-+ }
-+
-+ if (val != fp)
-+ writel(val, par->vid_regs + GX_FP_PM);
-+}
-+
- struct geode_vid_ops gx_vid_ops = {
- .set_dclk = gx_set_dclk_frequency,
-+ .get_dclk = gx_get_dclk,
- .configure_display = gx_configure_display,
- .blank_display = gx_blank_display,