-From 8a0e33bd81eafd86252acf7d7ff1bd5362208d7a Mon Sep 17 00:00:00 2001
+From 4f214b1ead0af7439921637645cb63f378516175 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Sat, 21 Jan 2012 18:48:38 +0100
Subject: [PATCH 33/34] b43: add workaround for b43 on pcie bus of bcm4716.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
- drivers/net/wireless/b43/b43.h | 25 +++++++++++++++++++++++++
+ drivers/net/wireless/b43/b43.h | 26 ++++++++++++++++++++++++++
drivers/net/wireless/b43/bus.h | 10 ++++++++++
drivers/net/wireless/b43/phy_common.c | 6 ++++++
drivers/net/wireless/b43/phy_n.c | 10 +++++-----
- 4 files changed, 46 insertions(+), 5 deletions(-)
+ 4 files changed, 47 insertions(+), 5 deletions(-)
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
-@@ -1016,6 +1016,31 @@ static inline bool b43_using_pio_transfe
+@@ -1044,6 +1044,32 @@ static inline bool b43_using_pio_transfe
return dev->__using_pio_transfers;
}
+ * transactions. As a fix, a read after write is performed on certain places
+ * in the code. Older chips and the newer 5357 family don't require this fix.
+ */
-+#ifdef CONFIG_BCM47XX
++#ifdef CONFIG_BCM47XX_BCMA
+#include <asm/mach-bcm47xx/bcm47xx.h>
+static inline void b43_wflush16(struct b43_wldev *dev, u16 offset, u16 value)
+{
+ if (b43_bus_host_is_pci(dev->dev) &&
++ bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA &&
+ (bcm47xx_bus.bcma.bus.chipinfo.id == 0x4716 ||
+ bcm47xx_bus.bcma.bus.chipinfo.id == 0x5300)) {
+ b43_write16(dev, offset, value);
dev->phy.writes_counter = 0;
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
-@@ -4104,14 +4104,14 @@ static inline void check_phyreg(struct b
+@@ -4837,14 +4837,14 @@ static inline void check_phyreg(struct b
static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
{
check_phyreg(dev, reg);
b43_write16(dev, B43_MMIO_PHY_DATA, value);
}
-@@ -4119,7 +4119,7 @@ static void b43_nphy_op_maskset(struct b
+@@ -4852,7 +4852,7 @@ static void b43_nphy_op_maskset(struct b
u16 set)
{
check_phyreg(dev, reg);
- b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
+ b43_wflush16(dev, B43_MMIO_PHY_CONTROL, reg);
- b43_write16(dev, B43_MMIO_PHY_DATA,
- (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
+ b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
}
-@@ -4131,7 +4131,7 @@ static u16 b43_nphy_op_radio_read(struct
+
+@@ -4863,7 +4863,7 @@ static u16 b43_nphy_op_radio_read(struct
/* N-PHY needs 0x100 for read access */
reg |= 0x100;
return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
}
-@@ -4140,7 +4140,7 @@ static void b43_nphy_op_radio_write(stru
+@@ -4872,7 +4872,7 @@ static void b43_nphy_op_radio_write(stru
/* Register 1 is a 32-bit register. */
B43_WARN_ON(reg == 1);