-diff -urN linux.old/arch/mips/bcm947xx/cfe_env.c linux.dev/arch/mips/bcm947xx/cfe_env.c
---- linux.old/arch/mips/bcm947xx/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/cfe_env.c 2007-01-25 23:34:01.000000000 +0100
-@@ -0,0 +1,232 @@
-+/*
-+ * CFE environment varialble access
-+ *
-+ * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+
-+#define NVRAM_SIZE (0x1ff0)
-+static char _nvdata[NVRAM_SIZE] __initdata;
-+static char _valuestr[256] __initdata;
-+
-+/*
-+ * TLV types. These codes are used in the "type-length-value"
-+ * encoding of the items stored in the NVRAM device (flash or EEPROM)
-+ *
-+ * The layout of the flash/nvram is as follows:
-+ *
-+ * <type> <length> <data ...> <type> <length> <data ...> <type_end>
-+ *
-+ * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
-+ * The "length" field marks the length of the data section, not
-+ * including the type and length fields.
-+ *
-+ * Environment variables are stored as follows:
-+ *
-+ * <type_env> <length> <flags> <name> = <value>
-+ *
-+ * If bit 0 (low bit) is set, the length is an 8-bit value.
-+ * If bit 0 (low bit) is clear, the length is a 16-bit value
-+ *
-+ * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
-+ * indicates the size of the length field.
-+ *
-+ * Flags are from the constants below:
-+ *
-+ */
-+#define ENV_LENGTH_16BITS 0x00 /* for low bit */
-+#define ENV_LENGTH_8BITS 0x01
-+
-+#define ENV_TYPE_USER 0x80
-+
-+#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
-+#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
-+
-+/*
-+ * The actual TLV types we support
-+ */
-+
-+#define ENV_TLV_TYPE_END 0x00
-+#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
-+
-+/*
-+ * Environment variable flags
-+ */
-+
-+#define ENV_FLG_NORMAL 0x00 /* normal read/write */
-+#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
-+#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
-+
-+#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
-+#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
-+
-+
-+/* *********************************************************************
-+ * _nvram_read(buffer,offset,length)
-+ *
-+ * Read data from the NVRAM device
-+ *
-+ * Input parameters:
-+ * buffer - destination buffer
-+ * offset - offset of data to read
-+ * length - number of bytes to read
-+ *
-+ * Return value:
-+ * number of bytes read, or <0 if error occured
-+ ********************************************************************* */
-+static int
-+_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
-+{
-+ int i;
-+ if (offset > NVRAM_SIZE)
-+ return -1;
-+
-+ for ( i = 0; i < length; i++) {
-+ buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
-+ }
-+ return length;
-+}
-+
-+
-+static char*
-+_strnchr(const char *dest,int c,size_t cnt)
-+{
-+ while (*dest && (cnt > 0)) {
-+ if (*dest == c) return (char *) dest;
-+ dest++;
-+ cnt--;
-+ }
-+ return NULL;
-+}
-+
-+
-+
-+/*
-+ * Core support API: Externally visible.
-+ */
-+
-+/*
-+ * Get the value of an NVRAM variable
-+ * @param name name of variable to get
-+ * @return value of variable or NULL if undefined
-+ */
-+
-+char*
-+cfe_env_get(unsigned char *nv_buf, char* name)
-+{
-+ int size;
-+ unsigned char *buffer;
-+ unsigned char *ptr;
-+ unsigned char *envval;
-+ unsigned int reclen;
-+ unsigned int rectype;
-+ int offset;
-+ int flg;
-+
-+ size = NVRAM_SIZE;
-+ buffer = &_nvdata[0];
-+
-+ ptr = buffer;
-+ offset = 0;
-+
-+ /* Read the record type and length */
-+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
-+ goto error;
-+ }
-+
-+ while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
-+
-+ /* Adjust pointer for TLV type */
-+ rectype = *(ptr);
-+ offset++;
-+ size--;
-+
-+ /*
-+ * Read the length. It can be either 1 or 2 bytes
-+ * depending on the code
-+ */
-+ if (rectype & ENV_LENGTH_8BITS) {
-+ /* Read the record type and length - 8 bits */
-+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
-+ goto error;
-+ }
-+ reclen = *(ptr);
-+ size--;
-+ offset++;
-+ }
-+ else {
-+ /* Read the record type and length - 16 bits, MSB first */
-+ if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
-+ goto error;
-+ }
-+ reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
-+ size -= 2;
-+ offset += 2;
-+ }
-+
-+ if (reclen > size)
-+ break; /* should not happen, bad NVRAM */
-+
-+ switch (rectype) {
-+ case ENV_TLV_TYPE_ENV:
-+ /* Read the TLV data */
-+ if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
-+ goto error;
-+ flg = *ptr++;
-+ envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
-+ if (envval) {
-+ *envval++ = '\0';
-+ memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
-+ _valuestr[(reclen-1)-(envval-ptr)] = '\0';
-+#if 0
-+ printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
-+#endif
-+ if(!strcmp(ptr, name)){
-+ return _valuestr;
-+ }
-+ if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
-+ return _valuestr;
-+ }
-+ break;
-+
-+ default:
-+ /* Unknown TLV type, skip it. */
-+ break;
-+ }
-+
-+ /*
-+ * Advance to next TLV
-+ */
-+
-+ size -= (int)reclen;
-+ offset += reclen;
-+
-+ /* Read the next record type */
-+ ptr = buffer;
-+ if (_nvram_read(nv_buf, ptr,offset,1) != 1)
-+ goto error;
-+ }
-+
-+error:
-+ return NULL;
-+
-+}
-+
-diff -urN linux.old/arch/mips/bcm947xx/include/nvram.h linux.dev/arch/mips/bcm947xx/include/nvram.h
---- linux.old/arch/mips/bcm947xx/include/nvram.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/include/nvram.h 2007-01-25 23:34:01.000000000 +0100
-@@ -0,0 +1,37 @@
-+/*
-+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#ifndef __NVRAM_H
-+#define __NVRAM_H
-+
-+struct nvram_header {
-+ u32 magic;
-+ u32 len;
-+ u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
-+ u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
-+ u32 config_ncdl; /* ncdl values for memc */
-+};
-+
-+struct nvram_tuple {
-+ char *name;
-+ char *value;
-+ struct nvram_tuple *next;
-+};
-+
-+#define NVRAM_HEADER 0x48534C46 /* 'FLSH' */
-+#define NVRAM_VERSION 1
-+#define NVRAM_HEADER_SIZE 20
-+#define NVRAM_SPACE 0x8000
-+
-+#define NVRAM_MAX_VALUE_LEN 255
-+#define NVRAM_MAX_PARAM_LEN 64
-+
-+char *nvram_get(const char *name);
-+
-+#endif
-diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c
---- linux.old/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/irq.c 2007-01-25 23:34:01.000000000 +0100
-@@ -0,0 +1,63 @@
-+/*
-+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/module.h>
-+#include <linux/smp.h>
-+#include <linux/types.h>
-+
-+#include <asm/cpu.h>
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+#include <asm/irq_cpu.h>
-+
-+void plat_irq_dispatch(void)
-+{
-+ u32 cause;
-+
-+ cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
-+
-+ clear_c0_status(cause);
-+
-+ if (cause & CAUSEF_IP7)
-+ do_IRQ(7);
-+ if (cause & CAUSEF_IP2)
-+ do_IRQ(2);
-+ if (cause & CAUSEF_IP3)
-+ do_IRQ(3);
-+ if (cause & CAUSEF_IP4)
-+ do_IRQ(4);
-+ if (cause & CAUSEF_IP5)
-+ do_IRQ(5);
-+ if (cause & CAUSEF_IP6)
-+ do_IRQ(6);
-+}
-+
-+void __init arch_init_irq(void)
-+{
-+ mips_cpu_irq_init(0);
-+}
-diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
---- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/Makefile 2007-01-26 01:38:18.000000000 +0100
-@@ -0,0 +1,7 @@
-+#
-+# Makefile for the BCM47xx specific kernel interface routines
-+# under Linux.
-+#
-+
-+obj-y := irq.o prom.o setup.o time.o
-+obj-y += nvram.o cfe_env.o
-diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
---- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/nvram.c 2007-01-26 01:14:42.000000000 +0100
-@@ -0,0 +1,131 @@
-+/*
-+ * BCM947xx nvram variable access
-+ *
-+ * Copyright 2006, Felix Fietkau <nbd@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ *
-+ * Copyright 2005, Broadcom Corporation
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/ssb/ssb.h>
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <linux/interrupt.h>
-+#include <linux/spinlock.h>
-+#include <linux/slab.h>
-+#include <asm/byteorder.h>
-+#include <asm/bootinfo.h>
-+#include <asm/addrspace.h>
-+#include <asm/io.h>
-+#include <asm/uaccess.h>
-+
-+#include <nvram.h>
-+
-+#define MB * 1048576
-+extern struct ssb_bus ssb;
-+
-+static char nvram_buf[NVRAM_SPACE];
-+static int cfe_env;
-+extern char *cfe_env_get(char *nv_buf, const char *name);
-+
-+/* Probe for NVRAM header */
-+static void __init early_nvram_init(void)
-+{
-+ struct ssb_mipscore *mcore = &ssb.mipscore;
-+ struct nvram_header *header;
-+ int i;
-+ u32 base, lim, off;
-+ u32 *src, *dst;
-+
-+ base = mcore->flash_window;
-+ lim = mcore->flash_window_size;
-+ cfe_env = 0;
-+
-+
-+ /* XXX: hack for supporting the CFE environment stuff on WGT634U */
-+ if (lim >= 8 MB) {
-+ src = (u32 *) KSEG1ADDR(base + 8 MB - 0x2000);
-+ dst = (u32 *) nvram_buf;
-+
-+ if ((*src & 0xff00ff) == 0x000001) {
-+ printk("early_nvram_init: WGT634U NVRAM found.\n");
-+
-+ for (i = 0; i < 0x1ff0; i++) {
-+ if (*src == 0xFFFFFFFF)
-+ break;
-+ *dst++ = *src++;
-+ }
-+ cfe_env = 1;
-+ return;
-+ }
-+ }
-+
-+ off = 0x20000;
-+ while (off <= lim) {
-+ /* Windowed flash access */
-+ header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
-+ if (header->magic == NVRAM_HEADER)
-+ goto found;
-+ off <<= 1;
-+ }
-+
-+ /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
-+ header = (struct nvram_header *) KSEG1ADDR(base + 4096);
-+ if (header->magic == NVRAM_HEADER)
-+ goto found;
-+
-+ header = (struct nvram_header *) KSEG1ADDR(base + 1024);
-+ if (header->magic == NVRAM_HEADER)
-+ goto found;
-+
-+ return;
-+
-+found:
-+ src = (u32 *) header;
-+ dst = (u32 *) nvram_buf;
-+ for (i = 0; i < sizeof(struct nvram_header); i += 4)
-+ *dst++ = *src++;
-+ for (; i < header->len && i < NVRAM_SPACE; i += 4)
-+ *dst++ = le32_to_cpu(*src++);
-+}
-+
-+char *nvram_get(const char *name)
-+{
-+ char *var, *value, *end, *eq;
-+
-+ if (!name)
-+ return NULL;
-+
-+ if (!nvram_buf[0])
-+ early_nvram_init();
-+
-+ if (cfe_env)
-+ return cfe_env_get(nvram_buf, name);
-+
-+ /* Look for name=value and return value */
-+ var = &nvram_buf[sizeof(struct nvram_header)];
-+ end = nvram_buf + sizeof(nvram_buf) - 2;
-+ end[0] = end[1] = '\0';
-+ for (; *var; var = value + strlen(value) + 1) {
-+ if (!(eq = strchr(var, '=')))
-+ break;
-+ value = eq + 1;
-+ if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
-+ return value;
-+ }
-+
-+ return NULL;
-+}
-diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
---- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/prom.c 2007-01-26 20:20:38.000000000 +0100
-@@ -0,0 +1,61 @@
-+/*
-+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/mm.h>
-+#include <linux/sched.h>
-+#include <linux/bootmem.h>
-+
-+#include <asm/addrspace.h>
-+#include <asm/bootinfo.h>
-+#include <asm/pmon.h>
-+
-+const char *get_system_type(void)
-+{
-+ return "Broadcom BCM47xx";
-+}
-+
-+void __init prom_init(void)
-+{
-+ unsigned long mem;
-+
-+ mips_machgroup = MACH_GROUP_BRCM;
-+ mips_machtype = MACH_BCM47XX;
-+
-+ cfe_setup(fw_arg0, fw_arg1, fw_arg2, fw_arg3);
-+
-+ /* Figure out memory size by finding aliases */
-+ for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
-+ if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
-+ *(unsigned long *)(prom_init))
-+ break;
-+ }
-+
-+ add_memory_region(0, mem, BOOT_MEM_RAM);
-+}
-+
-+unsigned long __init prom_free_prom_memory(void)
-+{
-+ return 0;
-+}
-diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
---- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/setup.c 2007-01-26 20:20:38.000000000 +0100
-@@ -0,0 +1,162 @@
-+/*
-+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
-+ * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
-+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
-+ * Copyright (C) 2006 Michael Buesch
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/types.h>
-+#include <linux/tty.h>
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial_reg.h>
-+#include <asm/bootinfo.h>
-+#include <asm/time.h>
-+#include <asm/reboot.h>
-+#include <asm/cfe.h>
-+#include <linux/pm.h>
-+#include <linux/ssb/ssb.h>
-+
-+#include <nvram.h>
-+
-+extern void bcm47xx_pci_init(void);
-+extern void bcm47xx_time_init(void);
-+
-+struct ssb_bus ssb;
-+
-+static void bcm47xx_machine_restart(char *command)
-+{
-+ printk(KERN_ALERT "Please stand by while rebooting the system...\n");
-+ local_irq_disable();
-+ /* CFE has a reboot callback, but that does not work.
-+ * Oopses with: Reserved instruction in kernel code.
-+ */
-+
-+ /* Set the watchdog timer to reset immediately */
-+//TODO sb_watchdog(sbh, 1);
-+ while (1)
-+ cpu_relax();
-+}
-+
-+static void bcm47xx_machine_halt(void)
-+{
-+ /* Disable interrupts and watchdog and spin forever */
-+ local_irq_disable();
-+//TODO sb_watchdog(sbh, 0);
-+ while (1)
-+ cpu_relax();
-+}
-+
-+static void e_aton(char *str, char *dest)
-+{
-+ int i = 0;
-+
-+ if (str == NULL) {
-+ memset(dest, 0, 6);
-+ return;
-+ }
-+
-+ for (;;) {
-+ dest[i++] = (char) simple_strtoul(str, NULL, 16);
-+ str += 2;
-+ if (!*str++ || i == 6)
-+ break;
-+ }
-+}
-+
-+static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
-+{
-+ // TODO
-+}
-+
-+static void bcm47xx_fill_sprom_nvram(struct ssb_sprom *sprom)
-+{
-+ char *s;
-+
-+ memset(sprom, 0, sizeof(struct ssb_sprom));
-+
-+ sprom->revision = 3;
-+ if ((s = nvram_get("et0macaddr")))
-+ e_aton(s, sprom->r1.et0mac);
-+ if ((s = nvram_get("et1macaddr")))
-+ e_aton(s, sprom->r1.et1mac);
-+ if ((s = nvram_get("et0phyaddr")))
-+ sprom->r1.et0phyaddr = simple_strtoul(s, NULL, 10);
-+ if ((s = nvram_get("et1phyaddr")))
-+ sprom->r1.et1phyaddr = simple_strtoul(s, NULL, 10);
-+}
-+
-+void __init plat_mem_setup(void)
-+{
-+ int i, err;
-+ char *s;
-+ struct ssb_mipscore *mcore;
-+
-+ err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_fill_sprom);
-+ if (err) {
-+ const char *msg = "Failed to initialize SSB bus (err %d)\n";
-+ cfe_printk(msg, err); /* Make sure the message gets out of the box. */
-+ panic(msg, err);
-+ }
-+ mcore = &ssb.mipscore;
-+
-+ /* FIXME: the nvram init depends on the ssb being fully initializes,
-+ * can't use the fill_sprom callback yet! */
-+ bcm47xx_fill_sprom_nvram(&ssb.sprom);
-+
-+ s = nvram_get("kernel_args");
-+ if (s && !strncmp(s, "console=ttyS1", 13)) {
-+ struct ssb_serial_port port;
-+
-+ cfe_printk("Swapping serial ports!\n");
-+ /* swap serial ports */
-+ memcpy(&port, &mcore->serial_ports[0], sizeof(port));
-+ memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
-+ memcpy(&mcore->serial_ports[1], &port, sizeof(port));
-+ }
-+
-+ for (i = 0; i < mcore->nr_serial_ports; i++) {
-+ struct ssb_serial_port *port = &(mcore->serial_ports[i]);
-+ struct uart_port s;
-+
-+ memset(&s, 0, sizeof(s));
-+ s.line = i;
-+ s.membase = port->regs;
-+ s.irq = port->irq + 2;//FIXME?
-+ s.uartclk = port->baud_base;
-+ s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
-+ s.iotype = SERIAL_IO_MEM;
-+ s.regshift = port->reg_shift;
-+
-+ early_serial_setup(&s);
-+ }
-+ cfe_printk("Serial init done.\n");
-+
-+ _machine_restart = bcm47xx_machine_restart;
-+ _machine_halt = bcm47xx_machine_halt;
-+ pm_power_off = bcm47xx_machine_halt;
-+
-+ board_time_init = bcm47xx_time_init;//FIXME move into ssb
-+}
-+
-diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
---- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/bcm947xx/time.c 2007-01-26 16:26:48.000000000 +0100
-@@ -0,0 +1,62 @@
-+/*
-+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ *
-+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
-+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
-+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
-+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
-+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ *
-+ * You should have received a copy of the GNU General Public License along
-+ * with this program; if not, write to the Free Software Foundation, Inc.,
-+ * 675 Mass Ave, Cambridge, MA 02139, USA.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/sched.h>
-+#include <linux/serial_reg.h>
-+#include <linux/interrupt.h>
-+#include <linux/ssb/ssb.h>
-+#include <asm/addrspace.h>
-+#include <asm/io.h>
-+#include <asm/time.h>
-+
-+extern struct ssb_bus ssb;
-+
-+void __init
-+bcm47xx_time_init(void)
-+{
-+ unsigned long hz;
-+
-+ /*
-+ * Use deterministic values for initial counter interrupt
-+ * so that calibrate delay avoids encountering a counter wrap.
-+ */
-+ write_c0_count(0);
-+ write_c0_compare(0xffff);
-+
-+// hz = ssb_clockspeed(&ssb);
-+// if (!hz)
-+ hz = 100000000;
-+
-+ /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
-+ mips_hpt_frequency = hz;
-+}
-+
-+void __init
-+plat_timer_setup(struct irqaction *irq)
-+{
-+ /* Enable the timer interrupt */
-+ setup_irq(7, irq);
-+}
-diff -urN linux.old/arch/mips/cfe/cfe.c linux.dev/arch/mips/cfe/cfe.c
---- linux.old/arch/mips/cfe/cfe.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/cfe/cfe.c 2007-01-25 23:34:01.000000000 +0100
-@@ -0,0 +1,533 @@
-+/*
-+ * Broadcom Common Firmware Environment (CFE) support
-+ *
-+ * Copyright 2000, 2001, 2002
-+ * Broadcom Corporation. All rights reserved.
-+ *
-+ * Copyright (C) 2006 Michael Buesch
-+ *
-+ * Original Authors: Mitch Lichtenberg, Chris Demetriou
-+ *
-+ * This software is furnished under license and may be used and copied only
-+ * in accordance with the following terms and conditions. Subject to these
-+ * conditions, you may download, copy, install, use, modify and distribute
-+ * modified or unmodified copies of this software in source and/or binary
-+ * form. No title or ownership is transferred hereby.
-+ *
-+ * 1) Any source code used, modified or distributed must reproduce and
-+ * retain this copyright notice and list of conditions as they appear in
-+ * the source file.
-+ *
-+ * 2) No right is granted to use any trade name, trademark, or logo of
-+ * Broadcom Corporation. The "Broadcom Corporation" name may not be
-+ * used to endorse or promote products derived from this software
-+ * without the prior written permission of Broadcom Corporation.
-+ *
-+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
-+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
-+ * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
-+ * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-+ * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/string.h>
-+#include <linux/errno.h>
-+#include <linux/spinlock.h>
-+#include <asm/cfe.h>
-+
-+#include "cfe_private.h"
-+
-+
-+static cfe_uint_t cfe_handle;
-+static int (*cfe_trampoline)(long handle, long iocb);
-+
-+
-+#include <linux/kernel.h>
-+
-+void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
-+ unsigned long fwarg2, unsigned long fwarg3)
-+{
-+ if (fwarg3 == 0x80300000) {
-+ /* WRT54G workaround */
-+ fwarg3 = CFE_EPTSEAL;
-+ fwarg2 = 0xBFC00500;
-+ }
-+ if (fwarg3 != CFE_EPTSEAL) {
-+ /* We are not booted from CFE */
-+ return;
-+ }
-+ if (fwarg1 == 0) {
-+ /* We are on the boot CPU */
-+ cfe_handle = (cfe_uint_t)fwarg0;
-+ cfe_trampoline = CFE_TO_PTR(fwarg2);
-+ }
-+}
-+
-+int cfe_vprintk(const char *fmt, va_list args)
-+{
-+ static char buffer[1024];
-+ static DEFINE_SPINLOCK(lock);
-+ static const char pfx[] = "CFE-console: ";
-+ static const size_t pfx_len = sizeof(pfx) - 1;
-+ unsigned long flags;
-+ int len, cnt, pos;
-+ int handle;
-+ int res;
-+
-+ if (!cfe_present())
-+ return -ENODEV;
-+
-+ spin_lock_irqsave(&lock, flags);
-+ handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
-+ if (CFE_ISERR(handle)) {
-+ len = -EIO;
-+ goto out;
-+ }
-+ strcpy(buffer, pfx);
-+ len = vscnprintf(buffer + pfx_len,
-+ sizeof(buffer) - pfx_len - 2,
-+ fmt, args);
-+ len += pfx_len;
-+ /* The CFE console requires CR-LF line-ends.
-+ * Add a CR, if we only terminate lines with a LF.
-+ * This does only fix CR-LF at the end of the string.
-+ * So for multiple lines, use multiple cfe_vprintk calls.
-+ */
-+ if (len > 1 &&
-+ buffer[len - 1] == '\n' && buffer[len - 2] != '\r') {
-+ buffer[len - 1] = '\r';
-+ buffer[len] = '\n';
-+ len += 1;
-+ }
-+ cnt = len;
-+ pos = 0;
-+ while (cnt > 0) {
-+ res = cfe_write(handle, buffer + pos, len - pos);
-+ if (CFE_ISERR(res)) {
-+ len = -EIO;
-+ goto out;
-+ }
-+ cnt -= res;
-+ pos += res;
-+ }
-+out:
-+ spin_unlock_irqrestore(&lock, flags);
-+
-+ return len;
-+}
-+
-+int cfe_printk(const char *fmt, ...)
-+{
-+ va_list args;
-+ int res;
-+
-+ va_start(args, fmt);
-+ res = cfe_vprintk(fmt, args);
-+ va_end(args);
-+
-+ return res;
-+}
-+
-+static int cfe_iocb_dispatch(struct cfe_iocb *iocb)
-+{
-+ if (!cfe_present())
-+ return CFE_ERR_UNSUPPORTED;
-+ return cfe_trampoline((long)cfe_handle, (long)iocb);
-+}
-+
-+int cfe_present(void)
-+{
-+ return (cfe_trampoline != NULL);
-+}
-+
-+int cfe_close(int handle)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_DEV_CLOSE;
-+ iocb.handle = handle;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+
-+ return (CFE_ISERR(err)) ? err : iocb.status;
-+}
-+
-+int cfe_cpu_start(int cpu, void (*fn)(void), long sp, long gp, long a1)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_FW_CPUCTL;
-+ iocb.psize = sizeof(struct cfe_iocb_cpuctl);
-+ iocb.cpuctl.number = cpu;
-+ iocb.cpuctl.command = CFE_CPU_CMD_START;
-+ iocb.cpuctl.gp = gp;
-+ iocb.cpuctl.sp = sp;
-+ iocb.cpuctl.a1 = a1;
-+ iocb.cpuctl.start_addr = (long)fn;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+
-+ return (CFE_ISERR(err)) ? err : iocb.status;
-+}
-+
-+int cfe_cpu_stop(int cpu)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_FW_CPUCTL;
-+ iocb.psize = sizeof(struct cfe_iocb_cpuctl);
-+ iocb.cpuctl.number = cpu;
-+ iocb.cpuctl.command = CFE_CPU_CMD_STOP;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+
-+ return (CFE_ISERR(err)) ? err : iocb.status;
-+}
-+
-+int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_ENV_ENUM;
-+ iocb.psize = sizeof(struct cfe_iocb_envbuf);
-+ iocb.envbuf.index = idx;
-+ iocb.envbuf.name = PTR_TO_CFE(name);
-+ iocb.envbuf.name_len = namelen;
-+ iocb.envbuf.val = PTR_TO_CFE(val);
-+ iocb.envbuf.val_len = vallen;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+
-+ return (CFE_ISERR(err)) ? err : iocb.status;
-+}
-+
-+int cfe_enumdev(int idx, char *name, int namelen)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+
-+ iocb.fcode = CFE_CMD_DEV_ENUM;
-+ iocb.psize = sizeof(struct cfe_iocb_envbuf);
-+ iocb.envbuf.index = idx;
-+ iocb.envbuf.name = PTR_TO_CFE(name);
-+ iocb.envbuf.name_len = namelen;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+
-+ return (CFE_ISERR(err)) ? err : iocb.status;
-+}
-+
-+int cfe_enummem(int idx, int flags, u64 *start, u64 *length,
-+ u64 *type)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+
-+ iocb.fcode = CFE_CMD_FW_MEMENUM;
-+ iocb.flags = flags;
-+ iocb.psize = sizeof(struct cfe_iocb_meminfo);
-+ iocb.meminfo.index = idx;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+ if (CFE_ISERR(err))
-+ return err;
-+ if (!CFE_ISERR(iocb.status)) {
-+ *start = iocb.meminfo.addr;
-+ *length = iocb.meminfo.size;
-+ *type = iocb.meminfo.type;
-+ }
-+
-+ return iocb.status;
-+}
-+
-+int cfe_exit(int warm, int status)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+printk("CFE REBOOT\n");
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_FW_RESTART;
-+ if (warm)
-+ iocb.flags = CFE_FLG_WARMSTART;
-+ iocb.psize = sizeof(struct cfe_iocb_exitstat);
-+ iocb.exitstat.status = status;
-+
-+printk("CALL\n");
-+ err = cfe_iocb_dispatch(&iocb);
-+printk("DONE\n");
-+
-+ return (CFE_ISERR(err)) ? err : iocb.status;
-+}
-+
-+int cfe_flushcache(int flags)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_FW_FLUSHCACHE;
-+ iocb.flags = flags;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+
-+ return (CFE_ISERR(err)) ? err : iocb.status;
-+}
-+
-+int cfe_getdevinfo(char *name)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_DEV_GETINFO;
-+ iocb.psize = sizeof(struct cfe_iocb_buf);
-+ iocb.buffer.ptr = PTR_TO_CFE(name);
-+ iocb.buffer.length = strlen(name);
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+ if (CFE_ISERR(err))
-+ return err;
-+ if (CFE_ISERR(iocb.status))
-+ return iocb.status;
-+
-+ return iocb.buffer.devflags;
-+}
-+
-+int cfe_getenv(char *name, char *dest, int destlen)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ dest[0] = '\0';
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_ENV_GET;
-+ iocb.psize = sizeof(struct cfe_iocb_envbuf);
-+ iocb.envbuf.name = PTR_TO_CFE(name);
-+ iocb.envbuf.name_len = strlen(name);
-+ iocb.envbuf.val = PTR_TO_CFE(dest);
-+ iocb.envbuf.val_len = destlen;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+
-+ return (CFE_ISERR(err)) ? err : iocb.status;
-+}
-+
-+int cfe_getfwinfo(struct cfe_fwinfo *info)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_FW_GETINFO;
-+ iocb.psize = sizeof(struct cfe_iocb_fwinfo);
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+ if (CFE_ISERR(err))
-+ return err;
-+ if (CFE_ISERR(iocb.status))
-+ return err;
-+
-+ info->version = iocb.fwinfo.version;
-+ info->totalmem = iocb.fwinfo.totalmem;
-+ info->flags = iocb.fwinfo.flags;
-+ info->boardid = iocb.fwinfo.boardid;
-+ info->bootarea_va = iocb.fwinfo.bootarea_va;
-+ info->bootarea_pa = iocb.fwinfo.bootarea_pa;
-+ info->bootarea_size = iocb.fwinfo.bootarea_size;
-+
-+ return iocb.status;
-+}
-+
-+int cfe_getstdhandle(int handletype)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_DEV_GETHANDLE;
-+ iocb.flags = handletype;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+ if (CFE_ISERR(err))
-+ return err;
-+ if (CFE_ISERR(iocb.status))
-+ return iocb.status;
-+
-+ return iocb.handle;
-+}
-+
-+int cfe_getticks(s64 *ticks)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_FW_GETTIME;
-+ iocb.psize = sizeof(struct cfe_iocb_time);
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+ if (CFE_ISERR(err))
-+ return err;
-+ if (!CFE_ISERR(iocb.status))
-+ *ticks = iocb.time.ticks;
-+
-+ return iocb.status;
-+}
-+
-+int cfe_inpstat(int handle)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_DEV_INPSTAT;
-+ iocb.handle = handle;
-+ iocb.psize = sizeof(struct cfe_iocb_inpstat);
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+ if (CFE_ISERR(err))
-+ return err;
-+ if (CFE_ISERR(iocb.status))
-+ return iocb.status;
-+
-+ return iocb.inpstat.status;
-+}
-+
-+int cfe_ioctl(int handle, unsigned int ioctlnum,
-+ unsigned char *buffer, int length,
-+ int *retlen, u64 offset)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_DEV_IOCTL;
-+ iocb.handle = handle;
-+ iocb.psize = sizeof(struct cfe_iocb_buf);
-+ iocb.buffer.offset = offset;
-+ iocb.buffer.ioctlcmd = ioctlnum;
-+ iocb.buffer.ptr = PTR_TO_CFE(buffer);
-+ iocb.buffer.length = length;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+ if (CFE_ISERR(err))
-+ return err;
-+ if (CFE_ISERR(iocb.status))
-+ return iocb.status;
-+ if (retlen)
-+ *retlen = iocb.buffer.retlen;
-+
-+ return iocb.status;
-+}
-+
-+int cfe_open(char *name)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_DEV_OPEN;
-+ iocb.psize = sizeof(struct cfe_iocb_buf);
-+ iocb.buffer.ptr = PTR_TO_CFE(name);
-+ iocb.buffer.length = strlen(name);
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+ if (CFE_ISERR(err))
-+ return err;
-+ if (CFE_ISERR(iocb.status))
-+ return iocb.status;
-+
-+ return iocb.handle;
-+}
-+
-+int cfe_read(int handle, unsigned char *buffer, int length)
-+{
-+ return cfe_readblk(handle, 0, buffer, length);
-+}
-+
-+int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_DEV_READ;
-+ iocb.handle = handle;
-+ iocb.psize = sizeof(struct cfe_iocb_buf);
-+ iocb.buffer.offset = offset;
-+ iocb.buffer.ptr = PTR_TO_CFE(buffer);
-+ iocb.buffer.length = length;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+ if (CFE_ISERR(err))
-+ return err;
-+ if (CFE_ISERR(iocb.status))
-+ return iocb.status;
-+
-+ return iocb.buffer.retlen;
-+}
-+
-+int cfe_setenv(char *name, char *val)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_ENV_SET;
-+ iocb.psize = sizeof(struct cfe_iocb_envbuf);
-+ iocb.envbuf.name = PTR_TO_CFE(name);
-+ iocb.envbuf.name_len = strlen(name);
-+ iocb.envbuf.val = PTR_TO_CFE(val);
-+ iocb.envbuf.val_len = strlen(val);
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+
-+ return (CFE_ISERR(err)) ? err : iocb.status;
-+}
-+
-+int cfe_write(int handle, unsigned char *buffer, int length)
-+{
-+ return cfe_writeblk(handle, 0, buffer, length);
-+}
-+
-+int cfe_writeblk(int handle, s64 offset, unsigned char *buffer, int length)
-+{
-+ struct cfe_iocb iocb;
-+ int err;
-+
-+ memset(&iocb, 0, sizeof(iocb));
-+ iocb.fcode = CFE_CMD_DEV_WRITE;
-+ iocb.handle = handle;
-+ iocb.psize = sizeof(struct cfe_iocb_buf);
-+ iocb.buffer.offset = offset;
-+ iocb.buffer.ptr = PTR_TO_CFE(buffer);
-+ iocb.buffer.length = length;
-+
-+ err = cfe_iocb_dispatch(&iocb);
-+ if (CFE_ISERR(err))
-+ return err;
-+ if (CFE_ISERR(iocb.status))
-+ return iocb.status;
-+
-+ return iocb.buffer.retlen;
-+}
-diff -urN linux.old/arch/mips/cfe/cfe_private.h linux.dev/arch/mips/cfe/cfe_private.h
---- linux.old/arch/mips/cfe/cfe_private.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/cfe/cfe_private.h 2007-01-25 23:34:01.000000000 +0100
-@@ -0,0 +1,176 @@
-+/*
-+ * Broadcom Common Firmware Environment (CFE) support
-+ *
-+ * Copyright 2000, 2001, 2002
-+ * Broadcom Corporation. All rights reserved.
-+ *
-+ * Copyright (C) 2006 Michael Buesch
-+ *
-+ * Original Authors: Mitch Lichtenberg, Chris Demetriou
-+ *
-+ * This software is furnished under license and may be used and copied only
-+ * in accordance with the following terms and conditions. Subject to these
-+ * conditions, you may download, copy, install, use, modify and distribute
-+ * modified or unmodified copies of this software in source and/or binary
-+ * form. No title or ownership is transferred hereby.
-+ *
-+ * 1) Any source code used, modified or distributed must reproduce and
-+ * retain this copyright notice and list of conditions as they appear in
-+ * the source file.
-+ *
-+ * 2) No right is granted to use any trade name, trademark, or logo of
-+ * Broadcom Corporation. The "Broadcom Corporation" name may not be
-+ * used to endorse or promote products derived from this software
-+ * without the prior written permission of Broadcom Corporation.
-+ *
-+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
-+ * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
-+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
-+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
-+ * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
-+ * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-+ * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-+ */
-+
-+#ifndef LINUX_CFE_PRIVATE_H_
-+#define LINUX_CFE_PRIVATE_H_
-+
-+#ifndef __ASSEMBLY__
-+
-+/* Seal indicating CFE's presence, passed to the kernel. */
-+#define CFE_EPTSEAL 0x43464531
-+
-+#define CFE_CMD_FW_GETINFO 0
-+#define CFE_CMD_FW_RESTART 1
-+#define CFE_CMD_FW_BOOT 2
-+#define CFE_CMD_FW_CPUCTL 3
-+#define CFE_CMD_FW_GETTIME 4
-+#define CFE_CMD_FW_MEMENUM 5
-+#define CFE_CMD_FW_FLUSHCACHE 6
-+
-+#define CFE_CMD_DEV_GETHANDLE 9
-+#define CFE_CMD_DEV_ENUM 10
-+#define CFE_CMD_DEV_OPEN 11
-+#define CFE_CMD_DEV_INPSTAT 12
-+#define CFE_CMD_DEV_READ 13
-+#define CFE_CMD_DEV_WRITE 14
-+#define CFE_CMD_DEV_IOCTL 15
-+#define CFE_CMD_DEV_CLOSE 16
-+#define CFE_CMD_DEV_GETINFO 17
-+
-+#define CFE_CMD_ENV_ENUM 20
-+#define CFE_CMD_ENV_GET 22
-+#define CFE_CMD_ENV_SET 23
-+#define CFE_CMD_ENV_DEL 24
-+
-+#define CFE_CMD_MAX 32
-+
-+#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */
-+
-+typedef u64 cfe_uint_t;
-+typedef s64 cfe_int_t;
-+typedef s64 cfe_ptr_t;
-+
-+/* Cast a pointer from native to CFE-API pointer and back */
-+#define CFE_TO_PTR(p) ((void *)(unsigned long)(p))
-+#define PTR_TO_CFE(p) ((cfe_ptr_t)(unsigned long)(p))
-+
-+struct cfe_iocb_buf {
-+ cfe_uint_t offset; /* offset on device (bytes) */
-+ cfe_ptr_t ptr; /* pointer to a buffer */
-+ cfe_uint_t length; /* length of this buffer */
-+ cfe_uint_t retlen; /* returned length (for read ops) */
-+ union {
-+ cfe_uint_t ioctlcmd; /* IOCTL command (used only for IOCTLs) */
-+ cfe_uint_t devflags; /* Returned device info flags */
-+ };
-+};
-+
-+struct cfe_iocb_inpstat {
-+ cfe_uint_t status; /* 1 means input available */
-+};
-+
-+struct cfe_iocb_envbuf {
-+ cfe_int_t index; /* 0-based enumeration index */
-+ cfe_ptr_t name; /* name string buffer */
-+ cfe_int_t name_len; /* size of name buffer */
-+ cfe_ptr_t val; /* value string buffer */
-+ cfe_int_t val_len; /* size of value string buffer */
-+};
-+
-+struct cfe_iocb_cpuctl {
-+ cfe_uint_t number; /* cpu number to control */
-+ cfe_uint_t command; /* command to issue to CPU */
-+ cfe_uint_t start_addr; /* CPU start address */
-+ cfe_uint_t gp; /* starting GP value */
-+ cfe_uint_t sp; /* starting SP value */
-+ cfe_uint_t a1; /* starting A1 value */
-+};
-+
-+struct cfe_iocb_time {
-+ cfe_int_t ticks; /* current time in ticks */
-+};
-+
-+struct cfe_iocb_exitstat {
-+ cfe_int_t status;
-+};
-+
-+struct cfe_iocb_meminfo {
-+ cfe_int_t index; /* 0-based enumeration index */
-+ cfe_int_t type; /* type of memory block */
-+ cfe_uint_t addr; /* physical start address */
-+ cfe_uint_t size; /* block size */
-+};
-+
-+struct cfe_iocb_fwinfo {
-+ cfe_int_t version; /* major, minor, eco version */
-+ cfe_int_t totalmem; /* total installed mem */
-+ cfe_int_t flags; /* various flags */
-+ cfe_int_t boardid; /* board ID */
-+ cfe_int_t bootarea_va; /* VA of boot area */
-+ cfe_int_t bootarea_pa; /* PA of boot area */
-+ cfe_int_t bootarea_size; /* size of boot area */
-+ cfe_int_t reserved1;
-+ cfe_int_t reserved2;
-+ cfe_int_t reserved3;
-+};
-+
-+/* CFE I/O Control Block */
-+struct cfe_iocb {
-+ cfe_uint_t fcode; /* IOCB function code */
-+ cfe_int_t status; /* return status */
-+ cfe_int_t handle; /* file/device handle */
-+ cfe_uint_t flags; /* flags for this IOCB */
-+ cfe_uint_t psize; /* size of parameter list */
-+ union {
-+ struct cfe_iocb_buf buffer; /* buffer parameters */
-+ struct cfe_iocb_inpstat inpstat; /* input status parameters */
-+ struct cfe_iocb_envbuf envbuf; /* environment function parameters */
-+ struct cfe_iocb_cpuctl cpuctl; /* CPU control parameters */
-+ struct cfe_iocb_time time; /* timer parameters */
-+ struct cfe_iocb_meminfo meminfo; /* memory arena info parameters */
-+ struct cfe_iocb_fwinfo fwinfo; /* firmware information */
-+ struct cfe_iocb_exitstat exitstat; /* Exit Status */
-+ };
-+};
-+
-+
-+#include <linux/init.h>
-+
-+void __init cfe_setup(unsigned long fwarg0, unsigned long fwarg1,
-+ unsigned long fwarg2, unsigned long fwarg3);
-+
-+#else /* __ASSEMBLY__ */
-+
-+ .macro cfe_early_init
-+#ifdef CONFIG_CFE
-+ jal cfe_setup
-+#endif
-+ .endm
-+
-+#endif /* __ASSEMBLY__ */
-+#endif /* LINUX_CFE_PRIVATE_H_ */
-diff -urN linux.old/arch/mips/cfe/Makefile linux.dev/arch/mips/cfe/Makefile
---- linux.old/arch/mips/cfe/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/arch/mips/cfe/Makefile 2007-01-25 23:34:01.000000000 +0100
-@@ -0,0 +1,5 @@
-+#
-+# Makefile for the Broadcom Common Firmware Environment support
-+#
-+
-+obj-y += cfe.o
-diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
---- linux.old/arch/mips/Kconfig 2007-01-26 00:51:33.000000000 +0100
-+++ linux.dev/arch/mips/Kconfig 2007-01-26 00:51:18.000000000 +0100
-@@ -4,6 +4,10 @@
- # Horrible source of confusion. Die, die, die ...
- select EMBEDDED
-
-+config CFE
-+ bool
-+ # Common Firmware Environment
-+
- mainmenu "Linux/MIPS Kernel Configuration"
-
- menu "Machine selection"
-@@ -222,6 +226,24 @@
- Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
- Olivetti M700-10 workstations.
-
-+config BCM947XX
-+ bool "Support for BCM947xx based boards"
-+ select DMA_NONCOHERENT
-+ select HW_HAS_PCI
-+ select IRQ_CPU
-+ select SYS_HAS_CPU_MIPS32_R1
-+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select SYS_SUPPORTS_LITTLE_ENDIAN
-+ select SSB
-+ select SSB_SERIAL
-+ select SSB_DRIVER_PCICORE
-+ select SSB_PCICORE_HOSTMODE
-+ select SSB_DRIVER_MIPS
-+ select SSB_DRIVER_EXTIF
-+ select CFE
-+ help
-+ Support for BCM947xx based boards
-+
- config LASAT
- bool "LASAT Networks platforms"
- select DMA_NONCOHERENT
-diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
---- linux.old/arch/mips/kernel/cpu-probe.c 2007-01-26 00:51:33.000000000 +0100
-+++ linux.dev/arch/mips/kernel/cpu-probe.c 2007-01-25 23:34:01.000000000 +0100
-@@ -723,6 +723,28 @@
- }
-
-
-+static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
-+{
-+ decode_config1(c);
-+ switch (c->processor_id & 0xff00) {
-+ case PRID_IMP_BCM3302:
-+ c->cputype = CPU_BCM3302;
-+ c->isa_level = MIPS_CPU_ISA_M32R1;
-+ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-+ MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
-+ break;
-+ case PRID_IMP_BCM4710:
-+ c->cputype = CPU_BCM4710;
-+ c->isa_level = MIPS_CPU_ISA_M32R1;
-+ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
-+ MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
-+ break;
-+ default:
-+ c->cputype = CPU_UNKNOWN;
-+ break;
-+ }
-+}
-+
- __init void cpu_probe(void)
- {
- struct cpuinfo_mips *c = ¤t_cpu_data;
-@@ -745,6 +767,9 @@
- case PRID_COMP_SIBYTE:
- cpu_probe_sibyte(c);
- break;
-+ case PRID_COMP_BROADCOM:
-+ cpu_probe_broadcom(c);
-+ break;
- case PRID_COMP_SANDCRAFT:
- cpu_probe_sandcraft(c);
- break;
-diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
---- linux.old/arch/mips/kernel/proc.c 2007-01-26 00:51:33.000000000 +0100
-+++ linux.dev/arch/mips/kernel/proc.c 2007-01-25 23:34:01.000000000 +0100
-@@ -83,6 +83,8 @@
- [CPU_VR4181] = "NEC VR4181",
- [CPU_VR4181A] = "NEC VR4181A",
- [CPU_SR71000] = "Sandcraft SR71000",
-+ [CPU_BCM3302] = "Broadcom BCM3302",
-+ [CPU_BCM4710] = "Broadcom BCM4710",
- [CPU_PR4450] = "Philips PR4450",
- };
-
-diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
---- linux.old/arch/mips/Makefile 2007-01-26 00:51:33.000000000 +0100
-+++ linux.dev/arch/mips/Makefile 2007-01-25 23:34:01.000000000 +0100
-@@ -571,6 +571,18 @@
- load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
-
- #
-+# Broadcom BCM47XX boards
-+#
-+core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/
-+cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include -Iinclude/asm-mips/mach-bcm947xx
-+load-$(CONFIG_BCM947XX) := 0xffffffff80001000
-+
-+#
-+# Common Firmware Environment
-+#
-+core-$(CONFIG_CFE) += arch/mips/cfe/
-+
-+#
- # SNI RM200 PCI
- #
- core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
-diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
---- linux.old/arch/mips/mm/tlbex.c 2007-01-26 00:51:33.000000000 +0100
-+++ linux.dev/arch/mips/mm/tlbex.c 2007-01-25 23:34:01.000000000 +0100
-@@ -880,6 +880,8 @@
- case CPU_4KSC:
- case CPU_20KC:
- case CPU_25KF:
-+ case CPU_BCM3302:
-+ case CPU_BCM4710:
- tlbw(p);
- break;
-
-diff -urN linux.old/drivers/Kconfig linux.dev/drivers/Kconfig
---- linux.old/drivers/Kconfig 2007-01-26 00:51:33.000000000 +0100
-+++ linux.dev/drivers/Kconfig 2007-01-25 23:34:01.000000000 +0100
-@@ -56,6 +56,8 @@
-
- source "drivers/hwmon/Kconfig"
-
-+source "drivers/ssb/Kconfig"
-+
- source "drivers/mfd/Kconfig"
-
- source "drivers/media/Kconfig"
-diff -urN linux.old/drivers/Makefile linux.dev/drivers/Makefile
---- linux.old/drivers/Makefile 2007-01-26 00:51:33.000000000 +0100
-+++ linux.dev/drivers/Makefile 2007-01-25 23:34:01.000000000 +0100
-@@ -77,3 +77,4 @@
- obj-$(CONFIG_SUPERH) += sh/
- obj-$(CONFIG_GENERIC_TIME) += clocksource/
- obj-$(CONFIG_DMA_ENGINE) += dma/
-+obj-$(CONFIG_SSB) += ssb/
-diff -urN linux.old/drivers/ssb/core.c linux.dev/drivers/ssb/core.c
---- linux.old/drivers/ssb/core.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/ssb/core.c 2007-01-26 00:44:13.000000000 +0100
-@@ -0,0 +1,805 @@
-+/*
-+ * Sonics Silicon Backplane
-+ * Subsystem core
-+ *
-+ * Copyright 2005, Broadcom Corporation
-+ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include "ssb_private.h"
-+
-+#include <linux/delay.h>
-+#include <linux/ssb/ssb.h>
-+#include <linux/ssb/ssb_regs.h>
-+
-+#ifdef CONFIG_SSB_PCIHOST
-+# include <linux/pci.h>
-+#endif
-+
-+#ifdef CONFIG_SSB_PCMCIAHOST
-+# include <pcmcia/cs_types.h>
-+# include <pcmcia/cs.h>
-+# include <pcmcia/cistpl.h>
-+# include <pcmcia/ds.h>
-+#endif
-+
-+
-+MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
-+MODULE_LICENSE("GPL");
-+
-+
-+static LIST_HEAD(attach_queue);
-+static LIST_HEAD(buses);
-+static int nr_buses;
-+static DEFINE_MUTEX(buses_mutex);
-+
-+#define ssb_buses_lock() do { \
-+ if (!is_early_boot()) \
-+ mutex_lock(&buses_mutex); \
-+ } while (0)
-+
-+#define ssb_buses_unlock() do { \
-+ if (!is_early_boot()) \
-+ mutex_unlock(&buses_mutex); \
-+ } while (0)
-+
-+
-+static struct ssb_device * ssb_device_get(struct ssb_device *dev)
-+{
-+ if (dev)
-+ get_device(&dev->dev);
-+ return dev;
-+}
-+
-+static void ssb_device_put(struct ssb_device *dev)
-+{
-+ if (dev)
-+ put_device(&dev->dev);
-+}
-+
-+static void ssb_bus_resume(struct ssb_bus *bus)
-+{
-+printk("SSB BUS RESUME\n");
-+ ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
-+ ssb_chipco_resume(&bus->chipco);
-+}
-+
-+static int ssb_device_resume(struct device *dev)
-+{
-+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-+ struct ssb_driver *ssb_drv;
-+ struct ssb_bus *bus;
-+ int err = 0;
-+
-+printk("SSB DEV RESUME\n");
-+ bus = ssb_dev->bus;
-+ if (bus->suspend_cnt == bus->nr_devices)
-+ ssb_bus_resume(bus);
-+ bus->suspend_cnt--;
-+ if (dev->driver) {
-+ ssb_drv = drv_to_ssb_drv(dev->driver);
-+ if (ssb_drv && ssb_drv->resume)
-+ err = ssb_drv->resume(ssb_dev);
-+ if (err)
-+ goto out;
-+ }
-+out:
-+ return err;
-+}
-+
-+static void ssb_bus_suspend(struct ssb_bus *bus, pm_message_t state)
-+{
-+printk("SSB BUS SUSPEND\n");
-+// ssb_chipco_suspend(&bus->chipco, state);
-+// ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
-+}
-+
-+static int ssb_device_suspend(struct device *dev, pm_message_t state)
-+{
-+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-+ struct ssb_driver *ssb_drv;
-+ struct ssb_bus *bus;
-+ int err = 0;
-+
-+printk("SSB DEV SUSPEND\n");
-+ if (dev->driver) {
-+ ssb_drv = drv_to_ssb_drv(dev->driver);
-+ if (ssb_drv && ssb_drv->suspend)
-+ err = ssb_drv->suspend(ssb_dev, state);
-+ if (err)
-+ goto out;
-+ }
-+
-+ bus = ssb_dev->bus;
-+ bus->suspend_cnt++;
-+ if (bus->suspend_cnt == bus->nr_devices) {
-+ /* All devices suspended. Shutdown the bus. */
-+ ssb_bus_suspend(bus, state);
-+ }
-+
-+out:
-+ return err;
-+}
-+
-+static void ssb_device_shutdown(struct device *dev)
-+{
-+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-+ struct ssb_driver *ssb_drv;
-+
-+ if (!dev->driver)
-+ return;
-+ ssb_drv = drv_to_ssb_drv(dev->driver);
-+ if (ssb_drv && ssb_drv->shutdown)
-+ ssb_drv->shutdown(ssb_dev);
-+}
-+
-+static int ssb_device_remove(struct device *dev)
-+{
-+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-+ struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
-+
-+ if (ssb_drv && ssb_drv->remove)
-+ ssb_drv->remove(ssb_dev);
-+ ssb_device_put(ssb_dev);
-+
-+ return 0;
-+}
-+
-+static int ssb_device_probe(struct device *dev)
-+{
-+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-+ struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
-+ int err = 0;
-+
-+ ssb_device_get(ssb_dev);
-+ if (ssb_drv && ssb_drv->probe)
-+ err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
-+ if (err)
-+ ssb_device_put(ssb_dev);
-+
-+ return err;
-+}
-+
-+static int ssb_match_devid(const struct ssb_device_id *tabid,
-+ const struct ssb_device_id *devid)
-+{
-+ if ((tabid->vendor != devid->vendor) &&
-+ tabid->vendor != SSB_ANY_VENDOR)
-+ return 0;
-+ if ((tabid->coreid != devid->coreid) &&
-+ tabid->coreid != SSB_ANY_ID)
-+ return 0;
-+ if ((tabid->revision != devid->revision) &&
-+ tabid->revision != SSB_ANY_REV)
-+ return 0;
-+ return 1;
-+}
-+
-+static int ssb_bus_match(struct device *dev, struct device_driver *drv)
-+{
-+ struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
-+ struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
-+ const struct ssb_device_id *id;
-+
-+ for (id = ssb_drv->id_table;
-+ id->vendor || id->coreid || id->revision;
-+ id++) {
-+ if (ssb_match_devid(id, &ssb_dev->id))
-+ return 1; /* found */
-+ }
-+
-+ return 0;
-+}
-+
-+struct bus_type ssb_bustype = {
-+ .name = NULL, /* Intentionally NULL to indicate early boot */
-+ .match = ssb_bus_match,
-+ .probe = ssb_device_probe,
-+ .remove = ssb_device_remove,
-+ .shutdown = ssb_device_shutdown,
-+ .suspend = ssb_device_suspend,
-+ .resume = ssb_device_resume,
-+};
-+
-+#define is_early_boot() (ssb_bustype.name == NULL)
-+
-+void ssb_bus_unregister(struct ssb_bus *bus)
-+{
-+ struct ssb_device *dev;
-+ int i;
-+
-+ ssb_buses_lock();
-+ for (i = bus->nr_devices - 1; i >= 0; i--) {
-+ dev = &(bus->devices[i]);
-+ device_unregister(&dev->dev);
-+ }
-+ list_del(&bus->list);
-+ ssb_buses_unlock();
-+
-+ ssb_iounmap(bus);
-+}
-+EXPORT_SYMBOL(ssb_bus_unregister);
-+
-+static void ssb_release_dev(struct device *dev)
-+{
-+ /* Nothing, devices are allocated together with struct ssb_bus. */
-+}
-+
-+/* Needs ssb_buses_lock() */
-+static int ssb_attach_queued_buses(void)
-+{
-+ struct ssb_bus *bus, *n;
-+ struct ssb_device *dev;
-+ int i, err;
-+
-+ list_for_each_entry_safe(bus, n, &attach_queue, list) {
-+ for (i = 0; i < bus->nr_devices; i++) {
-+ dev = &(bus->devices[i]);
-+
-+ dev->dev.release = ssb_release_dev;
-+ err = device_register(&dev->dev);
-+ if (err) {
-+ ssb_printk(KERN_ERR PFX
-+ "Could not register %s\n",
-+ dev->dev.bus_id);
-+ }
-+ }
-+ list_move_tail(&bus->list, &buses);
-+ }
-+ return 0;
-+}
-+
-+static void ssb_get_boardtype(struct ssb_bus *bus)
-+{//FIXME for pcmcia?
-+ if (bus->bustype != SSB_BUSTYPE_PCI) {
-+ /* Must set board_vendor, board_type and board_rev
-+ * before calling ssb_bus_*_register() */
-+ assert(bus->board_vendor && bus->board_type);
-+ return;
-+ }
-+ ssb_pci_get_boardtype(bus);
-+}
-+
-+static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ offset += dev->core_index * SSB_CORE_SIZE;
-+ return readw(bus->mmio + offset);
-+}
-+
-+static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ offset += dev->core_index * SSB_CORE_SIZE;
-+ return readl(bus->mmio + offset);
-+}
-+
-+static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ offset += dev->core_index * SSB_CORE_SIZE;
-+ writew(value, bus->mmio + offset);
-+}
-+
-+static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ offset += dev->core_index * SSB_CORE_SIZE;
-+ writel(value, bus->mmio + offset);
-+}
-+
-+static const struct ssb_bus_ops ssb_ssb_ops = {
-+ .read16 = ssb_ssb_read16,
-+ .read32 = ssb_ssb_read32,
-+ .write16 = ssb_ssb_write16,
-+ .write32 = ssb_ssb_write32,
-+};
-+
-+static int ssb_bus_register(struct ssb_bus *bus,
-+ unsigned long baseaddr)
-+{
-+ int err;
-+
-+ ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on ");
-+ switch (bus->bustype) {
-+ case SSB_BUSTYPE_SSB:
-+ ssb_printk("address 0x%08lX\n", baseaddr);
-+ break;
-+ case SSB_BUSTYPE_PCI:
-+#ifdef CONFIG_SSB_PCIHOST
-+ ssb_printk("PCI device %s\n", bus->host_pci->dev.bus_id);
-+#endif
-+ break;
-+ case SSB_BUSTYPE_PCMCIA:
-+#ifdef CONFIG_SSB_PCMCIAHOST
-+ ssb_printk("PCMCIA device %s\n", bus->host_pcmcia->devname);
-+#endif
-+ break;
-+ }
-+
-+ spin_lock_init(&bus->bar_lock);
-+ INIT_LIST_HEAD(&bus->list);
-+
-+ ssb_get_boardtype(bus);
-+ /* Powerup the bus */
-+ err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
-+ if (err)
-+ goto out;
-+ ssb_buses_lock();
-+ bus->busnumber = nr_buses;
-+ /* Scan for devices (cores) */
-+ err = ssb_bus_scan(bus, baseaddr);
-+ if (err)
-+ goto err_disable_xtal;
-+
-+ /* Init PCI-host device (if any) */
-+ err = ssb_pci_init(bus);
-+ if (err)
-+ goto err_unmap;
-+ /* Init PCMCIA-host device (if any) */
-+ err = ssb_pcmcia_init(bus);
-+ if (err)
-+ goto err_unmap;
-+
-+ /* Initialize basic system devices (if available) */
-+ ssb_chipcommon_init(&bus->chipco);
-+ ssb_mipscore_init(&bus->mipscore);
-+ ssb_pcicore_init(&bus->pcicore);
-+
-+ /* Queue it for attach */
-+ list_add_tail(&bus->list, &attach_queue);
-+ if (!is_early_boot()) {
-+ /* This is not early boot, so we must attach the bus now */
-+ err = ssb_attach_queued_buses();
-+ if (err)
-+ goto err_dequeue;
-+ }
-+ nr_buses++;
-+ ssb_buses_unlock();
-+
-+out:
-+ return err;
-+
-+err_dequeue:
-+ list_del(&bus->list);
-+err_unmap:
-+ ssb_iounmap(bus);
-+err_disable_xtal:
-+ ssb_buses_unlock();
-+ ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
-+ goto out;
-+}
-+
-+#ifdef CONFIG_SSB_PCIHOST
-+int ssb_bus_pcibus_register(struct ssb_bus *bus,
-+ struct pci_dev *host_pci)
-+{
-+ int err;
-+
-+ bus->bustype = SSB_BUSTYPE_PCI;
-+ bus->host_pci = host_pci;
-+ bus->ops = &ssb_pci_ops;
-+
-+ err = ssb_bus_register(bus, 0);
-+
-+ return err;
-+}
-+EXPORT_SYMBOL(ssb_bus_pcibus_register);
-+#endif /* CONFIG_SSB_PCIHOST */
-+
-+#ifdef CONFIG_SSB_PCMCIAHOST
-+int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
-+ struct pcmcia_device *pcmcia_dev,
-+ unsigned long baseaddr,
-+ void (*fill_sprom)(struct ssb_sprom *sprom))
-+{
-+ int err;
-+
-+ bus->bustype = SSB_BUSTYPE_PCMCIA;
-+ bus->host_pcmcia = pcmcia_dev;
-+ bus->ops = &ssb_pcmcia_ops;
-+ fill_sprom(&bus->sprom);
-+
-+ err = ssb_bus_register(bus, baseaddr);
-+
-+ return err;
-+}
-+EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
-+#endif /* CONFIG_SSB_PCMCIAHOST */
-+
-+int ssb_bus_ssbbus_register(struct ssb_bus *bus,
-+ unsigned long baseaddr,
-+ void (*fill_sprom)(struct ssb_sprom *sprom))
-+{
-+ int err;
-+
-+ bus->bustype = SSB_BUSTYPE_SSB;
-+ bus->ops = &ssb_ssb_ops;
-+ fill_sprom(&bus->sprom);
-+ err = ssb_bus_register(bus, baseaddr);
-+
-+ return err;
-+}
-+
-+int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
-+{
-+ drv->drv.name = drv->name;
-+ drv->drv.bus = &ssb_bustype;
-+ drv->drv.owner = owner;
-+
-+ return driver_register(&drv->drv);
-+}
-+EXPORT_SYMBOL(__ssb_driver_register);
-+
-+void ssb_driver_unregister(struct ssb_driver *drv)
-+{
-+ driver_unregister(&drv->drv);
-+}
-+EXPORT_SYMBOL(ssb_driver_unregister);
-+
-+void ssb_set_devtypedata(struct ssb_device *dev, void *data)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+ struct ssb_device *ent;
-+ int i;
-+
-+ for (i = 0; i < bus->nr_devices; i++) {
-+ ent = &(bus->devices[i]);
-+ if (ent->id.vendor != dev->id.vendor)
-+ continue;
-+ if (ent->id.coreid != dev->id.coreid)
-+ continue;
-+
-+ ent->devtypedata = data;
-+ }
-+}
-+EXPORT_SYMBOL(ssb_set_devtypedata);
-+
-+static u32 clkfactor_f6_resolve(u32 v)
-+{
-+ /* map the magic values */
-+ switch (v) {
-+ case SSB_CHIPCO_CLK_F6_2:
-+ return 2;
-+ case SSB_CHIPCO_CLK_F6_3:
-+ return 3;
-+ case SSB_CHIPCO_CLK_F6_4:
-+ return 4;
-+ case SSB_CHIPCO_CLK_F6_5:
-+ return 5;
-+ case SSB_CHIPCO_CLK_F6_6:
-+ return 6;
-+ case SSB_CHIPCO_CLK_F6_7:
-+ return 7;
-+ }
-+ return 0;
-+}
-+
-+/* Calculate the speed the backplane would run at a given set of clockcontrol values */
-+u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
-+{
-+ u32 n1, n2, clock, m1, m2, m3, mc;
-+
-+ n1 = (n & SSB_CHIPCO_CLK_N1);
-+ n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
-+
-+ switch (plltype) {
-+ case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
-+ if (m & SSB_CHIPCO_CLK_T6_MMASK)
-+ return SSB_CHIPCO_CLK_T6_M0;
-+ return SSB_CHIPCO_CLK_T6_M1;
-+ case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
-+ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
-+ case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
-+ case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
-+ n1 = clkfactor_f6_resolve(n1);
-+ n2 += SSB_CHIPCO_CLK_F5_BIAS;
-+ break;
-+ case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
-+ n1 += SSB_CHIPCO_CLK_T2_BIAS;
-+ n2 += SSB_CHIPCO_CLK_T2_BIAS;
-+ assert((n1 >= 2) && (n1 <= 7));
-+ assert((n2 >= 5) && (n2 <= 23));
-+ break;
-+ case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
-+ return 100000000;
-+ default:
-+ assert(0);
-+ }
-+
-+ switch (plltype) {
-+ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
-+ case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
-+ clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
-+ break;
-+ default:
-+ clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
-+ }
-+ if (!clock)
-+ return 0;
-+
-+ m1 = (m & SSB_CHIPCO_CLK_M1);
-+ m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
-+ m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
-+ mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
-+
-+ switch (plltype) {
-+ case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
-+ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
-+ case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
-+ case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
-+ m1 = clkfactor_f6_resolve(m1);
-+ if ((plltype == SSB_PLLTYPE_1) ||
-+ (plltype == SSB_PLLTYPE_3))
-+ m2 += SSB_CHIPCO_CLK_F5_BIAS;
-+ else
-+ m2 = clkfactor_f6_resolve(m2);
-+ m3 = clkfactor_f6_resolve(m3);
-+
-+ switch (mc) {
-+ case SSB_CHIPCO_CLK_MC_BYPASS:
-+ return clock;
-+ case SSB_CHIPCO_CLK_MC_M1:
-+ return (clock / m1);
-+ case SSB_CHIPCO_CLK_MC_M1M2:
-+ return (clock / (m1 * m2));
-+ case SSB_CHIPCO_CLK_MC_M1M2M3:
-+ return (clock / (m1 * m2 * m3));
-+ case SSB_CHIPCO_CLK_MC_M1M3:
-+ return (clock / (m1 * m3));
-+ }
-+ return 0;
-+ case SSB_PLLTYPE_2:
-+ m1 += SSB_CHIPCO_CLK_T2_BIAS;
-+ m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
-+ m3 += SSB_CHIPCO_CLK_T2_BIAS;
-+ assert((m1 >= 2) && (m1 <= 7));
-+ assert((m2 >= 3) && (m2 <= 10));
-+ assert((m3 >= 2) && (m3 <= 7));
-+
-+ if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
-+ clock /= m1;
-+ if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
-+ clock /= m2;
-+ if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
-+ clock /= m3;
-+ return clock;
-+ default:
-+ assert(0);
-+ }
-+ return 0;
-+}
-+
-+/* Get the current speed the backplane is running at */
-+u32 ssb_clockspeed(struct ssb_bus *bus)
-+{
-+ u32 rate;
-+ u32 plltype;
-+ u32 clkctl_n, clkctl_m;
-+
-+ //TODO if EXTIF: PLLTYPE == 1, read n from clockcontrol_n, m from clockcontrol_sb
-+
-+ if (bus->chipco.dev) {
-+ ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
-+ &clkctl_n, &clkctl_m);
-+ } else
-+ return 0;
-+
-+ if (bus->chip_id == 0x5365) {
-+ rate = 100000000;
-+ } else {
-+ rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
-+ if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
-+ rate /= 2;
-+ }
-+
-+ return rate;
-+}
-+EXPORT_SYMBOL(ssb_clockspeed);
-+
-+int ssb_device_is_enabled(struct ssb_device *dev)
-+{
-+ u32 val;
-+
-+ val = ssb_read32(dev, SSB_TMSLOW);
-+ val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT;
-+
-+ return (val == SSB_TMSLOW_CLOCK);
-+}
-+EXPORT_SYMBOL(ssb_device_is_enabled);
-+
-+void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
-+{
-+ u32 val;
-+
-+ ssb_device_disable(dev, core_specific_flags);
-+ ssb_write32(dev, SSB_TMSLOW,
-+ SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
-+ SSB_TMSLOW_FGC | core_specific_flags);
-+ /* flush */
-+ ssb_read32(dev, SSB_TMSLOW);
-+ udelay(1);
-+
-+ /* Clear SERR if set. This is a hw bug workaround. */
-+ if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
-+ ssb_write32(dev, SSB_TMSHIGH, 0);
-+
-+ val = ssb_read32(dev, SSB_IMSTATE);
-+ if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
-+ val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
-+ ssb_write32(dev, SSB_IMSTATE, val);
-+ }
-+
-+ ssb_write32(dev, SSB_TMSLOW,
-+ SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
-+ core_specific_flags);
-+ /* flush */
-+ ssb_read32(dev, SSB_TMSLOW);
-+ udelay(1);
-+
-+ ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
-+ core_specific_flags);
-+ /* flush */
-+ ssb_read32(dev, SSB_TMSLOW);
-+ udelay(1);
-+}
-+EXPORT_SYMBOL(ssb_device_enable);
-+
-+static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
-+ int timeout, int set)
-+{
-+ int i;
-+ u32 val;
-+
-+ for (i = 0; i < timeout; i++) {
-+ val = ssb_read32(dev, reg);
-+ if (set) {
-+ if (val & bitmask)
-+ return 0;
-+ } else {
-+ if (!(val & bitmask))
-+ return 0;
-+ }
-+ udelay(10);
-+ }
-+ printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
-+ "register %04X to %s.\n",
-+ bitmask, reg, (set ? "set" : "clear"));
-+
-+ return -ETIMEDOUT;
-+}
-+
-+void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
-+{
-+ if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
-+ return;
-+
-+ ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT | SSB_TMSLOW_CLOCK);
-+ ssb_wait_bit(dev, SSB_TMSLOW, SSB_TMSLOW_REJECT, 1000, 1);
-+ ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
-+ ssb_write32(dev, SSB_TMSLOW,
-+ SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
-+ SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
-+ core_specific_flags);
-+ /* flush */
-+ ssb_read32(dev, SSB_TMSLOW);
-+ udelay(1);
-+
-+ ssb_write32(dev, SSB_TMSLOW,
-+ SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET |
-+ core_specific_flags);
-+ /* flush */
-+ ssb_read32(dev, SSB_TMSLOW);
-+ udelay(1);
-+}
-+EXPORT_SYMBOL(ssb_device_disable);
-+
-+u32 ssb_dma_translation(struct ssb_device *dev)
-+{
-+ switch(dev->bus->bustype) {
-+ case SSB_BUSTYPE_SSB:
-+ return 0;
-+ case SSB_BUSTYPE_PCI:
-+ case SSB_BUSTYPE_PCMCIA:
-+ return SSB_PCI_DMA;
-+ }
-+ return 0;
-+}
-+EXPORT_SYMBOL(ssb_dma_translation);
-+
-+int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask)
-+{
-+ struct device *dev = &ssb_dev->dev;
-+
-+#ifdef CONFIG_SSB_PCIHOST
-+ if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI &&
-+ !dma_supported(dev, mask))
-+ return -EIO;
-+#endif
-+ dev->coherent_dma_mask = mask;
-+ dev->dma_mask = &dev->coherent_dma_mask;
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(ssb_dma_set_mask);
-+
-+u32 ssb_admatch_base(u32 adm)
-+{
-+ u32 base = 0;
-+
-+ switch (adm & SSB_ADM_TYPE) {
-+ case SSB_ADM_TYPE0:
-+ base = (adm & SSB_ADM_BASE0);
-+ break;
-+ case SSB_ADM_TYPE1:
-+ assert(!(adm & SSB_ADM_NEG)); /* unsupported */
-+ base = (adm & SSB_ADM_BASE1);
-+ break;
-+ case SSB_ADM_TYPE2:
-+ assert(!(adm & SSB_ADM_NEG)); /* unsupported */
-+ base = (adm & SSB_ADM_BASE2);
-+ break;
-+ default:
-+ assert(0);
-+ }
-+
-+ return base;
-+}
-+EXPORT_SYMBOL(ssb_admatch_base);
-+
-+u32 ssb_admatch_size(u32 adm)
-+{
-+ u32 size = 0;
-+
-+ switch (adm & SSB_ADM_TYPE) {
-+ case SSB_ADM_TYPE0:
-+ size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
-+ break;
-+ case SSB_ADM_TYPE1:
-+ assert(!(adm & SSB_ADM_NEG)); /* unsupported */
-+ size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
-+ break;
-+ case SSB_ADM_TYPE2:
-+ assert(!(adm & SSB_ADM_NEG)); /* unsupported */
-+ size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
-+ break;
-+ default:
-+ assert(0);
-+ }
-+ size = (1 << (size + 1));
-+
-+ return size;
-+}
-+EXPORT_SYMBOL(ssb_admatch_size);
-+
-+static int __init ssb_modinit(void)
-+{
-+ int err;
-+
-+ ssb_bustype.name = "ssb";
-+ err = bus_register(&ssb_bustype);
-+ if (err)
-+ return err;
-+
-+ /* Maybe we already registered some buses at early boot.
-+ * Check for this and attach them
-+ */
-+ ssb_buses_lock();
-+ err = ssb_attach_queued_buses();
-+ ssb_buses_unlock();
-+
-+ return err;
-+}
-+subsys_initcall(ssb_modinit);
-+
-+static void __exit ssb_modexit(void)
-+{
-+ bus_unregister(&ssb_bustype);
-+}
-+module_exit(ssb_modexit)
-diff -urN linux.old/drivers/ssb/driver_chipcommon/chipcommon.c linux.dev/drivers/ssb/driver_chipcommon/chipcommon.c
---- linux.old/drivers/ssb/driver_chipcommon/chipcommon.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/ssb/driver_chipcommon/chipcommon.c 2007-01-26 00:44:13.000000000 +0100
-@@ -0,0 +1,403 @@
-+/*
-+ * Sonics Silicon Backplane
-+ * Broadcom ChipCommon core driver
-+ *
-+ * Copyright 2005, Broadcom Corporation
-+ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include <linux/ssb/ssb.h>
-+#include <linux/ssb/ssb_regs.h>
-+#include <linux/pci.h>
-+
-+#include "../ssb_private.h"
-+
-+
-+/* Clock sources */
-+enum {
-+ /* PCI clock */
-+ SSB_CHIPCO_CLKSRC_PCI,
-+ /* Crystal slow clock oscillator */
-+ SSB_CHIPCO_CLKSRC_XTALOS,
-+ /* Low power oscillator */
-+ SSB_CHIPCO_CLKSRC_LOPWROS,
-+};
-+
-+
-+static inline u32 chipco_read32(struct ssb_chipcommon *cc,
-+ u16 offset)
-+{
-+ return ssb_read32(cc->dev, offset);
-+}
-+
-+static inline void chipco_write32(struct ssb_chipcommon *cc,
-+ u16 offset,
-+ u32 value)
-+{
-+ ssb_write32(cc->dev, offset, value);
-+}
-+
-+void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
-+ enum ssb_clkmode mode)
-+{
-+ struct ssb_device *ccdev = cc->dev;
-+ struct ssb_bus *bus;
-+ u32 tmp;
-+
-+ if (!ccdev)
-+ return;
-+ bus = ccdev->bus;
-+ /* chipcommon cores prior to rev6 don't support dynamic clock control */
-+ if (ccdev->id.revision < 6)
-+ return;
-+ /* chipcommon cores rev10 are a whole new ball game */
-+ if (ccdev->id.revision >= 10)
-+ return;
-+ if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
-+ return;
-+
-+ switch (mode) {
-+ case SSB_CLKMODE_SLOW:
-+ tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-+ tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
-+ chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
-+ break;
-+ case SSB_CLKMODE_FAST:
-+ ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
-+ tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-+ tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
-+ tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
-+ chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
-+ break;
-+ case SSB_CLKMODE_DYNAMIC:
-+ tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-+ tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
-+ tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
-+ tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
-+ if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
-+ tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
-+ chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
-+
-+ /* for dynamic control, we have to release our xtal_pu "force on" */
-+ if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
-+ ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
-+ break;
-+ default:
-+ assert(0);
-+ }
-+}
-+EXPORT_SYMBOL(ssb_chipco_set_clockmode);
-+
-+/* Get the Slow Clock Source */
-+static int chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
-+{
-+ struct ssb_bus *bus = cc->dev->bus;
-+ u32 tmp = 0;
-+
-+ if (cc->dev->id.revision < 6) {
-+ if (bus->bustype == SSB_BUSTYPE_SSB /*TODO ||
-+ bus->bustype == SSB_BUSTYPE_PCMCIA*/)
-+ return SSB_CHIPCO_CLKSRC_XTALOS;
-+ if (bus->bustype == SSB_BUSTYPE_PCI) {
-+ pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
-+ if (tmp & 0x10)
-+ return SSB_CHIPCO_CLKSRC_PCI;
-+ return SSB_CHIPCO_CLKSRC_XTALOS;
-+ }
-+ }
-+ if (cc->dev->id.revision < 10) {
-+ tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-+ tmp &= 0x7;
-+ if (tmp == 0)
-+ return SSB_CHIPCO_CLKSRC_LOPWROS;
-+ if (tmp == 1)
-+ return SSB_CHIPCO_CLKSRC_XTALOS;
-+ if (tmp == 2)
-+ return SSB_CHIPCO_CLKSRC_PCI;
-+ }
-+
-+ return SSB_CHIPCO_CLKSRC_XTALOS;
-+}
-+
-+/* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
-+static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
-+{
-+ int limit;
-+ int clocksrc;
-+ int divisor;
-+ u32 tmp;
-+
-+ clocksrc = chipco_pctl_get_slowclksrc(cc);
-+ if (cc->dev->id.revision < 6) {
-+ switch (clocksrc) {
-+ case SSB_CHIPCO_CLKSRC_PCI:
-+ divisor = 64;
-+ break;
-+ case SSB_CHIPCO_CLKSRC_XTALOS:
-+ divisor = 32;
-+ break;
-+ default:
-+ assert(0);
-+ divisor = 1;
-+ }
-+ } else if (cc->dev->id.revision < 10) {
-+ switch (clocksrc) {
-+ case SSB_CHIPCO_CLKSRC_LOPWROS:
-+ divisor = 1;
-+ break;
-+ case SSB_CHIPCO_CLKSRC_XTALOS:
-+ case SSB_CHIPCO_CLKSRC_PCI:
-+ tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
-+ divisor = (tmp >> 16) + 1;
-+ divisor *= 4;
-+ break;
-+ default:
-+ assert(0);
-+ divisor = 1;
-+ }
-+ } else {
-+ tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
-+ divisor = (tmp >> 16) + 1;
-+ divisor *= 4;
-+ }
-+
-+ switch (clocksrc) {
-+ case SSB_CHIPCO_CLKSRC_LOPWROS:
-+ if (get_max)
-+ limit = 43000;
-+ else
-+ limit = 25000;
-+ break;
-+ case SSB_CHIPCO_CLKSRC_XTALOS:
-+ if (get_max)
-+ limit = 20200000;
-+ else
-+ limit = 19800000;
-+ break;
-+ case SSB_CHIPCO_CLKSRC_PCI:
-+ if (get_max)
-+ limit = 34000000;
-+ else
-+ limit = 25000000;
-+ break;
-+ default:
-+ assert(0);
-+ limit = 0;
-+ }
-+ limit /= divisor;
-+
-+ return limit;
-+}
-+
-+static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
-+{
-+ struct ssb_bus *bus = cc->dev->bus;
-+
-+ if (bus->chip_id == 0x4321) {
-+ if (bus->chip_rev == 0)
-+ chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
-+ else if (bus->chip_rev == 1)
-+ chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
-+ }
-+
-+ if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
-+ return;
-+
-+ if (cc->dev->id.revision >= 10) {
-+ /* Set Idle Power clock rate to 1Mhz */
-+ chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
-+ (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
-+ 0x0000FFFF) | 0x00040000);
-+ } else {
-+ int maxfreq;
-+
-+ maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
-+ chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
-+ (maxfreq * 150 + 999999) / 1000000);
-+ chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
-+ (maxfreq * 15 + 999999) / 1000000);
-+ }
-+}
-+
-+static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
-+{
-+ struct ssb_bus *bus = cc->dev->bus;
-+ int minfreq;
-+ unsigned int tmp;
-+ u32 pll_on_delay;
-+
-+ if (bus->bustype != SSB_BUSTYPE_PCI)
-+ return;
-+ if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
-+ return;
-+
-+ minfreq = chipco_pctl_clockfreqlimit(cc, 0);
-+ pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
-+ tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
-+ assert((tmp & ~0xFFFF) == 0);
-+
-+ cc->fast_pwrup_delay = tmp;
-+}
-+
-+void ssb_chipcommon_init(struct ssb_chipcommon *cc)
-+{
-+ if (!cc->dev)
-+ return; /* We don't have a ChipCommon */
-+ ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
-+ chipco_powercontrol_init(cc);
-+ calc_fast_powerup_delay(cc);
-+}
-+
-+void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state)
-+{
-+ if (!cc->dev)
-+ return;
-+ ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
-+}
-+
-+void ssb_chipco_resume(struct ssb_chipcommon *cc)
-+{
-+ if (!cc->dev)
-+ return;
-+ ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
-+ chipco_powercontrol_init(cc);
-+}
-+
-+void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
-+ u32 *plltype, u32 *n, u32 *m)
-+{
-+ *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
-+ *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
-+ switch (*plltype) {
-+ case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
-+ *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
-+ break;
-+ case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
-+ if (cc->dev->bus->chip_id != 0x5365) {
-+ *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
-+ break;
-+ }
-+ /* Fallthough */
-+ default:
-+ *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
-+ }
-+}
-+
-+void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
-+ unsigned long ns)
-+{
-+ struct ssb_device *dev = cc->dev;
-+ struct ssb_bus *bus = dev->bus;
-+ u32 tmp;
-+
-+ /* set register for external IO to control LED. */
-+ chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
-+ tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
-+ tmp |= ceildiv(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */
-+ tmp |= ceildiv(240, ns); /* Waitcount-0 = 240ns */
-+ chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
-+
-+ /* Set timing for the flash */
-+ tmp = ceildiv(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */
-+ tmp |= ceildiv(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */
-+ tmp |= ceildiv(120, ns); /* Waitcount-0 = 120nS */
-+ if ((bus->chip_id == 0x5365) ||
-+ (dev->id.revision < 9))
-+ chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
-+ if ((bus->chip_id == 0x5365) ||
-+ (dev->id.revision < 9) ||
-+ ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
-+ chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
-+
-+ if (bus->chip_id == 0x5350) {
-+ /* Enable EXTIF */
-+ tmp = ceildiv(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
-+ tmp |= ceildiv(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */
-+ tmp |= ceildiv(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
-+ tmp |= ceildiv(120, ns); /* Waitcount-0 = 120ns */
-+ chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
-+ }
-+}
-+
-+
-+#ifdef CONFIG_SSB_SERIAL
-+int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
-+ struct ssb_serial_port *ports)
-+{
-+ struct ssb_bus *bus = cc->dev->bus;
-+ int nr_ports = 0;
-+ u32 plltype;
-+ unsigned int irq;
-+ u32 baud_base, div;
-+ u32 i, n;
-+
-+ plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
-+ irq = ssb_mips_irq(cc->dev);
-+
-+ if (plltype == SSB_PLLTYPE_1) {
-+ /* PLL clock */
-+ baud_base = ssb_calc_clock_rate(plltype,
-+ chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
-+ chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
-+ div = 1;
-+ } else {
-+ if (cc->dev->id.revision >= 11) {
-+ /* Fixed ALP clock */
-+ baud_base = 20000000;
-+ div = 1;
-+ /* Set the override bit so we don't divide it */
-+ chipco_write32(cc, SSB_CHIPCO_CORECTL,
-+ SSB_CHIPCO_CORECTL_UARTCLK0);
-+ } else if (cc->dev->id.revision >= 3) {
-+ /* Internal backplane clock */
-+ baud_base = ssb_clockspeed(bus);
-+ div = 2; /* Minimum divisor */
-+ chipco_write32(cc, SSB_CHIPCO_CLKDIV,
-+ (chipco_read32(cc, SSB_CHIPCO_CLKDIV)
-+ & ~SSB_CHIPCO_CLKDIV_UART) | div);
-+ } else {
-+ /* Fixed internal backplane clock */
-+ baud_base = 88000000;
-+ div = 48;
-+ }
-+
-+ /* Clock source depends on strapping if UartClkOverride is unset */
-+ if ((cc->dev->id.revision > 0) &&
-+ !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
-+ if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
-+ SSB_CHIPCO_CAP_UARTCLK_INT) {
-+ /* Internal divided backplane clock */
-+ baud_base /= div;
-+ } else {
-+ /* Assume external clock of 1.8432 MHz */
-+ baud_base = 1843200;
-+ }
-+ }
-+ }
-+
-+ /* Determine the registers of the UARTs */
-+ n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
-+ for (i = 0; i < n; i++) {
-+ void __iomem *cc_mmio;
-+ void __iomem *uart_regs;
-+
-+ cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
-+ uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
-+ /* Offset changed at after rev 0 */
-+ if (cc->dev->id.revision == 0)
-+ uart_regs += (i * 8);
-+ else
-+ uart_regs += (i * 256);
-+
-+ nr_ports++;
-+ ports[i].regs = uart_regs;
-+ ports[i].irq = irq;
-+ ports[i].baud_base = baud_base;
-+ ports[i].reg_shift = 0;
-+ }
-+
-+ return nr_ports;
-+}
-+#endif /* CONFIG_SSB_SERIAL */
-diff -urN linux.old/drivers/ssb/driver_mips/mips.c linux.dev/drivers/ssb/driver_mips/mips.c
---- linux.old/drivers/ssb/driver_mips/mips.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/ssb/driver_mips/mips.c 2007-01-26 00:44:13.000000000 +0100
-@@ -0,0 +1,258 @@
-+/*
-+ * Sonics Silicon Backplane
-+ * Broadcom MIPS core driver
-+ *
-+ * Copyright 2005, Broadcom Corporation
-+ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include <linux/ssb/ssb.h>
-+
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
-+#include <linux/serial_reg.h>
-+#include <asm/time.h>
-+
-+#include "../ssb_private.h"
-+
-+
-+static inline u32 mips_read32(struct ssb_mipscore *mcore,
-+ u16 offset)
-+{
-+ return ssb_read32(mcore->dev, offset);
-+}
-+
-+static inline void mips_write32(struct ssb_mipscore *mcore,
-+ u16 offset,
-+ u32 value)
-+{
-+ ssb_write32(mcore->dev, offset, value);
-+}
-+
-+static const u32 ipsflag_irq_mask[] = {
-+ 0,
-+ SSB_IPSFLAG_IRQ1,
-+ SSB_IPSFLAG_IRQ2,
-+ SSB_IPSFLAG_IRQ3,
-+ SSB_IPSFLAG_IRQ4,
-+};
-+
-+static const u32 ipsflag_irq_shift[] = {
-+ 0,
-+ SSB_IPSFLAG_IRQ1_SHIFT,
-+ SSB_IPSFLAG_IRQ2_SHIFT,
-+ SSB_IPSFLAG_IRQ3_SHIFT,
-+ SSB_IPSFLAG_IRQ4_SHIFT,
-+};
-+
-+static inline u32 ssb_irqflag(struct ssb_device *dev)
-+{
-+ return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
-+}
-+
-+/* Get the MIPS IRQ assignment for a specified device.
-+ * If unassigned, 0 is returned.
-+ */
-+unsigned int ssb_mips_irq(struct ssb_device *dev)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+ u32 irqflag;
-+ u32 ipsflag;
-+ u32 tmp;
-+ unsigned int irq;
-+
-+ irqflag = ssb_irqflag(dev);
-+ ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
-+ for (irq = 1; irq <= 4; irq++) {
-+ tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
-+ if (tmp == irqflag)
-+ break;
-+ }
-+ if (irq == 5)
-+ irq = 0;
-+
-+ return irq;
-+}
-+
-+static void clear_irq(struct ssb_bus *bus, unsigned int irq)
-+{
-+ struct ssb_device *dev = bus->mipscore.dev;
-+
-+ /* Clear the IRQ in the MIPScore backplane registers */
-+ if (irq == 0) {
-+ ssb_write32(dev, SSB_INTVEC, 0);
-+ } else {
-+ ssb_write32(dev, SSB_IPSFLAG,
-+ ssb_read32(dev, SSB_IPSFLAG) |
-+ ipsflag_irq_mask[irq]);
-+ }
-+}
-+
-+static void set_irq(struct ssb_device *dev, unsigned int irq)
-+{
-+ unsigned int oldirq = ssb_mips_irq(dev);
-+ struct ssb_bus *bus = dev->bus;
-+ struct ssb_device *mdev = bus->mipscore.dev;
-+ u32 irqflag = ssb_irqflag(dev);
-+
-+ dev->irq = irq + 2;
-+
-+ ssb_dprintk(KERN_INFO PFX
-+ "set_irq: core 0x%04x, irq %d => %d\n",
-+ dev->id.coreid, oldirq, irq);
-+ /* clear the old irq */
-+ if (oldirq == 0)
-+ ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
-+ else
-+ clear_irq(bus, oldirq);
-+
-+ /* assign the new one */
-+ if (irq == 0)
-+ ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
-+
-+ irqflag <<= ipsflag_irq_shift[irq];
-+ irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
-+ ssb_write32(mdev, SSB_IPSFLAG, irqflag);
-+}
-+
-+/* XXX: leave here or move into separate extif driver? */
-+static int ssb_extif_serial_init(struct ssb_device *dev, struct ssb_serial_ports *ports)
-+{
-+
-+}
-+
-+
-+static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
-+{
-+ struct ssb_bus *bus = mcore->dev->bus;
-+
-+ //TODO if (EXTIF available
-+#if 0
-+ extifregs_t *eir = (extifregs_t *) regs;
-+ sbconfig_t *sb;
-+
-+ /* Determine external UART register base */
-+ sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
-+ base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
-+
-+ /* Determine IRQ */
-+ irq = sb_irq(sbh);
-+
-+ /* Disable GPIO interrupt initially */
-+ W_REG(&eir->gpiointpolarity, 0);
-+ W_REG(&eir->gpiointmask, 0);
-+
-+ /* Search for external UARTs */
-+ n = 2;
-+ for (i = 0; i < 2; i++) {
-+ regs = (void *) REG_MAP(base + (i * 8), 8);
-+ if (BCMINIT(serial_exists)(regs)) {
-+ /* Set GPIO 1 to be the external UART IRQ */
-+ W_REG(&eir->gpiointmask, 2);
-+ if (add)
-+ add(regs, irq, 13500000, 0);
-+ }
-+ }
-+
-+ /* Add internal UART if enabled */
-+ if (R_REG(&eir->corecontrol) & CC_UE)
-+ if (add)
-+ add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
-+
-+#endif
-+ if (bus->extif.dev)
-+ mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
-+ else if (bus->chipco.dev)
-+ mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
-+ else
-+ mcore->nr_serial_ports = 0;
-+}
-+
-+static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
-+{
-+ struct ssb_bus *bus = mcore->dev->bus;
-+
-+ if (bus->chipco.dev) {
-+ mcore->flash_window = 0x1c000000;
-+ mcore->flash_window_size = 0x800000;
-+ } else {
-+ mcore->flash_window = 0x1fc00000;
-+ mcore->flash_window_size = 0x400000;
-+ }
-+}
-+
-+
-+static void ssb_cpu_clock(struct ssb_mipscore *mcore)
-+{
-+}
-+
-+void ssb_mipscore_init(struct ssb_mipscore *mcore)
-+{
-+ struct ssb_bus *bus = mcore->dev->bus;
-+ struct ssb_device *dev;
-+ unsigned long hz, ns;
-+ unsigned int irq, i;
-+
-+ if (!mcore->dev)
-+ return; /* We don't have a MIPS core */
-+
-+ ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
-+
-+ hz = ssb_clockspeed(bus);
-+ if (!hz)
-+ hz = 100000000;
-+ ns = 1000000000 / hz;
-+
-+//TODO
-+#if 0
-+ if (have EXTIF) {
-+ /* Initialize extif so we can get to the LEDs and external UART */
-+ W_REG(&eir->prog_config, CF_EN);
-+
-+ /* Set timing for the flash */
-+ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
-+ tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
-+ tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
-+ W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
-+
-+ /* Set programmable interface timing for external uart */
-+ tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
-+ tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
-+ tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
-+ tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
-+ W_REG(&eir->prog_waitcount, tmp);
-+ }
-+ else... chipcommon
-+#endif
-+ if (bus->chipco.dev)
-+ ssb_chipco_timing_init(&bus->chipco, ns);
-+
-+ /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
-+ for (irq = 2, i = 0; i < bus->nr_devices; i++) {
-+ dev = &(bus->devices[i]);
-+ dev->irq = ssb_mips_irq(dev) + 2;
-+ switch(dev->id.coreid) {
-+ case SSB_DEV_USB11_HOST:
-+ /* shouldn't need a separate irq line for non-4710, most of them have a proper
-+ * external usb controller on the pci */
-+ if ((bus->chip_id == 0x4710) && (irq <= 4)) {
-+ set_irq(dev, irq++);
-+ break;
-+ }
-+ case SSB_DEV_PCI:
-+ case SSB_DEV_ETHERNET:
-+ case SSB_DEV_80211:
-+ case SSB_DEV_USB20_HOST:
-+ /* These devices get their own IRQ line if available, the rest goes on IRQ0 */
-+ if (irq <= 4) {
-+ set_irq(dev, irq++);
-+ break;
-+ }
-+ }
-+ }
-+
-+ ssb_mips_serial_init(mcore);
-+ ssb_mips_flash_detect(mcore);
-+}
-diff -urN linux.old/drivers/ssb/driver_pci/pcicore.c linux.dev/drivers/ssb/driver_pci/pcicore.c
---- linux.old/drivers/ssb/driver_pci/pcicore.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/ssb/driver_pci/pcicore.c 2007-01-26 20:19:19.000000000 +0100
-@@ -0,0 +1,549 @@
-+/*
-+ * Sonics Silicon Backplane
-+ * Broadcom PCI-core driver
-+ *
-+ * Copyright 2005, Broadcom Corporation
-+ * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include <linux/ssb/ssb.h>
-+#include <linux/pci.h>
-+#include <linux/delay.h>
-+
-+#include "../ssb_private.h"
-+
-+static inline
-+u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
-+{
-+ return ssb_read32(pc->dev, offset);
-+}
-+
-+static inline
-+void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
-+{
-+ ssb_write32(pc->dev, offset, value);
-+}
-+
-+/**************************************************
-+ * Code for hostmode operation.
-+ **************************************************/
-+
-+#ifdef CONFIG_SSB_PCICORE_HOSTMODE
-+
-+#include <asm/paccess.h>
-+/* Read the bus and catch bus exceptions. This is MIPS specific. */
-+#define mips_busprobe(val, addr) get_dbe((val), (addr))
-+
-+/* Assume one-hot slot wiring */
-+#define SSB_PCI_SLOT_MAX 16
-+
-+/* Global lock is OK, as we won't have more than one extpci anyway. */
-+static DEFINE_SPINLOCK(cfgspace_lock);
-+/* Core to access the external PCI config space. Can only have one. */
-+static struct ssb_pcicore *extpci_core;
-+
-+u32 pci_iobase = 0x100;
-+u32 pci_membase = SSB_PCI_DMA;
-+
-+int pcibios_plat_dev_init(struct pci_dev *d)
-+{
-+ struct resource *res;
-+ int pos, size;
-+ u32 *base;
-+
-+ printk("PCI: Fixing up device %s\n", pci_name(d));
-+
-+ /* Fix up resource bases */
-+ for (pos = 0; pos < 6; pos++) {
-+ res = &d->resource[pos];
-+ base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
-+ if (res->end) {
-+ size = res->end - res->start + 1;
-+ if (*base & (size - 1))
-+ *base = (*base + size) & ~(size - 1);
-+ res->start = *base;
-+ res->end = res->start + size - 1;
-+ *base += size;
-+ pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
-+ }
-+ /* Fix up PCI bridge BAR0 only */
-+ if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
-+ break;
-+ }
-+ /* Fix up interrupt lines */
-+ d->irq = ssb_mips_irq(extpci_core->dev) + 2;
-+ pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
-+
-+ return 0;
-+}
-+
-+static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
-+{
-+ if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
-+ return;
-+
-+ printk("PCI: fixing up bridge\n");
-+
-+ /* Enable PCI bridge bus mastering and memory space */
-+ pci_set_master(dev);
-+ pcibios_enable_device(dev, ~0);
-+
-+ /* Enable PCI bridge BAR1 prefetch and burst */
-+ pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
-+}
-+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
-+
-+int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
-+{
-+ return ssb_mips_irq(extpci_core->dev) + 2;
-+}
-+
-+static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
-+ unsigned int bus, unsigned int dev,
-+ unsigned int func, unsigned int off)
-+{
-+ u32 addr = 0;
-+ u32 tmp;
-+
-+ if (unlikely(pc->cardbusmode && dev > 1))
-+ goto out;
-+ if (bus == 0) {//FIXME busnumber ok?
-+ /* Type 0 transaction */
-+ if (unlikely(dev >= SSB_PCI_SLOT_MAX))
-+ goto out;
-+ /* Slide the window */
-+ tmp = SSB_PCICORE_SBTOPCI_CFG0;
-+ tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
-+ pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
-+ /* Calculate the address */
-+ addr = SSB_PCI_CFG;
-+ addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
-+ addr |= (func << 8);
-+ addr |= (off & ~3);
-+ } else {
-+ /* Type 1 transaction */
-+ pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
-+ SSB_PCICORE_SBTOPCI_CFG1);
-+ /* Calculate the address */
-+ addr = SSB_PCI_CFG;
-+ addr |= (bus << 16);
-+ addr |= (dev << 11);
-+ addr |= (func << 8);
-+ addr |= (off & ~3);
-+ }
-+out:
-+ return addr;
-+}
-+
-+static int ssb_extpci_read_config(struct ssb_pcicore *pc,
-+ unsigned int bus, unsigned int dev,
-+ unsigned int func, unsigned int off,
-+ void *buf, int len)
-+{
-+ int err = -EINVAL;
-+ u32 addr, val;
-+ void __iomem *mmio;
-+
-+ assert(pc->hostmode);
-+ if (unlikely(len != 1 && len != 2 && len != 4))
-+ goto out;
-+ addr = get_cfgspace_addr(pc, bus, dev, func, off);
-+ if (unlikely(!addr))
-+ goto out;
-+ err = -ENOMEM;
-+ mmio = ioremap_nocache(addr, len);
-+ if (!mmio)
-+ goto out;
-+
-+ if (mips_busprobe(val, (u32 *) mmio)) {
-+ val = 0xffffffff;
-+ goto unmap;
-+ }
-+
-+ val = readl(mmio);
-+ val >>= (8 * (off & 3));
-+
-+ switch (len) {
-+ case 1:
-+ *((u8 *)buf) = (u8)val;
-+ break;
-+ case 2:
-+ *((u16 *)buf) = (u16)val;
-+ break;
-+ case 4:
-+ *((u32 *)buf) = (u32)val;
-+ break;
-+ }
-+ err = 0;
-+unmap:
-+ iounmap(mmio);
-+out:
-+ return err;
-+}
-+
-+static int ssb_extpci_write_config(struct ssb_pcicore *pc,
-+ unsigned int bus, unsigned int dev,
-+ unsigned int func, unsigned int off,
-+ const void *buf, int len)
-+{
-+ int err = -EINVAL;
-+ u32 addr, val = 0;
-+ void __iomem *mmio;
-+
-+ assert(pc->hostmode);
-+ if (unlikely(len != 1 && len != 2 && len != 4))
-+ goto out;
-+ addr = get_cfgspace_addr(pc, bus, dev, func, off);
-+ if (unlikely(!addr))
-+ goto out;
-+ err = -ENOMEM;
-+ mmio = ioremap_nocache(addr, len);
-+ if (!mmio)
-+ goto out;
-+
-+ if (mips_busprobe(val, (u32 *) mmio)) {
-+ val = 0xffffffff;
-+ goto unmap;
-+ }
-+
-+ switch (len) {
-+ case 1:
-+ val = readl(mmio);
-+ val &= ~(0xFF << (8 * (off & 3)));
-+ val |= *((const u8 *)buf) << (8 * (off & 3));
-+ break;
-+ case 2:
-+ val = readl(mmio);
-+ val &= ~(0xFFFF << (8 * (off & 3)));
-+ val |= *((const u16 *)buf) << (8 * (off & 3));
-+ break;
-+ case 4:
-+ val = *((const u32 *)buf);
-+ break;
-+ }
-+ writel(*((const u32 *)buf), mmio);
-+
-+ err = 0;
-+unmap:
-+ iounmap(mmio);
-+out:
-+ return err;
-+}
-+
-+static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
-+ int reg, int size, u32 *val)
-+{
-+ unsigned long flags;
-+ int err;
-+
-+ spin_lock_irqsave(&cfgspace_lock, flags);
-+ err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
-+ PCI_FUNC(devfn), reg, val, size);
-+ spin_unlock_irqrestore(&cfgspace_lock, flags);
-+
-+ return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
-+ int reg, int size, u32 val)
-+{
-+ unsigned long flags;
-+ int err;
-+
-+ spin_lock_irqsave(&cfgspace_lock, flags);
-+ err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
-+ PCI_FUNC(devfn), reg, &val, size);
-+ spin_unlock_irqrestore(&cfgspace_lock, flags);
-+
-+ return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
-+}
-+
-+static struct pci_ops ssb_pcicore_pciops = {
-+ .read = ssb_pcicore_read_config,
-+ .write = ssb_pcicore_write_config,
-+};
-+
-+static struct resource ssb_pcicore_mem_resource = {
-+ .name = "SSB PCIcore external memory",
-+ .start = SSB_PCI_DMA,
-+ .end = (u32)SSB_PCI_DMA + (u32)SSB_PCI_DMA_SZ - 1,
-+ .flags = IORESOURCE_MEM,
-+};
-+
-+static struct resource ssb_pcicore_io_resource = {
-+ .name = "SSB PCIcore external I/O",
-+ .start = 0x100,
-+ .end = 0x7FF,
-+ .flags = IORESOURCE_IO,
-+};
-+
-+static struct pci_controller ssb_pcicore_controller = {
-+ .pci_ops = &ssb_pcicore_pciops,
-+ .io_resource = &ssb_pcicore_io_resource,
-+ .mem_resource = &ssb_pcicore_mem_resource,
-+ .mem_offset = 0x24000000,
-+};
-+
-+static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
-+{
-+ u32 val;
-+
-+ assert(!extpci_core);
-+ extpci_core = pc;
-+
-+ ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
-+ /* Reset devices on the external PCI bus */
-+ val = SSB_PCICORE_CTL_RST_OE;
-+ val |= SSB_PCICORE_CTL_CLK_OE;
-+ pcicore_write32(pc, SSB_PCICORE_CTL, val);
-+ val |= SSB_PCICORE_CTL_CLK; /* Clock on */
-+ pcicore_write32(pc, SSB_PCICORE_CTL, val);
-+ udelay(150);
-+ val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
-+ pcicore_write32(pc, SSB_PCICORE_CTL, val);
-+ udelay(1);
-+
-+ //TODO cardbus mode
-+
-+ /* 64MB I/O window */
-+ pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
-+ SSB_PCICORE_SBTOPCI_IO);
-+ /* 64MB config space */
-+ pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
-+ SSB_PCICORE_SBTOPCI_CFG0);
-+ /* 1GB memory window */
-+ pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
-+ SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
-+
-+ /* Enable PCI bridge BAR0 prefetch and burst */
-+ val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-+ ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 4);
-+
-+ /* Enable PCI interrupts */
-+ pcicore_write32(pc, SSB_PCICORE_IMASK,
-+ SSB_PCICORE_IMASK_INTA);
-+
-+ /* Ok, ready to run, register it to the system.
-+ * The following needs change, if we want to port hostmode
-+ * to non-MIPS platform. */
-+ set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
-+ register_pci_controller(&ssb_pcicore_controller);
-+}
-+
-+static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
-+{
-+ struct ssb_bus *bus = pc->dev->bus;
-+ u16 chipid_top;
-+ u32 tmp;
-+
-+ chipid_top = (bus->chip_id & 0xFF00);
-+ if (chipid_top != 0x4700 &&
-+ chipid_top != 0x5300)
-+ return 0;
-+
-+ if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
-+ return 0;
-+
-+ /* The 200-pin BCM4712 package does not bond out PCI. Even when
-+ * PCI is bonded out, some boards may leave the pins floating. */
-+ if (bus->chip_id == 0x4712) {
-+ if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
-+ return 0;
-+ if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
-+ return 0;
-+ }
-+ if (bus->chip_id == 0x5350)
-+ return 0;
-+
-+ return !mips_busprobe(tmp, (u32 *) (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
-+}
-+#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
-+
-+
-+/**************************************************
-+ * Generic and Clientmode operation code.
-+ **************************************************/
-+
-+static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
-+{
-+ /* Disable PCI interrupts. */
-+ ssb_write32(pc->dev, SSB_INTVEC, 0);
-+}
-+
-+void ssb_pcicore_init(struct ssb_pcicore *pc)
-+{
-+ struct ssb_device *dev = pc->dev;
-+ struct ssb_bus *bus;
-+
-+ if (!dev)
-+ return;
-+ bus = dev->bus;
-+ if (!ssb_device_is_enabled(dev))
-+ ssb_device_enable(dev, 0);
-+
-+#ifdef CONFIG_SSB_PCICORE_HOSTMODE
-+ pc->hostmode = pcicore_is_in_hostmode(pc);
-+ if (pc->hostmode)
-+ ssb_pcicore_init_hostmode(pc);
-+#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
-+ if (!pc->hostmode)
-+ ssb_pcicore_init_clientmode(pc);
-+}
-+
-+static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
-+{
-+ pcicore_write32(pc, 0x130, address);
-+ return pcicore_read32(pc, 0x134);
-+}
-+
-+static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
-+{
-+ pcicore_write32(pc, 0x130, address);
-+ pcicore_write32(pc, 0x134, data);
-+}
-+
-+static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
-+ u8 address, u16 data)
-+{
-+ const u16 mdio_control = 0x128;
-+ const u16 mdio_data = 0x12C;
-+ u32 v;
-+ int i;
-+
-+ v = 0x80; /* Enable Preamble Sequence */
-+ v |= 0x2; /* MDIO Clock Divisor */
-+ pcicore_write32(pc, mdio_control, v);
-+
-+ v = (1 << 30); /* Start of Transaction */
-+ v |= (1 << 28); /* Write Transaction */
-+ v |= (1 << 17); /* Turnaround */
-+ v |= (u32)device << 22;
-+ v |= (u32)address << 18;
-+ v |= data;
-+ pcicore_write32(pc, mdio_data, v);
-+ udelay(10);
-+ for (i = 0; i < 10; i++) {
-+ v = pcicore_read32(pc, mdio_control);
-+ if (v & 0x100 /* Trans complete */)
-+ break;
-+ msleep(1);
-+ }
-+ pcicore_write32(pc, mdio_control, 0);
-+}
-+
-+static void ssb_broadcast_value(struct ssb_device *dev,
-+ u32 address, u32 data)
-+{
-+ /* This is used for both, PCI and ChipCommon core, so be careful. */
-+ BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
-+ BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
-+
-+ ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
-+ ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
-+ ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
-+ ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
-+}
-+
-+static void ssb_commit_settings(struct ssb_bus *bus)
-+{
-+ struct ssb_device *dev;
-+
-+ dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
-+ assert(dev);
-+ /* This forces an update of the cached registers. */
-+ ssb_broadcast_value(dev, 0xFD8, 0);
-+}
-+
-+int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
-+ struct ssb_device *dev)
-+{
-+ struct ssb_device *pdev = pc->dev;
-+ struct ssb_bus *bus;
-+ int err = 0;
-+ u32 tmp;
-+
-+ might_sleep();
-+
-+ if (!pdev)
-+ goto out;
-+ bus = pdev->bus;
-+
-+ /* Enable interrupts for this device. */
-+ if (bus->host_pci &&
-+ ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
-+ u32 coremask;
-+
-+ /* Calculate the "coremask" for the device. */
-+ coremask = (1 << dev->core_index);
-+
-+ err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
-+ if (err)
-+ goto out;
-+ tmp |= coremask << 8;
-+ err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
-+ if (err)
-+ goto out;
-+ } else {
-+ u32 intvec;
-+
-+ intvec = ssb_read32(pdev, SSB_INTVEC);
-+ tmp = ssb_read32(dev, SSB_TPSFLAG);
-+ tmp &= SSB_TPSFLAG_BPFLAG;
-+ intvec |= tmp;
-+ ssb_write32(pdev, SSB_INTVEC, intvec);
-+ }
-+
-+ /* Setup PCIcore operation. */
-+ if (pc->setup_done)
-+ goto out;
-+ if (pdev->id.coreid == SSB_DEV_PCI) {
-+ tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
-+ tmp |= SSB_PCICORE_SBTOPCI_PREF;
-+ tmp |= SSB_PCICORE_SBTOPCI_BURST;
-+ pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
-+
-+ if (pdev->id.revision < 5) {
-+ tmp = ssb_read32(pdev, SSB_IMCFGLO);
-+ tmp &= ~SSB_IMCFGLO_SERTO;
-+ tmp |= 2;
-+ tmp &= ~SSB_IMCFGLO_REQTO;
-+ tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
-+ ssb_write32(pdev, SSB_IMCFGLO, tmp);
-+ ssb_commit_settings(bus);
-+ } else if (pdev->id.revision >= 11) {
-+ tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
-+ tmp |= SSB_PCICORE_SBTOPCI_MRM;
-+ pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
-+ }
-+ } else {
-+ assert(pdev->id.coreid == SSB_DEV_PCIE);
-+ //TODO: Better make defines for all these magic PCIE values.
-+ if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
-+ /* TLP Workaround register. */
-+ tmp = ssb_pcie_read(pc, 0x4);
-+ tmp |= 0x8;
-+ ssb_pcie_write(pc, 0x4, tmp);
-+ }
-+ if (pdev->id.revision == 0) {
-+ const u8 serdes_rx_device = 0x1F;
-+
-+ ssb_pcie_mdio_write(pc, serdes_rx_device,
-+ 2 /* Timer */, 0x8128);
-+ ssb_pcie_mdio_write(pc, serdes_rx_device,
-+ 6 /* CDR */, 0x0100);
-+ ssb_pcie_mdio_write(pc, serdes_rx_device,
-+ 7 /* CDR BW */, 0x1466);
-+ } else if (pdev->id.revision == 1) {
-+ /* DLLP Link Control register. */
-+ tmp = ssb_pcie_read(pc, 0x100);
-+ tmp |= 0x40;
-+ ssb_pcie_write(pc, 0x100, tmp);
-+ }
-+ }
-+ pc->setup_done = 1;
-+out:
-+ return err;
-+}
-+EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
-diff -urN linux.old/drivers/ssb/Kconfig linux.dev/drivers/ssb/Kconfig
---- linux.old/drivers/ssb/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/ssb/Kconfig 2007-01-26 00:44:13.000000000 +0100
-@@ -0,0 +1,93 @@
-+menu "Sonics Silicon Backplane"
-+
-+config SSB
-+ tristate "Sonics Silicon Backplane support"
-+ depends on EXPERIMENTAL
-+ help
-+ Support for the Sonics Silicon Backplane bus
-+
-+ The module will be called ssb
-+
-+ If unsure, say M
-+
-+config SSB_PCIHOST
-+ bool "Support for SSB on PCI-bus host"
-+ depends on SSB && PCI
-+ default y
-+ help
-+ Support for a Sonics Silicon Backplane on top
-+ of a PCI device.
-+
-+ If unsure, say Y
-+
-+config SSB_PCMCIAHOST
-+ bool "Support for SSB on PCMCIA-bus host"
-+ depends on SSB && PCMCIA
-+ help
-+ Support for a Sonics Silicon Backplane on top
-+ of a PCMCIA device.
-+
-+ If unsure, say N
-+
-+config SSB_SILENT
-+ bool "No SSB kernel messages"
-+ depends on SSB
-+ help
-+ This option turns off all Sonics Silicon Backplane printks.
-+ Note that you won't be able to identify problems, once
-+ messages are turned off.
-+ This might only be desired for production kernels on
-+ embedded devices to reduce the kernel size.
-+
-+ Say N
-+
-+config SSB_DEBUG
-+ bool "SSB debugging"
-+ depends on SSB && !SSB_SILENT
-+ help
-+ This turns on additional runtime checks and debugging
-+ messages. Turn this on for SSB troubleshooting.
-+
-+ If unsure, say N
-+
-+config SSB_SERIAL
-+ bool
-+ depends on SSB
-+ # ChipCommon and ExtIf serial support routines.
-+
-+config SSB_DRIVER_PCICORE
-+ bool "SSB PCI core driver"
-+ depends on SSB && SSB_PCIHOST
-+ default y
-+ help
-+ Driver for the Sonics Silicon Backplane attached
-+ Broadcom PCI core.
-+
-+ If unsure, say Y
-+
-+config SSB_PCICORE_HOSTMODE
-+ bool "Hostmode support for SSB PCI core"
-+ depends on SSB_DRIVER_PCICORE && SSB_DRIVER_MIPS
-+ help
-+ PCIcore hostmode operation (external PCI bus).
-+
-+config SSB_DRIVER_MIPS
-+ bool "SSB Broadcom MIPS core driver"
-+ depends on SSB && MIPS
-+ select SSB_SERIAL
-+ help
-+ Driver for the Sonics Silicon Backplane attached
-+ Broadcom MIPS core.
-+
-+ If unsure, say N
-+
-+config SSB_DRIVER_EXTIF
-+ bool "SSB Broadcom EXTIF core driver"
-+ depends on SSB_DRIVER_MIPS
-+ help
-+ Driver for the Sonics Silicon Backplane attached
-+ Broadcom EXTIF core.
-+
-+ If unsure, say N
-+
-+endmenu
-diff -urN linux.old/drivers/ssb/Makefile linux.dev/drivers/ssb/Makefile
---- linux.old/drivers/ssb/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/ssb/Makefile 2007-01-26 00:44:13.000000000 +0100
-@@ -0,0 +1,14 @@
-+ssb-driver-chipcommon-y := driver_chipcommon/chipcommon.o
-+ssb-driver-mips-$(CONFIG_SSB_DRIVER_MIPS) := driver_mips/mips.o
-+ssb-driver-pci-$(CONFIG_SSB_DRIVER_PCICORE) := driver_pci/pcicore.o
-+
-+ssb-$(CONFIG_SSB_PCIHOST) += pci.o
-+ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.o
-+
-+obj-$(CONFIG_SSB) += ssb.o
-+
-+ssb-objs := core.o scan.o \
-+ $(ssb-y) $(ssb-m) \
-+ $(ssb-driver-chipcommon-y) \
-+ $(ssb-driver-mips-y) \
-+ $(ssb-driver-pci-y)
-diff -urN linux.old/drivers/ssb/pci.c linux.dev/drivers/ssb/pci.c
---- linux.old/drivers/ssb/pci.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/ssb/pci.c 2007-01-26 00:44:13.000000000 +0100
-@@ -0,0 +1,480 @@
-+/*
-+ * Sonics Silicon Backplane PCI-Hostbus related functions.
-+ *
-+ * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
-+ * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
-+ * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
-+ * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
-+ * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
-+ *
-+ * Derived from the Broadcom 4400 device driver.
-+ * Copyright (C) 2002 David S. Miller (davem@redhat.com)
-+ * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
-+ * Copyright (C) 2006 Broadcom Corporation.
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include <linux/ssb/ssb.h>
-+#include <linux/ssb/ssb_regs.h>
-+#include <linux/pci.h>
-+#include <linux/delay.h>
-+
-+#include "ssb_private.h"
-+
-+
-+int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
-+{
-+ int err;
-+ int attempts = 0;
-+ u32 cur_core;
-+
-+ while (1) {
-+ err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN,
-+ (coreidx * SSB_CORE_SIZE)
-+ + SSB_ENUM_BASE);
-+ if (err)
-+ goto error;
-+ err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN,
-+ &cur_core);
-+ if (err)
-+ goto error;
-+ cur_core = (cur_core - SSB_ENUM_BASE)
-+ / SSB_CORE_SIZE;
-+ if (cur_core == coreidx)
-+ break;
-+
-+ if (attempts++ > SSB_BAR0_MAX_RETRIES)
-+ goto error;
-+ udelay(10);
-+ }
-+ return 0;
-+error:
-+ ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
-+ return -ENODEV;
-+}
-+
-+int ssb_pci_switch_core(struct ssb_bus *bus,
-+ struct ssb_device *dev)
-+{
-+ int err;
-+ unsigned long flags;
-+
-+ ssb_dprintk(KERN_INFO PFX
-+ "Switching to %s core, index %d\n",
-+ ssb_core_name(dev->id.coreid),
-+ dev->core_index);
-+
-+ spin_lock_irqsave(&bus->bar_lock, flags);
-+ err = ssb_pci_switch_coreidx(bus, dev->core_index);
-+ if (!err)
-+ bus->mapped_device = dev;
-+ spin_unlock_irqrestore(&bus->bar_lock, flags);
-+
-+ return err;
-+}
-+
-+int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
-+{
-+ int err;
-+ u32 in, out, outenable;
-+ u16 pci_status;
-+
-+ if (bus->bustype != SSB_BUSTYPE_PCI)
-+ return 0;
-+
-+ err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
-+ if (err)
-+ goto err_pci;
-+ err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
-+ if (err)
-+ goto err_pci;
-+ err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
-+ if (err)
-+ goto err_pci;
-+
-+ outenable |= what;
-+
-+ if (turn_on) {
-+ /* Avoid glitching the clock if GPRS is already using it.
-+ * We can't actually read the state of the PLLPD so we infer it
-+ * by the value of XTAL_PU which *is* readable via gpioin.
-+ */
-+ if (!(in & SSB_GPIO_XTAL)) {
-+ if (what & SSB_GPIO_XTAL) {
-+ /* Turn the crystal on */
-+ out |= SSB_GPIO_XTAL;
-+ if (what & SSB_GPIO_PLL)
-+ out |= SSB_GPIO_PLL;
-+ err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
-+ if (err)
-+ goto err_pci;
-+ err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
-+ outenable);
-+ if (err)
-+ goto err_pci;
-+ msleep(1);
-+ }
-+ if (what & SSB_GPIO_PLL) {
-+ /* Turn the PLL on */
-+ out &= ~SSB_GPIO_PLL;
-+ err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
-+ if (err)
-+ goto err_pci;
-+ msleep(2);
-+ }
-+ }
-+
-+ err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status);
-+ if (err)
-+ goto err_pci;
-+ pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT;
-+ err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status);
-+ if (err)
-+ goto err_pci;
-+ } else {
-+ if (what & SSB_GPIO_XTAL) {
-+ /* Turn the crystal off */
-+ out &= ~SSB_GPIO_XTAL;
-+ }
-+ if (what & SSB_GPIO_PLL) {
-+ /* Turn the PLL off */
-+ out |= SSB_GPIO_PLL;
-+ }
-+ err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
-+ if (err)
-+ goto err_pci;
-+ err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
-+ if (err)
-+ goto err_pci;
-+ }
-+
-+out:
-+ return err;
-+
-+err_pci:
-+ printk(KERN_ERR PFX "Error: ssb_pci_xtal() could not access PCI config space!\n");
-+ err = -EBUSY;
-+ goto out;
-+}
-+
-+#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
-+#define SPEX(_outvar, _offset, _mask, _shift) \
-+ out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
-+
-+static inline u8 ssb_crc8(u8 crc, u8 data)
-+{
-+ /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
-+ static const u8 t[] = {
-+ 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
-+ 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
-+ 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
-+ 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
-+ 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
-+ 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
-+ 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
-+ 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
-+ 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
-+ 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
-+ 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
-+ 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
-+ 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
-+ 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
-+ 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
-+ 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
-+ 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
-+ 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
-+ 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
-+ 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
-+ 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
-+ 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
-+ 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
-+ 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
-+ 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
-+ 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
-+ 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
-+ 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
-+ 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
-+ 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
-+ 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
-+ 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
-+ };
-+ return t[crc ^ data];
-+}
-+
-+static u8 ssb_sprom_crc(const u16 *sprom)
-+{
-+ int word;
-+ u8 crc = 0xFF;
-+
-+ for (word = 0; word < SSB_SPROMSIZE_WORDS - 1; word++) {
-+ crc = ssb_crc8(crc, sprom[word] & 0x00FF);
-+ crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8);
-+ }
-+ crc = ssb_crc8(crc, sprom[SPOFF(SSB_SPROM_REVISION)] & 0x00FF);
-+ crc ^= 0xFF;
-+
-+ return crc;
-+}
-+
-+static int sprom_check_crc(const u16 *sprom)
-+{
-+ u8 crc;
-+ u8 expected_crc;
-+ u16 tmp;
-+
-+ crc = ssb_sprom_crc(sprom);
-+ tmp = sprom[SPOFF(SSB_SPROM_REVISION)] & SSB_SPROM_REVISION_CRC;
-+ expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
-+ if (crc != expected_crc)
-+ return -EPROTO;
-+
-+ return 0;
-+}
-+
-+static void sprom_do_read(struct ssb_bus *bus, u16 *sprom)
-+{
-+ int i;
-+
-+ for (i = 0; i < SSB_SPROMSIZE_WORDS; i++)
-+ sprom[i] = readw(bus->mmio + SSB_SPROM_BASE + (i * 2));
-+}
-+
-+static void sprom_extract_r1(struct ssb_sprom_r1 *out, const u16 *in)
-+{
-+ int i;
-+ u16 v;
-+
-+ SPEX(pci_spid, SSB_SPROM1_SPID, 0xFFFF, 0);
-+ SPEX(pci_svid, SSB_SPROM1_SVID, 0xFFFF, 0);
-+ SPEX(pci_pid, SSB_SPROM1_PID, 0xFFFF, 0);
-+ for (i = 0; i < 3; i++) {
-+ v = in[SPOFF(SSB_SPROM1_IL0MAC) + i];
-+ *(((u16 *)out->il0mac) + i) = cpu_to_be16(v);
-+ }
-+ for (i = 0; i < 3; i++) {
-+ v = in[SPOFF(SSB_SPROM1_ET0MAC) + i];
-+ *(((u16 *)out->et0mac) + i) = cpu_to_be16(v);
-+ }
-+ for (i = 0; i < 3; i++) {
-+ v = in[SPOFF(SSB_SPROM1_ET1MAC) + i];
-+ *(((u16 *)out->et1mac) + i) = cpu_to_be16(v);
-+ }
-+ SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
-+ SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
-+ SSB_SPROM1_ETHPHY_ET1A_SHIFT);
-+ SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
-+ SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
-+ SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
-+ SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
-+ SSB_SPROM1_BINF_CCODE_SHIFT);
-+ SPEX(antenna_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
-+ SSB_SPROM1_BINF_ANTA_SHIFT);
-+ SPEX(antenna_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
-+ SSB_SPROM1_BINF_ANTBG_SHIFT);
-+ SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
-+ SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
-+ SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
-+ SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
-+ SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
-+ SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
-+ SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
-+ SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
-+ SSB_SPROM1_GPIOA_P1_SHIFT);
-+ SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
-+ SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
-+ SSB_SPROM1_GPIOB_P3_SHIFT);
-+ SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A, 0);
-+ SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG,
-+ SSB_SPROM1_MAXPWR_BG_SHIFT);
-+ SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A, 0);
-+ SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG,
-+ SSB_SPROM1_ITSSI_BG_SHIFT);
-+ SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
-+ SPEX(antenna_gain_a, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_A, 0);
-+ SPEX(antenna_gain_bg, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_BG,
-+ SSB_SPROM1_AGAIN_BG_SHIFT);
-+ for (i = 0; i < 4; i++) {
-+ v = in[SPOFF(SSB_SPROM1_OEM) + i];
-+ *(((u16 *)out->oem) + i) = cpu_to_le16(v);
-+ }
-+}
-+
-+static void sprom_extract_r2(struct ssb_sprom_r2 *out, const u16 *in)
-+{
-+ int i;
-+ u16 v;
-+
-+ SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
-+ SPEX(maxpwr_a_hi, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
-+ SPEX(maxpwr_a_lo, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
-+ SSB_SPROM2_MAXP_A_LO_SHIFT);
-+ SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
-+ SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
-+ SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
-+ SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
-+ SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
-+ SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
-+ SPEX(ofdm_pwr_off, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
-+ for (i = 0; i < 4; i++) {
-+ v = in[SPOFF(SSB_SPROM2_CCODE) + i];
-+ *(((u16 *)out->country_str) + i) = cpu_to_le16(v);
-+ }
-+}
-+
-+static void sprom_extract_r3(struct ssb_sprom_r3 *out, const u16 *in)
-+{
-+ out->ofdmapo = (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0xFF00) >> 8;
-+ out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0x00FF) << 8;
-+ out->ofdmapo <<= 16;
-+ out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0xFF00) >> 8;
-+ out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0x00FF) << 8;
-+
-+ out->ofdmalpo = (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0xFF00) >> 8;
-+ out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0x00FF) << 8;
-+ out->ofdmalpo <<= 16;
-+ out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0xFF00) >> 8;
-+ out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0x00FF) << 8;
-+
-+ out->ofdmahpo = (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0xFF00) >> 8;
-+ out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0x00FF) << 8;
-+ out->ofdmahpo <<= 16;
-+ out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0xFF00) >> 8;
-+ out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0x00FF) << 8;
-+
-+ SPEX(gpioldc_on_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_ON,
-+ SSB_SPROM3_GPIOLDC_ON_SHIFT);
-+ SPEX(gpioldc_off_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_OFF,
-+ SSB_SPROM3_GPIOLDC_OFF_SHIFT);
-+ SPEX(cckpo_1M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_1M, 0);
-+ SPEX(cckpo_2M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_2M,
-+ SSB_SPROM3_CCKPO_2M_SHIFT);
-+ SPEX(cckpo_55M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_55M,
-+ SSB_SPROM3_CCKPO_55M_SHIFT);
-+ SPEX(cckpo_11M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_11M,
-+ SSB_SPROM3_CCKPO_11M_SHIFT);
-+
-+ out->ofdmgpo = (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0xFF00) >> 8;
-+ out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0x00FF) << 8;
-+ out->ofdmgpo <<= 16;
-+ out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0xFF00) >> 8;
-+ out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0x00FF) << 8;
-+}
-+
-+static int sprom_extract(struct ssb_sprom *out, const u16 *in)
-+{
-+ memset(out, 0, sizeof(*out));
-+
-+ SPEX(revision, SSB_SPROM_REVISION, SSB_SPROM_REVISION_REV, 0);
-+ SPEX(crc, SSB_SPROM_REVISION, SSB_SPROM_REVISION_CRC,
-+ SSB_SPROM_REVISION_CRC_SHIFT);
-+
-+ if (out->revision == 0)
-+ goto unsupported;
-+ if (out->revision >= 1 && out->revision <= 3)
-+ sprom_extract_r1(&out->r1, in);
-+ if (out->revision >= 2 && out->revision <= 3)
-+ sprom_extract_r2(&out->r2, in);
-+ if (out->revision == 3)
-+ sprom_extract_r3(&out->r3, in);
-+ if (out->revision >= 4)
-+ goto unsupported;
-+
-+ return 0;
-+unsupported:
-+ ssb_printk(KERN_WARNING PFX "Unsupported SPROM revision %d "
-+ "detected. Will extract v1\n", out->revision);
-+ sprom_extract_r1(&out->r1, in);
-+ return 0;
-+}
-+
-+int ssb_pci_sprom_get(struct ssb_bus *bus)
-+{
-+ int err = -ENOMEM;
-+ u16 *buf;
-+
-+ assert(bus->bustype == SSB_BUSTYPE_PCI);
-+
-+ buf = kcalloc(SSB_SPROMSIZE_WORDS, sizeof(u16), GFP_KERNEL);
-+ if (!buf)
-+ goto out;
-+ sprom_do_read(bus, buf);
-+ err = sprom_check_crc(buf);
-+ if (err) {
-+ ssb_printk(KERN_WARNING PFX
-+ "WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
-+ }
-+ err = sprom_extract(&bus->sprom, buf);
-+
-+ kfree(buf);
-+out:
-+ return err;
-+}
-+
-+void ssb_pci_get_boardtype(struct ssb_bus *bus)
-+{
-+ pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
-+ &bus->board_vendor);
-+ pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
-+ &bus->board_type);
-+ pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
-+ &bus->board_rev);
-+}
-+
-+static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ if (unlikely(bus->mapped_device != dev)) {
-+ if (unlikely(ssb_pci_switch_core(bus, dev)))
-+ return 0xFFFF;
-+ }
-+ return readw(bus->mmio + offset);
-+}
-+
-+static u32 ssb_pci_read32(struct ssb_device *dev, u16 offset)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ if (unlikely(bus->mapped_device != dev)) {
-+ if (unlikely(ssb_pci_switch_core(bus, dev)))
-+ return 0xFFFFFFFF;
-+ }
-+ return readl(bus->mmio + offset);
-+}
-+
-+static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ if (unlikely(bus->mapped_device != dev)) {
-+ if (unlikely(ssb_pci_switch_core(bus, dev)))
-+ return;
-+ }
-+ writew(value, bus->mmio + offset);
-+}
-+
-+static void ssb_pci_write32(struct ssb_device *dev, u16 offset, u32 value)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ if (unlikely(bus->mapped_device != dev)) {
-+ if (unlikely(ssb_pci_switch_core(bus, dev)))
-+ return;
-+ }
-+ writel(value, bus->mmio + offset);
-+}
-+
-+const struct ssb_bus_ops ssb_pci_ops = {
-+ .read16 = ssb_pci_read16,
-+ .read32 = ssb_pci_read32,
-+ .write16 = ssb_pci_write16,
-+ .write32 = ssb_pci_write32,
-+};
-+
-+int ssb_pci_init(struct ssb_bus *bus)
-+{
-+ if (bus->bustype != SSB_BUSTYPE_PCI)
-+ return 0;
-+ return ssb_pci_sprom_get(bus);
-+}
-diff -urN linux.old/drivers/ssb/pcmcia.c linux.dev/drivers/ssb/pcmcia.c
---- linux.old/drivers/ssb/pcmcia.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/ssb/pcmcia.c 2007-01-26 00:44:13.000000000 +0100
-@@ -0,0 +1,256 @@
-+/*
-+ * Sonics Silicon Backplane
-+ * PCMCIA-Hostbus related functions
-+ *
-+ * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
-+ * Copyright 2007 Michael Buesch <mb@bu3sch.de>
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include <linux/ssb/ssb.h>
-+#include <linux/delay.h>
-+
-+#include <pcmcia/cs_types.h>
-+#include <pcmcia/cs.h>
-+#include <pcmcia/cistpl.h>
-+#include <pcmcia/ciscode.h>
-+#include <pcmcia/ds.h>
-+#include <pcmcia/cisreg.h>
-+
-+#include "ssb_private.h"
-+
-+
-+int ssb_pcmcia_switch_coreidx(struct ssb_bus *bus,
-+ u8 coreidx)
-+{
-+ struct pcmcia_device *pdev = bus->host_pcmcia;
-+ int err;
-+ int attempts = 0;
-+ u32 cur_core;
-+ conf_reg_t reg;
-+ u32 addr;
-+ u32 read_addr;
-+
-+ addr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE;
-+ while (1) {
-+ reg.Action = CS_WRITE;
-+ reg.Offset = 0x2E;
-+ reg.Value = (addr & 0x0000F000) >> 12;
-+ err = pcmcia_access_configuration_register(pdev, ®);
-+ if (err != CS_SUCCESS)
-+ goto error;
-+ reg.Offset = 0x30;
-+ reg.Value = (addr & 0x00FF0000) >> 16;
-+ err = pcmcia_access_configuration_register(pdev, ®);
-+ if (err != CS_SUCCESS)
-+ goto error;
-+ reg.Offset = 0x32;
-+ reg.Value = (addr & 0xFF000000) >> 24;
-+ err = pcmcia_access_configuration_register(pdev, ®);
-+ if (err != CS_SUCCESS)
-+ goto error;
-+
-+ read_addr = 0;
-+
-+ reg.Action = CS_READ;
-+ reg.Offset = 0x2E;
-+ err = pcmcia_access_configuration_register(pdev, ®);
-+ if (err != CS_SUCCESS)
-+ goto error;
-+ read_addr |= (reg.Value & 0xF) << 12;
-+ reg.Offset = 0x30;
-+ err = pcmcia_access_configuration_register(pdev, ®);
-+ if (err != CS_SUCCESS)
-+ goto error;
-+ read_addr |= reg.Value << 16;
-+ reg.Offset = 0x32;
-+ err = pcmcia_access_configuration_register(pdev, ®);
-+ if (err != CS_SUCCESS)
-+ goto error;
-+ read_addr |= reg.Value << 24;
-+
-+ cur_core = (read_addr - SSB_ENUM_BASE) / SSB_CORE_SIZE;
-+ if (cur_core == coreidx)
-+ break;
-+
-+ if (attempts++ > SSB_BAR0_MAX_RETRIES)
-+ goto error;
-+ udelay(10);
-+ }
-+
-+ return 0;
-+error:
-+ ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
-+ return -ENODEV;
-+}
-+
-+int ssb_pcmcia_switch_core(struct ssb_bus *bus,
-+ struct ssb_device *dev)
-+{
-+ int err;
-+ unsigned long flags;
-+
-+ ssb_dprintk(KERN_INFO PFX
-+ "Switching to %s core, index %d\n",
-+ ssb_core_name(dev->id.coreid),
-+ dev->core_index);
-+
-+ spin_lock_irqsave(&bus->bar_lock, flags);
-+ err = ssb_pcmcia_switch_coreidx(bus, dev->core_index);
-+ if (!err)
-+ bus->mapped_device = dev;
-+ spin_unlock_irqrestore(&bus->bar_lock, flags);
-+
-+ return err;
-+}
-+
-+int ssb_pcmcia_switch_segment(struct ssb_bus *bus, u8 seg)
-+{
-+ int attempts = 0;
-+ unsigned long flags;
-+ conf_reg_t reg;
-+ int res, err = 0;
-+
-+ assert(seg == 0 || seg == 1);
-+ reg.Offset = 0x34;
-+ reg.Function = 0;
-+ spin_lock_irqsave(&bus->bar_lock, flags);
-+ while (1) {
-+ reg.Action = CS_WRITE;
-+ reg.Value = seg;
-+ res = pcmcia_access_configuration_register(bus->host_pcmcia, ®);
-+ if (unlikely(res != CS_SUCCESS))
-+ goto error;
-+ reg.Value = 0xFF;
-+ reg.Action = CS_READ;
-+ res = pcmcia_access_configuration_register(bus->host_pcmcia, ®);
-+ if (unlikely(res != CS_SUCCESS))
-+ goto error;
-+
-+ if (reg.Value == seg)
-+ break;
-+
-+ if (unlikely(attempts++ > SSB_BAR0_MAX_RETRIES))
-+ goto error;
-+ udelay(10);
-+ }
-+ bus->mapped_pcmcia_seg = seg;
-+out_unlock:
-+ spin_unlock_irqrestore(&bus->bar_lock, flags);
-+ return err;
-+error:
-+ ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n");
-+ err = -ENODEV;
-+ goto out_unlock;
-+}
-+
-+static inline int do_select_core(struct ssb_bus *bus,
-+ struct ssb_device *dev,
-+ u16 *offset)
-+{
-+ int err;
-+ u8 need_seg = (*offset >= 0x800) ? 1 : 0;
-+
-+ if (unlikely(dev != bus->mapped_device)) {
-+ err = ssb_pcmcia_switch_core(bus, dev);
-+ if (unlikely(err))
-+ return err;
-+ }
-+ if (unlikely(need_seg != bus->mapped_pcmcia_seg)) {
-+ err = ssb_pcmcia_switch_segment(bus, need_seg);
-+ if (unlikely(err))
-+ return err;
-+ }
-+ if (need_seg == 1)
-+ *offset -= 0x800;
-+
-+ return 0;
-+}
-+
-+static u16 ssb_pcmcia_read16(struct ssb_device *dev, u16 offset)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+ u16 x;
-+
-+ if (unlikely(do_select_core(bus, dev, &offset)))
-+ return 0xFFFF;
-+ x = readw(bus->mmio + offset);
-+//printk("R16 0x%04X, 0x%04X\n", offset, x);
-+ return x;
-+}
-+
-+static u32 ssb_pcmcia_read32(struct ssb_device *dev, u16 offset)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+ u32 x;
-+
-+ if (unlikely(do_select_core(bus, dev, &offset)))
-+ return 0xFFFFFFFF;
-+ x = readl(bus->mmio + offset);
-+//printk("R32 0x%04X, 0x%08X\n", offset, x);
-+ return x;
-+}
-+
-+static void ssb_pcmcia_write16(struct ssb_device *dev, u16 offset, u16 value)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ if (unlikely(do_select_core(bus, dev, &offset)))
-+ return;
-+//printk("W16 0x%04X, 0x%04X\n", offset, value);
-+ writew(value, bus->mmio + offset);
-+}
-+
-+static void ssb_pcmcia_write32(struct ssb_device *dev, u16 offset, u32 value)
-+{
-+ struct ssb_bus *bus = dev->bus;
-+
-+ if (unlikely(do_select_core(bus, dev, &offset)))
-+ return;
-+//printk("W32 0x%04X, 0x%08X\n", offset, value);
-+ readw(bus->mmio + offset);
-+ writew(value >> 16, bus->mmio + offset + 2);
-+ readw(bus->mmio + offset);
-+ writew(value, bus->mmio + offset);
-+}
-+
-+const struct ssb_bus_ops ssb_pcmcia_ops = {
-+ .read16 = ssb_pcmcia_read16,
-+ .read32 = ssb_pcmcia_read32,
-+ .write16 = ssb_pcmcia_write16,
-+ .write32 = ssb_pcmcia_write32,
-+};
-+
-+int ssb_pcmcia_init(struct ssb_bus *bus)
-+{
-+ conf_reg_t reg;
-+ int err;
-+
-+ if (bus->bustype != SSB_BUSTYPE_PCMCIA)
-+ return 0;
-+
-+ /* Switch segment to a known state and sync
-+ * bus->mapped_pcmcia_seg with hardware state. */
-+ ssb_pcmcia_switch_segment(bus, 0);
-+
-+ /* Init IRQ routing */
-+ reg.Action = CS_READ;
-+ reg.Function = 0;
-+ if (bus->chip_id == 0x4306)
-+ reg.Offset = 0x00;
-+ else
-+ reg.Offset = 0x80;
-+ err = pcmcia_access_configuration_register(bus->host_pcmcia, ®);
-+ if (err != CS_SUCCESS)
-+ goto error;
-+ reg.Action = CS_WRITE;
-+ reg.Value |= 0x04 | 0x01;
-+ err = pcmcia_access_configuration_register(bus->host_pcmcia, ®);
-+ if (err != CS_SUCCESS)
-+ goto error;
-+
-+ return 0;
-+error:
-+ return -ENODEV;
-+}
-diff -urN linux.old/drivers/ssb/scan.c linux.dev/drivers/ssb/scan.c
---- linux.old/drivers/ssb/scan.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux.dev/drivers/ssb/scan.c 2007-01-26 00:44:13.000000000 +0100
-@@ -0,0 +1,373 @@
-+/*
-+ * Sonics Silicon Backplane
-+ * Bus scanning
-+ *
-+ * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
-+ * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
-+ * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
-+ * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
-+ * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
-+ * Copyright (C) 2006 Broadcom Corporation.
-+ *
-+ * Licensed under the GNU/GPL. See COPYING for details.
-+ */
-+
-+#include <linux/ssb/ssb.h>
-+#include <linux/ssb/ssb_regs.h>
-+#include <linux/pci.h>
-+#include <asm/io.h>
-+
-+#include "ssb_private.h"
-+
projects / openwrt.git / blobdiff