---- linux-2.6.22-rc5.orig/drivers/ssb/driver_chipcommon.c 2007-06-21 23:04:38.000000000 +0100
-+++ linux-2.6.22-rc5/drivers/ssb/driver_chipcommon.c 2007-06-24 20:07:15.000000000 +0100
-@@ -264,6 +264,31 @@
- ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
- }
-
-+/* TODO: These two functions are a clear candidate for merging, but one gets
-+ * the processor clock, and the other gets the bus clock.
-+ */
-+void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
-+ u32 *plltype, u32 *n, u32 *m)
-+{
-+ *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
-+ *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
-+ switch (*plltype) {
-+ case SSB_PLLTYPE_2:
-+ case SSB_PLLTYPE_4:
-+ case SSB_PLLTYPE_6:
-+ case SSB_PLLTYPE_7:
-+ *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
-+ break;
-+ case SSB_PLLTYPE_3:
-+ /* 5350 uses m2 to control mips */
-+ *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
-+ break;
-+ default:
-+ *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
-+ break;
-+ }
-+}
-+
- void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
- u32 *plltype, u32 *n, u32 *m)
- {
-@@ -400,3 +425,13 @@
- return nr_ports;
- }
- #endif /* CONFIG_SSB_SERIAL */
-+
-+/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
-+int
-+ssb_chipco_watchdog(struct ssb_chipcommon *cc, uint ticks)
-+{
-+ /* instant NMI */
-+ chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
-+ return 0;
-+}
-+EXPORT_SYMBOL(ssb_chipco_watchdog);
-Index: linux-2.6.22-rc5/drivers/ssb/driver_mipscore.c
-===================================================================
---- linux-2.6.22-rc5.orig/drivers/ssb/driver_mipscore.c 2007-06-10 16:44:31.000000000 +0100
-+++ linux-2.6.22-rc5/drivers/ssb/driver_mipscore.c 2007-06-24 20:48:52.000000000 +0100
-@@ -4,6 +4,7 @@
- *
- * Copyright 2005, Broadcom Corporation
- * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
-+ * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
- *
- * Licensed under the GNU/GPL. See COPYING for details.
- */
-@@ -31,6 +32,16 @@
- ssb_write32(mcore->dev, offset, value);
- }
-
-+static inline u32 extif_read32(struct ssb_extif *extif, u16 offset)
-+{
-+ return ssb_read32(extif->dev, offset);
-+}
-+
-+static inline void extif_write32(struct ssb_extif *extif, u16 offset, u32 value)
-+{
-+ ssb_write32(extif->dev, offset, value);
-+}
-+
- static const u32 ipsflag_irq_mask[] = {
- 0,
- SSB_IPSFLAG_IRQ1,
-@@ -118,9 +129,9 @@
- }
-
- /* XXX: leave here or move into separate extif driver? */
--static int ssb_extif_serial_init(struct ssb_device *dev, struct ssb_serial_ports *ports)
-+static int ssb_extif_serial_init(struct ssb_extif *dev, struct ssb_serial_port *ports)
- {
--
-+ return 0;
- }
-
-
-@@ -174,23 +185,76 @@
- {
- struct ssb_bus *bus = mcore->dev->bus;
-
-+ mcore->flash_buswidth = 2;
- if (bus->chipco.dev) {
- mcore->flash_window = 0x1c000000;
-- mcore->flash_window_size = 0x800000;
-+ mcore->flash_window_size = 0x02000000;
-+ if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
-+ & SSB_CHIPCO_CFG_DS16) == 0)
-+ mcore->flash_buswidth = 1;
- } else {
- mcore->flash_window = 0x1fc00000;
-- mcore->flash_window_size = 0x400000;
-+ mcore->flash_window_size = 0x00400000;
- }
- }
-
-+static void ssb_extif_timing_init(struct ssb_extif *extif, u32 ns)
-+{
-+ u32 tmp;
-+
-+ /* Initialize extif so we can get to the LEDs and external UART */
-+ extif_write32(extif, SSB_EXTIF_PROG_CFG, SSB_EXTCFG_EN);
-+
-+ /* Set timing for the flash */
-+ tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;
-+ tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT;
-+ tmp |= DIV_ROUND_UP(120, ns);
-+ extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
-+
-+ /* Set programmable interface timing for external uart */
-+ tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT;
-+ tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT;
-+ tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT;
-+ tmp |= DIV_ROUND_UP(120, ns);
-+ extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp);
-+}
-
--static void ssb_cpu_clock(struct ssb_mipscore *mcore)
-+static inline void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
-+ u32 *pll_type, u32 *n, u32 *m)
- {
-+ *pll_type = SSB_PLLTYPE_1;
-+ *n = extif_read32(extif, SSB_EXTIF_CLOCK_N);
-+ *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
- }
-
--void ssb_mipscore_init(struct ssb_mipscore *mcore)
-+u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
- {
- struct ssb_bus *bus = mcore->dev->bus;
-+ u32 pll_type, n, m, rate = 0;
-+
-+ if (bus->extif.dev) {
-+ ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
-+ } else if (bus->chipco.dev) {
-+ ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
-+ } else
-+ return 0;
-+
-+ if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
-+ rate = 200000000;
-+ } else {
-+ rate = ssb_calc_clock_rate(pll_type, n, m);
-+ }
-+
-+ if (pll_type == SSB_PLLTYPE_6) {
-+ rate *= 2;
-+ }
-+
-+ return rate;
-+}
-+
-+void ssb_mipscore_init(struct ssb_mipscore *mcore)
-+{
-+ struct ssb_bus *bus;
- struct ssb_device *dev;
- unsigned long hz, ns;
- unsigned int irq, i;
-@@ -198,6 +262,8 @@
- if (!mcore->dev)
- return; /* We don't have a MIPS core */
-
-+ bus = mcore->dev->bus;
-+
- ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
-
- hz = ssb_clockspeed(bus);
-@@ -205,28 +271,9 @@
- hz = 100000000;
- ns = 1000000000 / hz;
-
--//TODO
--#if 0
-- if (have EXTIF) {
-- /* Initialize extif so we can get to the LEDs and external UART */
-- W_REG(&eir->prog_config, CF_EN);
--
-- /* Set timing for the flash */
-- tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
-- tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
-- tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
-- W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
--
-- /* Set programmable interface timing for external uart */
-- tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
-- tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
-- tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
-- tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
-- W_REG(&eir->prog_waitcount, tmp);
-- }
-- else... chipcommon
--#endif
-- if (bus->chipco.dev)
-+ if (bus->extif.dev)
-+ ssb_extif_timing_init(&bus->extif, ns);
-+ else if (bus->chipco.dev)
- ssb_chipco_timing_init(&bus->chipco, ns);
-
- /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
-@@ -256,3 +303,5 @@
projects / openwrt.git / blobdiff