ar71xx: add AR933x specific glue code for IRQ initialization

[openwrt.git] / target / linux / ar71xx / files / arch / mips / pci / pci-ar71xx.c

diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
index ac94da9..5f10d6a 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
+++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
@@ -1,7 +1,7 @@
 /*
  *  Atheros AR71xx PCI host controller driver
  *
 /*
  *  Atheros AR71xx PCI host controller driver
  *

- *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>

  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Parts of this file are based on Atheros' 2.6.15 BSP
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Parts of this file are based on Atheros' 2.6.15 BSP


@@ -46,16 +46,6 @@ static inline void ar71xx_pci_delay(void)
        mdelay(AR71XX_PCI_DELAY);
 }
 
        mdelay(AR71XX_PCI_DELAY);
 }
 

-static inline u32 ar71xx_pcicfg_rr(unsigned int reg)
-{
-       return __raw_readl(ar71xx_pcicfg_base + reg);
-}
-
-static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
-{
-       __raw_writel(val, ar71xx_pcicfg_base + reg);
-}
-

 /* Byte lane enable bits */
 static u8 ble_table[4][4] = {
        {0x0, 0xf, 0xf, 0xf},
 /* Byte lane enable bits */
 static u8 ble_table[4][4] = {
        {0x0, 0xf, 0xf, 0xf},


@@ -94,34 +84,36 @@ static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
 
 int ar71xx_pci_be_handler(int is_fixup)
 {
 
 int ar71xx_pci_be_handler(int is_fixup)
 {

+       void __iomem *base = ar71xx_pcicfg_base;

        u32 pci_err;
        u32 ahb_err;
 
        u32 pci_err;
        u32 ahb_err;
 

-       pci_err = ar71xx_pcicfg_rr(PCI_REG_PCI_ERR) & 3;
+       pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3;

        if (pci_err) {
                if (!is_fixup)
                        printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
                                pci_err,
        if (pci_err) {
                if (!is_fixup)
                        printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
                                pci_err,

-                               ar71xx_pcicfg_rr(PCI_REG_PCI_ERR_ADDR));
+                               __raw_readl(base + PCI_REG_PCI_ERR_ADDR));

 
 

-               ar71xx_pcicfg_wr(PCI_REG_PCI_ERR, pci_err);
+               __raw_writel(pci_err, base + PCI_REG_PCI_ERR);

        }
 
        }
 

-       ahb_err = ar71xx_pcicfg_rr(PCI_REG_AHB_ERR) & 1;
+       ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1;

        if (ahb_err) {
                if (!is_fixup)
                        printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
        if (ahb_err) {
                if (!is_fixup)
                        printk(KERN_ALERT "AHB error at AHB address 0x%x\n",

-                               ar71xx_pcicfg_rr(PCI_REG_AHB_ERR_ADDR));
+                               __raw_readl(base + PCI_REG_AHB_ERR_ADDR));

 
 

-               ar71xx_pcicfg_wr(PCI_REG_AHB_ERR, ahb_err);
+               __raw_writel(ahb_err, base + PCI_REG_AHB_ERR);

        }
 
        }
 

-       return ((ahb_err | pci_err) ? 1 : 0);
+       return (ahb_err | pci_err) ? 1 : 0;

 }
 
 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
                        unsigned int devfn, int where, int size, u32 cmd)
 {
 }
 
 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
                        unsigned int devfn, int where, int size, u32 cmd)
 {

+       void __iomem *base = ar71xx_pcicfg_base;

        u32 addr;
 
        addr = ar71xx_pci_bus_addr(bus, devfn, where);
        u32 addr;
 
        addr = ar71xx_pci_bus_addr(bus, devfn, where);


@@ -130,9 +122,9 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
                bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
                where, size, addr);
 
                bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
                where, size, addr);
 

-       ar71xx_pcicfg_wr(PCI_REG_CFG_AD, addr);
-       ar71xx_pcicfg_wr(PCI_REG_CFG_CBE,
-                       cmd | ar71xx_pci_get_ble(where, size, 0));
+       __raw_writel(addr, base + PCI_REG_CFG_AD);
+       __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
+                    base + PCI_REG_CFG_CBE);

 
        return ar71xx_pci_be_handler(1);
 }
 
        return ar71xx_pci_be_handler(1);
 }


@@ -140,9 +132,11 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
                                  int where, int size, u32 *value)
 {
 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
                                  int where, int size, u32 *value)
 {

+       void __iomem *base = ar71xx_pcicfg_base;

        static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
        unsigned long flags;
        u32 data;
        static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
        unsigned long flags;
        u32 data;

+       int retry = 0;

        int ret;
 
        ret = PCIBIOS_SUCCESSFUL;
        int ret;
 
        ret = PCIBIOS_SUCCESSFUL;


@@ -150,6 +144,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
        DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
                        PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
 
        DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
                        PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
 

+retry:

        spin_lock_irqsave(&ar71xx_pci_lock, flags);
 
        if (bus->number == 0 && devfn == 0) {
        spin_lock_irqsave(&ar71xx_pci_lock, flags);
 
        if (bus->number == 0 && devfn == 0) {


@@ -157,8 +152,8 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 
                t = PCI_CRP_CMD_READ | (where & ~3);
 
 
                t = PCI_CRP_CMD_READ | (where & ~3);
 

-               ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
-               data = ar71xx_pcicfg_rr(PCI_REG_CRP_RDDATA);
+               __raw_writel(t, base + PCI_REG_CRP_AD_CBE);
+               data = __raw_readl(base + PCI_REG_CRP_RDDATA);

 
                DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
 
 
                DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
 


@@ -169,7 +164,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
                                                PCI_CFG_CMD_READ);
 
                if (err == 0) {
                                                PCI_CFG_CMD_READ);
 
                if (err == 0) {

-                       data = ar71xx_pcicfg_rr(PCI_REG_CFG_RDDATA);
+                       data = __raw_readl(base + PCI_REG_CFG_RDDATA);

                } else {
                        ret = PCIBIOS_DEVICE_NOT_FOUND;
                        data = ~0;
                } else {
                        ret = PCIBIOS_DEVICE_NOT_FOUND;
                        data = ~0;


@@ -183,12 +178,21 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 
        *value = (data >> (8 * (where & 3))) & mask[size & 7];
 
 
        *value = (data >> (8 * (where & 3))) & mask[size & 7];
 

+       /*
+        * PCI controller bug: sometimes reads to the PCI_COMMAND register
+        * return 0xffff, even though the PCI trace shows the correct value.
+        * Work around this by retrying reads to this register
+        */
+       if (where == PCI_COMMAND && (*value & 0xffff) == 0xffff && retry++ < 2)
+               goto retry;
+

        return ret;
 }
 
 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
                                   int where, int size, u32 value)
 {
        return ret;
 }
 
 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
                                   int where, int size, u32 value)
 {

+       void __iomem *base = ar71xx_pcicfg_base;

        unsigned long flags;
        int ret;
 
        unsigned long flags;
        int ret;
 


@@ -208,8 +212,8 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 
                DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
 
 
                DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
 

-               ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
-               ar71xx_pcicfg_wr(PCI_REG_CRP_WRDATA, value);
+               __raw_writel(t, base + PCI_REG_CRP_AD_CBE);
+               __raw_writel(value, base + PCI_REG_CRP_WRDATA);

        } else {
                int err;
 
        } else {
                int err;
 


@@ -217,7 +221,7 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
                                                PCI_CFG_CMD_WRITE);
 
                if (err == 0)
                                                PCI_CFG_CMD_WRITE);
 
                if (err == 0)

-                       ar71xx_pcicfg_wr(PCI_REG_CFG_WRDATA, value);
+                       __raw_writel(value, base + PCI_REG_CFG_WRDATA);

                else
                        ret = PCIBIOS_DEVICE_NOT_FOUND;
        }
                else
                        ret = PCIBIOS_DEVICE_NOT_FOUND;
        }


@@ -303,10 +307,11 @@ static struct pci_controller ar71xx_pci_controller = {
 
 static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
 
 static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 {

+       void __iomem *base = ar71xx_reset_base;

        u32 pending;
 
        u32 pending;
 

-       pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
-                 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
+       pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
+                 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);

 
        if (pending & PCI_INT_DEV0)
                generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
 
        if (pending & PCI_INT_DEV0)
                generic_handle_irq(AR71XX_PCI_IRQ_DEV0);


@@ -326,22 +331,30 @@ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 static void ar71xx_pci_irq_unmask(unsigned int irq)
 {
 
 static void ar71xx_pci_irq_unmask(unsigned int irq)
 {

+       void __iomem *base = ar71xx_reset_base;
+       u32 t;
+

        irq -= AR71XX_PCI_IRQ_BASE;
        irq -= AR71XX_PCI_IRQ_BASE;

-       ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
-               ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
+
+       t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+       __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);

 
        /* flush write */
 
        /* flush write */

-       ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
+       (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);

 }
 
 static void ar71xx_pci_irq_mask(unsigned int irq)
 {
 }
 
 static void ar71xx_pci_irq_mask(unsigned int irq)
 {

+       void __iomem *base = ar71xx_reset_base;
+       u32 t;
+

        irq -= AR71XX_PCI_IRQ_BASE;
        irq -= AR71XX_PCI_IRQ_BASE;

-       ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
-               ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
+
+       t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+       __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);

 
        /* flush write */
 
        /* flush write */

-       ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
+       (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);

 }
 
 static struct irq_chip ar71xx_pci_irq_chip = {
 }
 
 static struct irq_chip ar71xx_pci_irq_chip = {


@@ -353,10 +366,11 @@ static struct irq_chip ar71xx_pci_irq_chip = {
 
 static void __init ar71xx_pci_irq_init(void)
 {
 
 static void __init ar71xx_pci_irq_init(void)
 {

+       void __iomem *base = ar71xx_reset_base;

        int i;
 
        int i;
 

-       ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
-       ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
+       __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+       __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);

 
        for (i = AR71XX_PCI_IRQ_BASE;
             i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
 
        for (i = AR71XX_PCI_IRQ_BASE;
             i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {


@@ -370,6 +384,8 @@ static void __init ar71xx_pci_irq_init(void)
 
 int __init ar71xx_pcibios_init(void)
 {
 
 int __init ar71xx_pcibios_init(void)
 {

+       void __iomem *ddr_base = ar71xx_ddr_base;
+

        ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
        ar71xx_pci_delay();
 
        ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
        ar71xx_pci_delay();
 


@@ -378,15 +394,17 @@ int __init ar71xx_pcibios_init(void)
 
        ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
                                                AR71XX_PCI_CFG_SIZE);
 
        ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
                                                AR71XX_PCI_CFG_SIZE);

-
-       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
-       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
-       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
-       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
-       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
-       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
-       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
-       ar71xx_ddr_wr(AR71XX_DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
+       if (ar71xx_pcicfg_base == NULL)
+               return -ENOMEM;
+
+       __raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
+       __raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
+       __raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
+       __raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
+       __raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
+       __raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
+       __raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
+       __raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);

 
        ar71xx_pci_delay();
 
 
        ar71xx_pci_delay();