ar71xx: add preliminary support for wzr-hp-g450h

[openwrt.git] / target / linux / brcm63xx / patches-3.0 / 240-spi.patch

diff --git a/target/linux/brcm63xx/patches-3.0/240-spi.patch b/target/linux/brcm63xx/patches-3.0/240-spi.patch
index 4060650..4c5cfa6 100644 (file)
--- a/target/linux/brcm63xx/patches-3.0/240-spi.patch
+++ b/target/linux/brcm63xx/patches-3.0/240-spi.patch
@@ -170,7 +170,7 @@
  #define BCM_6358_OHCI0_IRQ            (IRQ_INTERNAL_BASE + 5)
 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -771,4 +771,116 @@
+@@ -805,4 +805,116 @@
  #define DMIPSPLLCFG_N2_SHIFT          29
  #define DMIPSPLLCFG_N2_MASK           (0x7 << DMIPSPLLCFG_N2_SHIFT)
  
@@ -195,17 +195,17 @@
 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
 +
 +/* BCM 6348 SPI core */
-+#define SPI_BCM_6348_SPI_INT_MASK_ST  0x00
-+#define SPI_BCM_6348_SPI_INT_STATUS   0x01
-+#define SPI_BCM_6348_SPI_CMD          0x02    /* 16-bits register */
-+#define SPI_BCM_6348_SPI_FILL_BYTE    0x04
-+#define SPI_BCM_6348_SPI_CLK_CFG      0x05
-+#define SPI_BCM_6348_SPI_ST           0x06
-+#define SPI_BCM_6348_SPI_INT_MASK     0x07
-+#define SPI_BCM_6348_SPI_RX_TAIL      0x08
-+#define SPI_BCM_6348_SPI_MSG_TAIL     0x10
-+#define SPI_BCM_6348_SPI_MSG_DATA     0x40
-+#define SPI_BCM_6348_SPI_MSG_CTL      0x42
++#define SPI_BCM_6348_SPI_CMD          0x00    /* 16-bits register */
++#define SPI_BCM_6348_SPI_INT_STATUS   0x02
++#define SPI_BCM_6348_SPI_INT_MASK_ST  0x03
++#define SPI_BCM_6348_SPI_INT_MASK     0x04
++#define SPI_BCM_6348_SPI_ST           0x05
++#define SPI_BCM_6348_SPI_CLK_CFG      0x06
++#define SPI_BCM_6348_SPI_FILL_BYTE    0x07
++#define SPI_BCM_6348_SPI_MSG_TAIL     0x09
++#define SPI_BCM_6348_SPI_RX_TAIL      0x0b
++#define SPI_BCM_6348_SPI_MSG_CTL      0x40
++#define SPI_BCM_6348_SPI_MSG_DATA     0x41
 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE        0x3f
 +#define SPI_BCM_6348_SPI_RX_DATA      0x80
 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
@@ -244,10 +244,10 @@
 +#define SPI_MSG_TYPE_SHIFT            14
 +
 +/* Command */
-+#define SPI_CMD_NOOP                  0x01
-+#define SPI_CMD_SOFT_RESET            0x02
-+#define SPI_CMD_HARD_RESET            0x04
-+#define SPI_CMD_START_IMMEDIATE               0x08
++#define SPI_CMD_NOOP                  0x00
++#define SPI_CMD_SOFT_RESET            0x01
++#define SPI_CMD_HARD_RESET            0x02
++#define SPI_CMD_START_IMMEDIATE               0x03
 +#define SPI_CMD_COMMAND_SHIFT         0
 +#define SPI_CMD_COMMAND_MASK          0x000f
 +#define SPI_CMD_DEVICE_ID_SHIFT               4
@@ -847,7 +847,7 @@
 +
 +#define __GEN_SPI_RSET_BASE(__cpu, __rset)                            \
 +      case SPI_## __rset:                                             \
-+              return SPI_BCM_## __cpu ##_SPI_## __rset ##;
++              return SPI_BCM_## __cpu ##_SPI_## __rset;
 +
 +#define __GEN_SPI_RSET(__cpu)                                         \
 +      switch (reg) {                                                  \
@@ -919,12 +919,12 @@
  #include <board_bcm963xx.h>
  
  #define PFX   "board_bcm963xx: "
-@@ -943,6 +944,8 @@ int __init board_register_devices(void)
+@@ -933,6 +934,8 @@ int __init board_register_devices(void)
        if (board.num_spis)
                spi_register_board_info(board.spis, board.num_spis);
  
 +      bcm63xx_spi_register();
 +
        /* read base address of boot chip select (0) */
-       if (BCMCPU_IS_6345())
-               val = 0x1fc00000;
+       val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+       val &= MPI_CSBASE_BASE_MASK;