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[ar71xx] WRT160NL: more mtd parser cleanup
[openwrt.git] / target / linux / brcm47xx / patches-2.6.28 / 810-ssb-add-pmu-support.patch
diff --git a/target/linux/brcm47xx/patches-2.6.28/810-ssb-add-pmu-support.patch b/target/linux/brcm47xx/patches-2.6.28/810-ssb-add-pmu-support.patch
index 1c88b38..7ab70aa 100644 (file)
--- a/target/linux/brcm47xx/patches-2.6.28/810-ssb-add-pmu-support.patch
+++ b/target/linux/brcm47xx/patches-2.6.28/810-ssb-add-pmu-support.patch
@@ -1,7 +1,13 @@
-Index: linux-2.6.28.2/drivers/ssb/Makefile
-===================================================================
---- linux-2.6.28.2.orig/drivers/ssb/Makefile   2009-02-01 13:09:04.000000000 +0100
-+++ linux-2.6.28.2/drivers/ssb/Makefile        2009-02-01 13:09:31.000000000 +0100
+Sent to mainline on 2009 Feb 03.
+
+For further modifications, please use separate patch files. This simpifies
+keeping track of what is upstream and what is not. Thanks.
+
+--mb
+
+
+--- a/drivers/ssb/Makefile
++++ b/drivers/ssb/Makefile
 @@ -9,6 +9,7 @@ ssb-$(CONFIG_SSB_PCMCIAHOST)           += pcmcia.
  
  # built-in drivers
 @@ -9,6 +9,7 @@ ssb-$(CONFIG_SSB_PCMCIAHOST)           += pcmcia.
  
  # built-in drivers
@@ -10,11 +16,9 @@ Index: linux-2.6.28.2/drivers/ssb/Makefile
  ssb-$(CONFIG_SSB_DRIVER_MIPS)         += driver_mipscore.o
  ssb-$(CONFIG_SSB_DRIVER_EXTIF)                += driver_extif.o
  ssb-$(CONFIG_SSB_DRIVER_PCICORE)      += driver_pcicore.o
  ssb-$(CONFIG_SSB_DRIVER_MIPS)         += driver_mipscore.o
  ssb-$(CONFIG_SSB_DRIVER_EXTIF)                += driver_extif.o
  ssb-$(CONFIG_SSB_DRIVER_PCICORE)      += driver_pcicore.o
-Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
-===================================================================
---- /dev/null  1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c 2009-02-02 20:57:13.000000000 +0100
-@@ -0,0 +1,481 @@
+--- /dev/null
++++ b/drivers/ssb/driver_chipcommon_pmu.c
+@@ -0,0 +1,508 @@
 +/*
 + * Sonics Silicon Backplane
 + * Broadcom ChipCommon Power Management Unit driver
 +/*
 + * Sonics Silicon Backplane
 + * Broadcom ChipCommon Power Management Unit driver
@@ -119,15 +123,15 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
 +      switch (bus->chip_id) {
 +      case 0x4328:
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
 +      switch (bus->chip_id) {
 +      case 0x4328:
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
-+                            ~(1 << SSB_PLLRES_4328_BB_PLL_PU));
++                            ~(1 << SSB_PMURES_4328_BB_PLL_PU));
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
-+                            ~(1 << SSB_PLLRES_4328_BB_PLL_PU));
++                            ~(1 << SSB_PMURES_4328_BB_PLL_PU));
 +              break;
 +      case 0x5354:
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
 +              break;
 +      case 0x5354:
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
-+                            ~(1 << SSB_PLLRES_5354_BB_PLL_PU));
++                            ~(1 << SSB_PMURES_5354_BB_PLL_PU));
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
-+                            ~(1 << SSB_PLLRES_5354_BB_PLL_PU));
++                            ~(1 << SSB_PMURES_5354_BB_PLL_PU));
 +              break;
 +      default:
 +              SSB_WARN_ON(1);
 +              break;
 +      default:
 +              SSB_WARN_ON(1);
@@ -254,17 +258,15 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
 +      ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
 +                 (crystalfreq / 1000), (crystalfreq % 1000));
 +
 +      ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
 +                 (crystalfreq / 1000), (crystalfreq % 1000));
 +
-+WARN_ON(1); //TODO not fully implemented, yet.
-+return;
 +      /* First turn the PLL off. */
 +      switch (bus->chip_id) {
 +      case 0x4325:
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
 +      /* First turn the PLL off. */
 +      switch (bus->chip_id) {
 +      case 0x4325:
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
-+                            ~((1 << SSB_PLLRES_4325_BBPLL_PWRSW_PU) |
-+                              (1 << SSB_PLLRES_4325_HT_AVAIL)));
++                            ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
++                              (1 << SSB_PMURES_4325_HT_AVAIL)));
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
 +              chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
-+                            ~((1 << SSB_PLLRES_4325_BBPLL_PWRSW_PU) |
-+                              (1 << SSB_PLLRES_4325_HT_AVAIL)));
++                            ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
++                              (1 << SSB_PMURES_4325_HT_AVAIL)));
 +              /* Adjust the BBPLL to 2 on all channels later. */
 +              buffer_strength = 0x222222;
 +              break;
 +              /* Adjust the BBPLL to 2 on all channels later. */
 +              buffer_strength = 0x222222;
 +              break;
@@ -283,10 +285,39 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
 +
 +      /* Set p1div and p2div. */
 +      pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
 +
 +      /* Set p1div and p2div. */
 +      pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
-+      //TODO
++      pllctl &= ~(SSB_PMU1_PLLCTL0_P1DIV | SSB_PMU1_PLLCTL0_P2DIV);
++      pllctl |= ((u32)e->p1div << SSB_PMU1_PLLCTL0_P1DIV_SHIFT) & SSB_PMU1_PLLCTL0_P1DIV;
++      pllctl |= ((u32)e->p2div << SSB_PMU1_PLLCTL0_P2DIV_SHIFT) & SSB_PMU1_PLLCTL0_P2DIV;
 +      ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
 +
 +      ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
 +
-+      //TODO
++      /* Set ndiv int and ndiv mode */
++      pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL2);
++      pllctl &= ~(SSB_PMU1_PLLCTL2_NDIVINT | SSB_PMU1_PLLCTL2_NDIVMODE);
++      pllctl |= ((u32)e->ndiv_int << SSB_PMU1_PLLCTL2_NDIVINT_SHIFT) & SSB_PMU1_PLLCTL2_NDIVINT;
++      pllctl |= (1 << SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT) & SSB_PMU1_PLLCTL2_NDIVMODE;
++      ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, pllctl);
++
++      /* Set ndiv frac */
++      pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL3);
++      pllctl &= ~SSB_PMU1_PLLCTL3_NDIVFRAC;
++      pllctl |= ((u32)e->ndiv_frac << SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT) & SSB_PMU1_PLLCTL3_NDIVFRAC;
++      ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, pllctl);
++
++      /* Change the drive strength, if required. */
++      if (buffer_strength) {
++              pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL5);
++              pllctl &= ~SSB_PMU1_PLLCTL5_CLKDRV;
++              pllctl |= (buffer_strength << SSB_PMU1_PLLCTL5_CLKDRV_SHIFT) & SSB_PMU1_PLLCTL5_CLKDRV;
++              ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, pllctl);
++      }
++
++      /* Tune the crystalfreq and the divisor. */
++      pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
++      pmuctl &= ~(SSB_CHIPCO_PMU_CTL_ILP_DIV | SSB_CHIPCO_PMU_CTL_XTALFREQ);
++      pmuctl |= ((((u32)e->freq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
++                      & SSB_CHIPCO_PMU_CTL_ILP_DIV;
++      pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
++      chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
 +}
 +
 +static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
 +}
 +
 +static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
@@ -332,51 +363,51 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
 +};
 +
 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4328a0[] = {
 +};
 +
 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4328a0[] = {
-+      { .resource = SSB_PLLRES_4328_EXT_SWITCHER_PWM,         .updown = 0x0101, },
-+      { .resource = SSB_PLLRES_4328_BB_SWITCHER_PWM,          .updown = 0x1F01, },
-+      { .resource = SSB_PLLRES_4328_BB_SWITCHER_BURST,        .updown = 0x010F, },
-+      { .resource = SSB_PLLRES_4328_BB_EXT_SWITCHER_BURST,    .updown = 0x0101, },
-+      { .resource = SSB_PLLRES_4328_ILP_REQUEST,              .updown = 0x0202, },
-+      { .resource = SSB_PLLRES_4328_RADIO_SWITCHER_PWM,       .updown = 0x0F01, },
-+      { .resource = SSB_PLLRES_4328_RADIO_SWITCHER_BURST,     .updown = 0x0F01, },
-+      { .resource = SSB_PLLRES_4328_ROM_SWITCH,               .updown = 0x0101, },
-+      { .resource = SSB_PLLRES_4328_PA_REF_LDO,               .updown = 0x0F01, },
-+      { .resource = SSB_PLLRES_4328_RADIO_LDO,                .updown = 0x0F01, },
-+      { .resource = SSB_PLLRES_4328_AFE_LDO,                  .updown = 0x0F01, },
-+      { .resource = SSB_PLLRES_4328_PLL_LDO,                  .updown = 0x0F01, },
-+      { .resource = SSB_PLLRES_4328_BG_FILTBYP,               .updown = 0x0101, },
-+      { .resource = SSB_PLLRES_4328_TX_FILTBYP,               .updown = 0x0101, },
-+      { .resource = SSB_PLLRES_4328_RX_FILTBYP,               .updown = 0x0101, },
-+      { .resource = SSB_PLLRES_4328_XTAL_PU,                  .updown = 0x0101, },
-+      { .resource = SSB_PLLRES_4328_XTAL_EN,                  .updown = 0xA001, },
-+      { .resource = SSB_PLLRES_4328_BB_PLL_FILTBYP,           .updown = 0x0101, },
-+      { .resource = SSB_PLLRES_4328_RF_PLL_FILTBYP,           .updown = 0x0101, },
-+      { .resource = SSB_PLLRES_4328_BB_PLL_PU,                .updown = 0x0701, },
++      { .resource = SSB_PMURES_4328_EXT_SWITCHER_PWM,         .updown = 0x0101, },
++      { .resource = SSB_PMURES_4328_BB_SWITCHER_PWM,          .updown = 0x1F01, },
++      { .resource = SSB_PMURES_4328_BB_SWITCHER_BURST,        .updown = 0x010F, },
++      { .resource = SSB_PMURES_4328_BB_EXT_SWITCHER_BURST,    .updown = 0x0101, },
++      { .resource = SSB_PMURES_4328_ILP_REQUEST,              .updown = 0x0202, },
++      { .resource = SSB_PMURES_4328_RADIO_SWITCHER_PWM,       .updown = 0x0F01, },
++      { .resource = SSB_PMURES_4328_RADIO_SWITCHER_BURST,     .updown = 0x0F01, },
++      { .resource = SSB_PMURES_4328_ROM_SWITCH,               .updown = 0x0101, },
++      { .resource = SSB_PMURES_4328_PA_REF_LDO,               .updown = 0x0F01, },
++      { .resource = SSB_PMURES_4328_RADIO_LDO,                .updown = 0x0F01, },
++      { .resource = SSB_PMURES_4328_AFE_LDO,                  .updown = 0x0F01, },
++      { .resource = SSB_PMURES_4328_PLL_LDO,                  .updown = 0x0F01, },
++      { .resource = SSB_PMURES_4328_BG_FILTBYP,               .updown = 0x0101, },
++      { .resource = SSB_PMURES_4328_TX_FILTBYP,               .updown = 0x0101, },
++      { .resource = SSB_PMURES_4328_RX_FILTBYP,               .updown = 0x0101, },
++      { .resource = SSB_PMURES_4328_XTAL_PU,                  .updown = 0x0101, },
++      { .resource = SSB_PMURES_4328_XTAL_EN,                  .updown = 0xA001, },
++      { .resource = SSB_PMURES_4328_BB_PLL_FILTBYP,           .updown = 0x0101, },
++      { .resource = SSB_PMURES_4328_RF_PLL_FILTBYP,           .updown = 0x0101, },
++      { .resource = SSB_PMURES_4328_BB_PLL_PU,                .updown = 0x0701, },
 +};
 +
 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4328a0[] = {
 +      {
 +              /* Adjust ILP Request to avoid forcing EXT/BB into burst mode. */
 +};
 +
 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4328a0[] = {
 +      {
 +              /* Adjust ILP Request to avoid forcing EXT/BB into burst mode. */
-+              .resource = SSB_PLLRES_4328_ILP_REQUEST,
++              .resource = SSB_PMURES_4328_ILP_REQUEST,
 +              .task = PMU_RES_DEP_SET,
 +              .task = PMU_RES_DEP_SET,
-+              .depend = ((1 << SSB_PLLRES_4328_EXT_SWITCHER_PWM) |
-+                         (1 << SSB_PLLRES_4328_BB_SWITCHER_PWM)),
++              .depend = ((1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
++                         (1 << SSB_PMURES_4328_BB_SWITCHER_PWM)),
 +      },
 +};
 +
 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4325a0[] = {
 +      },
 +};
 +
 +static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4325a0[] = {
-+      { .resource = SSB_PLLRES_4325_XTAL_PU,                  .updown = 0x1501, },
++      { .resource = SSB_PMURES_4325_XTAL_PU,                  .updown = 0x1501, },
 +};
 +
 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4325a0[] = {
 +      {
 +              /* Adjust HT-Available dependencies. */
 +};
 +
 +static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4325a0[] = {
 +      {
 +              /* Adjust HT-Available dependencies. */
-+              .resource = SSB_PLLRES_4325_HT_AVAIL,
++              .resource = SSB_PMURES_4325_HT_AVAIL,
 +              .task = PMU_RES_DEP_ADD,
 +              .task = PMU_RES_DEP_ADD,
-+              .depend = ((1 << SSB_PLLRES_4325_RX_PWRSW_PU) |
-+                         (1 << SSB_PLLRES_4325_TX_PWRSW_PU) |
-+                         (1 << SSB_PLLRES_4325_LOGEN_PWRSW_PU) |
-+                         (1 << SSB_PLLRES_4325_AFE_PWRSW_PU)),
++              .depend = ((1 << SSB_PMURES_4325_RX_PWRSW_PU) |
++                         (1 << SSB_PMURES_4325_TX_PWRSW_PU) |
++                         (1 << SSB_PMURES_4325_LOGEN_PWRSW_PU) |
++                         (1 << SSB_PMURES_4325_AFE_PWRSW_PU)),
 +      },
 +};
 +
 +      },
 +};
 +
@@ -399,11 +430,11 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
 +              break;
 +      case 0x4325:
 +              /* Power OTP down later. */
 +              break;
 +      case 0x4325:
 +              /* Power OTP down later. */
-+              min_msk = (1 << SSB_PLLRES_4325_CBUCK_BURST) |
-+                        (1 << SSB_PLLRES_4325_LNLDO2_PU);
++              min_msk = (1 << SSB_PMURES_4325_CBUCK_BURST) |
++                        (1 << SSB_PMURES_4325_LNLDO2_PU);
 +              if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) &
 +                  SSB_CHIPCO_CHST_4325_PMUTOP_2B)
 +              if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) &
 +                  SSB_CHIPCO_CHST_4325_PMUTOP_2B)
-+                      min_msk |= (1 << SSB_PLLRES_4325_CLDO_CBUCK_BURST);
++                      min_msk |= (1 << SSB_PMURES_4325_CLDO_CBUCK_BURST);
 +              /* The PLL may turn on, if it decides so. */
 +              max_msk = 0xFFFFF;
 +              updown_tab = pmu_res_updown_tab_4325a0;
 +              /* The PLL may turn on, if it decides so. */
 +              max_msk = 0xFFFFF;
 +              updown_tab = pmu_res_updown_tab_4325a0;
@@ -412,9 +443,9 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
 +              depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4325a0);
 +              break;
 +      case 0x4328:
 +              depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4325a0);
 +              break;
 +      case 0x4328:
-+              min_msk = (1 << SSB_PLLRES_4328_EXT_SWITCHER_PWM) |
-+                        (1 << SSB_PLLRES_4328_BB_SWITCHER_PWM) |
-+                        (1 << SSB_PLLRES_4328_XTAL_EN);
++              min_msk = (1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
++                        (1 << SSB_PMURES_4328_BB_SWITCHER_PWM) |
++                        (1 << SSB_PMURES_4328_XTAL_EN);
 +              /* The PLL may turn on, if it decides so. */
 +              max_msk = 0xFFFFF;
 +              updown_tab = pmu_res_updown_tab_4328a0;
 +              /* The PLL may turn on, if it decides so. */
 +              max_msk = 0xFFFFF;
 +              updown_tab = pmu_res_updown_tab_4328a0;
@@ -496,10 +527,8 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon_pmu.c
 +      ssb_pmu_pll_init(cc);
 +      ssb_pmu_resources_init(cc);
 +}
 +      ssb_pmu_pll_init(cc);
 +      ssb_pmu_resources_init(cc);
 +}
-Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon.c
-===================================================================
---- linux-2.6.28.2.orig/drivers/ssb/driver_chipcommon.c        2009-02-01 13:07:03.000000000 +0100
-+++ linux-2.6.28.2/drivers/ssb/driver_chipcommon.c     2009-02-01 13:47:17.000000000 +0100
+--- a/drivers/ssb/driver_chipcommon.c
++++ b/drivers/ssb/driver_chipcommon.c
 @@ -26,19 +26,6 @@ enum ssb_clksrc {
  };
  
 @@ -26,19 +26,6 @@ enum ssb_clksrc {
  };
  
@@ -528,10 +557,8 @@ Index: linux-2.6.28.2/drivers/ssb/driver_chipcommon.c
        chipco_powercontrol_init(cc);
        ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
        calc_fast_powerup_delay(cc);
        chipco_powercontrol_init(cc);
        ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
        calc_fast_powerup_delay(cc);
-Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
-===================================================================
---- linux-2.6.28.2.orig/include/linux/ssb/ssb_driver_chipcommon.h      2009-02-01 13:22:59.000000000 +0100
-+++ linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h   2009-02-01 21:09:37.000000000 +0100
+--- a/include/linux/ssb/ssb_driver_chipcommon.h
++++ b/include/linux/ssb/ssb_driver_chipcommon.h
 @@ -181,6 +181,16 @@
  #define SSB_CHIPCO_PROG_WAITCNT               0x0124
  #define SSB_CHIPCO_FLASH_CFG          0x0128
 @@ -181,6 +181,16 @@
  #define SSB_CHIPCO_PROG_WAITCNT               0x0124
  #define SSB_CHIPCO_FLASH_CFG          0x0128
@@ -549,7 +576,7 @@ Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
  #define SSB_CHIPCO_UART0_DATA         0x0300
  #define SSB_CHIPCO_UART0_IMR          0x0304
  #define SSB_CHIPCO_UART0_FCR          0x0308
  #define SSB_CHIPCO_UART0_DATA         0x0300
  #define SSB_CHIPCO_UART0_IMR          0x0304
  #define SSB_CHIPCO_UART0_FCR          0x0308
-@@ -197,6 +207,172 @@
+@@ -197,6 +207,196 @@
  #define SSB_CHIPCO_UART1_LSR          0x0414
  #define SSB_CHIPCO_UART1_MSR          0x0418
  #define SSB_CHIPCO_UART1_SCRATCH      0x041C
  #define SSB_CHIPCO_UART1_LSR          0x0414
  #define SSB_CHIPCO_UART1_MSR          0x0418
  #define SSB_CHIPCO_UART1_SCRATCH      0x041C
@@ -613,96 +640,120 @@ Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
 +
 +/* PMU rev 1 PLL registers */
 +#define SSB_PMU1_PLLCTL0                      0
 +
 +/* PMU rev 1 PLL registers */
 +#define SSB_PMU1_PLLCTL0                      0
++#define  SSB_PMU1_PLLCTL0_P1DIV                       0x00F00000 /* P1 div */
++#define  SSB_PMU1_PLLCTL0_P1DIV_SHIFT         20
++#define  SSB_PMU1_PLLCTL0_P2DIV                       0x0F000000 /* P2 div */
++#define  SSB_PMU1_PLLCTL0_P2DIV_SHIFT         24
 +#define SSB_PMU1_PLLCTL1                      1
 +#define SSB_PMU1_PLLCTL1                      1
++#define  SSB_PMU1_PLLCTL1_M1DIV                       0x000000FF /* M1 div */
++#define  SSB_PMU1_PLLCTL1_M1DIV_SHIFT         0
++#define  SSB_PMU1_PLLCTL1_M2DIV                       0x0000FF00 /* M2 div */
++#define  SSB_PMU1_PLLCTL1_M2DIV_SHIFT         8
++#define  SSB_PMU1_PLLCTL1_M3DIV                       0x00FF0000 /* M3 div */
++#define  SSB_PMU1_PLLCTL1_M3DIV_SHIFT         16
++#define  SSB_PMU1_PLLCTL1_M4DIV                       0xFF000000 /* M4 div */
++#define  SSB_PMU1_PLLCTL1_M4DIV_SHIFT         24
 +#define SSB_PMU1_PLLCTL2                      2
 +#define SSB_PMU1_PLLCTL2                      2
++#define  SSB_PMU1_PLLCTL2_M5DIV                       0x000000FF /* M5 div */
++#define  SSB_PMU1_PLLCTL2_M5DIV_SHIFT         0
++#define  SSB_PMU1_PLLCTL2_M6DIV                       0x0000FF00 /* M6 div */
++#define  SSB_PMU1_PLLCTL2_M6DIV_SHIFT         8
++#define  SSB_PMU1_PLLCTL2_NDIVMODE            0x000E0000 /* NDIV mode */
++#define  SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT      17
++#define  SSB_PMU1_PLLCTL2_NDIVINT             0x1FF00000 /* NDIV int */
++#define  SSB_PMU1_PLLCTL2_NDIVINT_SHIFT               20
 +#define SSB_PMU1_PLLCTL3                      3
 +#define SSB_PMU1_PLLCTL3                      3
++#define  SSB_PMU1_PLLCTL3_NDIVFRAC            0x00FFFFFF /* NDIV frac */
++#define  SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT      0
 +#define SSB_PMU1_PLLCTL4                      4
 +#define SSB_PMU1_PLLCTL5                      5
 +#define SSB_PMU1_PLLCTL4                      4
 +#define SSB_PMU1_PLLCTL5                      5
++#define  SSB_PMU1_PLLCTL5_CLKDRV              0xFFFFFF00 /* clk drv */
++#define  SSB_PMU1_PLLCTL5_CLKDRV_SHIFT                8
 +
 +/* BCM4312 PLL resource numbers. */
 +
 +/* BCM4312 PLL resource numbers. */
-+#define SSB_PLLRES_4312_SWITCHER_BURST                0
-+#define SSB_PLLRES_4312_SWITCHER_PWM          1
-+#define SSB_PLLRES_4312_PA_REF_LDO            2
-+#define SSB_PLLRES_4312_CORE_LDO_BURST                3
-+#define SSB_PLLRES_4312_CORE_LDO_PWM          4
-+#define SSB_PLLRES_4312_RADIO_LDO             5
-+#define SSB_PLLRES_4312_ILP_REQUEST           6
-+#define SSB_PLLRES_4312_BG_FILTBYP            7
-+#define SSB_PLLRES_4312_TX_FILTBYP            8
-+#define SSB_PLLRES_4312_RX_FILTBYP            9
-+#define SSB_PLLRES_4312_XTAL_PU                       10
-+#define SSB_PLLRES_4312_ALP_AVAIL             11
-+#define SSB_PLLRES_4312_BB_PLL_FILTBYP                12
-+#define SSB_PLLRES_4312_RF_PLL_FILTBYP                13
-+#define SSB_PLLRES_4312_HT_AVAIL              14
++#define SSB_PMURES_4312_SWITCHER_BURST                0
++#define SSB_PMURES_4312_SWITCHER_PWM          1
++#define SSB_PMURES_4312_PA_REF_LDO            2
++#define SSB_PMURES_4312_CORE_LDO_BURST                3
++#define SSB_PMURES_4312_CORE_LDO_PWM          4
++#define SSB_PMURES_4312_RADIO_LDO             5
++#define SSB_PMURES_4312_ILP_REQUEST           6
++#define SSB_PMURES_4312_BG_FILTBYP            7
++#define SSB_PMURES_4312_TX_FILTBYP            8
++#define SSB_PMURES_4312_RX_FILTBYP            9
++#define SSB_PMURES_4312_XTAL_PU                       10
++#define SSB_PMURES_4312_ALP_AVAIL             11
++#define SSB_PMURES_4312_BB_PLL_FILTBYP                12
++#define SSB_PMURES_4312_RF_PLL_FILTBYP                13
++#define SSB_PMURES_4312_HT_AVAIL              14
 +
 +/* BCM4325 PLL resource numbers. */
 +
 +/* BCM4325 PLL resource numbers. */
-+#define SSB_PLLRES_4325_BUCK_BOOST_BURST      0
-+#define SSB_PLLRES_4325_CBUCK_BURST           1
-+#define SSB_PLLRES_4325_CBUCK_PWM             2
-+#define SSB_PLLRES_4325_CLDO_CBUCK_BURST      3
-+#define SSB_PLLRES_4325_CLDO_CBUCK_PWM                4
-+#define SSB_PLLRES_4325_BUCK_BOOST_PWM                5
-+#define SSB_PLLRES_4325_ILP_REQUEST           6
-+#define SSB_PLLRES_4325_ABUCK_BURST           7
-+#define SSB_PLLRES_4325_ABUCK_PWM             8
-+#define SSB_PLLRES_4325_LNLDO1_PU             9
-+#define SSB_PLLRES_4325_LNLDO2_PU             10
-+#define SSB_PLLRES_4325_LNLDO3_PU             11
-+#define SSB_PLLRES_4325_LNLDO4_PU             12
-+#define SSB_PLLRES_4325_XTAL_PU                       13
-+#define SSB_PLLRES_4325_ALP_AVAIL             14
-+#define SSB_PLLRES_4325_RX_PWRSW_PU           15
-+#define SSB_PLLRES_4325_TX_PWRSW_PU           16
-+#define SSB_PLLRES_4325_RFPLL_PWRSW_PU                17
-+#define SSB_PLLRES_4325_LOGEN_PWRSW_PU                18
-+#define SSB_PLLRES_4325_AFE_PWRSW_PU          19
-+#define SSB_PLLRES_4325_BBPLL_PWRSW_PU                20
-+#define SSB_PLLRES_4325_HT_AVAIL              21
++#define SSB_PMURES_4325_BUCK_BOOST_BURST      0
++#define SSB_PMURES_4325_CBUCK_BURST           1
++#define SSB_PMURES_4325_CBUCK_PWM             2
++#define SSB_PMURES_4325_CLDO_CBUCK_BURST      3
++#define SSB_PMURES_4325_CLDO_CBUCK_PWM                4
++#define SSB_PMURES_4325_BUCK_BOOST_PWM                5
++#define SSB_PMURES_4325_ILP_REQUEST           6
++#define SSB_PMURES_4325_ABUCK_BURST           7
++#define SSB_PMURES_4325_ABUCK_PWM             8
++#define SSB_PMURES_4325_LNLDO1_PU             9
++#define SSB_PMURES_4325_LNLDO2_PU             10
++#define SSB_PMURES_4325_LNLDO3_PU             11
++#define SSB_PMURES_4325_LNLDO4_PU             12
++#define SSB_PMURES_4325_XTAL_PU                       13
++#define SSB_PMURES_4325_ALP_AVAIL             14
++#define SSB_PMURES_4325_RX_PWRSW_PU           15
++#define SSB_PMURES_4325_TX_PWRSW_PU           16
++#define SSB_PMURES_4325_RFPLL_PWRSW_PU                17
++#define SSB_PMURES_4325_LOGEN_PWRSW_PU                18
++#define SSB_PMURES_4325_AFE_PWRSW_PU          19
++#define SSB_PMURES_4325_BBPLL_PWRSW_PU                20
++#define SSB_PMURES_4325_HT_AVAIL              21
 +
 +/* BCM4328 PLL resource numbers. */
 +
 +/* BCM4328 PLL resource numbers. */
-+#define SSB_PLLRES_4328_EXT_SWITCHER_PWM      0
-+#define SSB_PLLRES_4328_BB_SWITCHER_PWM               1
-+#define SSB_PLLRES_4328_BB_SWITCHER_BURST     2
-+#define SSB_PLLRES_4328_BB_EXT_SWITCHER_BURST 3
-+#define SSB_PLLRES_4328_ILP_REQUEST           4
-+#define SSB_PLLRES_4328_RADIO_SWITCHER_PWM    5
-+#define SSB_PLLRES_4328_RADIO_SWITCHER_BURST  6
-+#define SSB_PLLRES_4328_ROM_SWITCH            7
-+#define SSB_PLLRES_4328_PA_REF_LDO            8
-+#define SSB_PLLRES_4328_RADIO_LDO             9
-+#define SSB_PLLRES_4328_AFE_LDO                       10
-+#define SSB_PLLRES_4328_PLL_LDO                       11
-+#define SSB_PLLRES_4328_BG_FILTBYP            12
-+#define SSB_PLLRES_4328_TX_FILTBYP            13
-+#define SSB_PLLRES_4328_RX_FILTBYP            14
-+#define SSB_PLLRES_4328_XTAL_PU                       15
-+#define SSB_PLLRES_4328_XTAL_EN                       16
-+#define SSB_PLLRES_4328_BB_PLL_FILTBYP                17
-+#define SSB_PLLRES_4328_RF_PLL_FILTBYP                18
-+#define SSB_PLLRES_4328_BB_PLL_PU             19
++#define SSB_PMURES_4328_EXT_SWITCHER_PWM      0
++#define SSB_PMURES_4328_BB_SWITCHER_PWM               1
++#define SSB_PMURES_4328_BB_SWITCHER_BURST     2
++#define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST 3
++#define SSB_PMURES_4328_ILP_REQUEST           4
++#define SSB_PMURES_4328_RADIO_SWITCHER_PWM    5
++#define SSB_PMURES_4328_RADIO_SWITCHER_BURST  6
++#define SSB_PMURES_4328_ROM_SWITCH            7
++#define SSB_PMURES_4328_PA_REF_LDO            8
++#define SSB_PMURES_4328_RADIO_LDO             9
++#define SSB_PMURES_4328_AFE_LDO                       10
++#define SSB_PMURES_4328_PLL_LDO                       11
++#define SSB_PMURES_4328_BG_FILTBYP            12
++#define SSB_PMURES_4328_TX_FILTBYP            13
++#define SSB_PMURES_4328_RX_FILTBYP            14
++#define SSB_PMURES_4328_XTAL_PU                       15
++#define SSB_PMURES_4328_XTAL_EN                       16
++#define SSB_PMURES_4328_BB_PLL_FILTBYP                17
++#define SSB_PMURES_4328_RF_PLL_FILTBYP                18
++#define SSB_PMURES_4328_BB_PLL_PU             19
 +
 +/* BCM5354 PLL resource numbers. */
 +
 +/* BCM5354 PLL resource numbers. */
-+#define SSB_PLLRES_5354_EXT_SWITCHER_PWM      0
-+#define SSB_PLLRES_5354_BB_SWITCHER_PWM               1
-+#define SSB_PLLRES_5354_BB_SWITCHER_BURST     2
-+#define SSB_PLLRES_5354_BB_EXT_SWITCHER_BURST 3
-+#define SSB_PLLRES_5354_ILP_REQUEST           4
-+#define SSB_PLLRES_5354_RADIO_SWITCHER_PWM    5
-+#define SSB_PLLRES_5354_RADIO_SWITCHER_BURST  6
-+#define SSB_PLLRES_5354_ROM_SWITCH            7
-+#define SSB_PLLRES_5354_PA_REF_LDO            8
-+#define SSB_PLLRES_5354_RADIO_LDO             9
-+#define SSB_PLLRES_5354_AFE_LDO                       10
-+#define SSB_PLLRES_5354_PLL_LDO                       11
-+#define SSB_PLLRES_5354_BG_FILTBYP            12
-+#define SSB_PLLRES_5354_TX_FILTBYP            13
-+#define SSB_PLLRES_5354_RX_FILTBYP            14
-+#define SSB_PLLRES_5354_XTAL_PU                       15
-+#define SSB_PLLRES_5354_XTAL_EN                       16
-+#define SSB_PLLRES_5354_BB_PLL_FILTBYP                17
-+#define SSB_PLLRES_5354_RF_PLL_FILTBYP                18
-+#define SSB_PLLRES_5354_BB_PLL_PU             19
++#define SSB_PMURES_5354_EXT_SWITCHER_PWM      0
++#define SSB_PMURES_5354_BB_SWITCHER_PWM               1
++#define SSB_PMURES_5354_BB_SWITCHER_BURST     2
++#define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST 3
++#define SSB_PMURES_5354_ILP_REQUEST           4
++#define SSB_PMURES_5354_RADIO_SWITCHER_PWM    5
++#define SSB_PMURES_5354_RADIO_SWITCHER_BURST  6
++#define SSB_PMURES_5354_ROM_SWITCH            7
++#define SSB_PMURES_5354_PA_REF_LDO            8
++#define SSB_PMURES_5354_RADIO_LDO             9
++#define SSB_PMURES_5354_AFE_LDO                       10
++#define SSB_PMURES_5354_PLL_LDO                       11
++#define SSB_PMURES_5354_BG_FILTBYP            12
++#define SSB_PMURES_5354_TX_FILTBYP            13
++#define SSB_PMURES_5354_RX_FILTBYP            14
++#define SSB_PMURES_5354_XTAL_PU                       15
++#define SSB_PMURES_5354_XTAL_EN                       16
++#define SSB_PMURES_5354_BB_PLL_FILTBYP                17
++#define SSB_PMURES_5354_RF_PLL_FILTBYP                18
++#define SSB_PMURES_5354_BB_PLL_PU             19
 +
 +
 +
 +
 +
 +
@@ -722,7 +773,7 @@ Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
  
  
  
  
  
  
-@@ -353,11 +529,20 @@
+@@ -353,11 +553,20 @@
  struct ssb_device;
  struct ssb_serial_port;
  
  struct ssb_device;
  struct ssb_serial_port;
  
@@ -743,7 +794,7 @@ Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
  };
  
  static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
  };
  
  static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
-@@ -365,6 +550,17 @@ static inline bool ssb_chipco_available(
+@@ -365,6 +574,17 @@ static inline bool ssb_chipco_available(
        return (cc->dev != NULL);
  }
  
        return (cc->dev != NULL);
  }
  
@@ -761,7 +812,7 @@ Index: linux-2.6.28.2/include/linux/ssb/ssb_driver_chipcommon.h
  extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
  
  extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
  extern void ssb_chipcommon_init(struct ssb_chipcommon *cc);
  
  extern void ssb_chipco_suspend(struct ssb_chipcommon *cc);
-@@ -406,4 +602,8 @@ extern int ssb_chipco_serial_init(struct
+@@ -406,4 +626,8 @@ extern int ssb_chipco_serial_init(struct
                                  struct ssb_serial_port *ports);
  #endif /* CONFIG_SSB_SERIAL */
  
                                  struct ssb_serial_port *ports);
  #endif /* CONFIG_SSB_SERIAL */
  
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