#define ETH_FCS_LEN 4
#define AG71XX_DRV_NAME "ag71xx"
-#define AG71XX_DRV_VERSION "0.5.23"
+#define AG71XX_DRV_VERSION "0.5.25"
#define AG71XX_NAPI_WEIGHT 64
#define AG71XX_OOM_REFILL (1 + HZ/10)
};
struct ag71xx_mdio {
- struct mii_bus *mii_bus;
- int mii_irq[PHY_MAX_ADDR];
- void __iomem *mdio_base;
+ struct mii_bus *mii_bus;
+ int mii_irq[PHY_MAX_ADDR];
+ void __iomem *mdio_base;
+ struct ag71xx_mdio_platform_data *pdata;
};
struct ag71xx {
void __iomem *mac_base;
- void __iomem *mac_base2;
void __iomem *mii_ctrl;
spinlock_t lock;
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
- r = ag->mac_base + reg;
- __raw_writel(value, r);
- __raw_readl(r);
- break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
- r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+ r = ag->mac_base + reg;
__raw_writel(value, r);
- __raw_readl(r);
+
+ /* flush write */
+ (void) __raw_readl(r);
break;
default:
BUG();
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
- r = ag->mac_base + reg;
- ret = __raw_readl(r);
- break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
- r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+ r = ag->mac_base + reg;
ret = __raw_readl(r);
break;
default:
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
- r = ag->mac_base + reg;
- __raw_writel(__raw_readl(r) | mask, r);
- __raw_readl(r);
- break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
- r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+ r = ag->mac_base + reg;
__raw_writel(__raw_readl(r) | mask, r);
- __raw_readl(r);
+
+ /* flush write */
+ (void)__raw_readl(r);
break;
default:
BUG();
switch (reg) {
case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
- r = ag->mac_base + reg;
- __raw_writel(__raw_readl(r) & ~mask, r);
- __raw_readl(r);
- break;
case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
- r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
+ r = ag->mac_base + reg;
__raw_writel(__raw_readl(r) & ~mask, r);
- __raw_readl(r);
+
+ /* flush write */
+ (void) __raw_readl(r);
break;
default:
BUG();
return;
__raw_writel(value, ag->mii_ctrl);
+
+ /* flush write */
__raw_readl(ag->mii_ctrl);
}