final fix for BCM5354 USB cores, hopefully

[openwrt.git] / target / linux / brcm-2.4 / files / arch / mips / bcm947xx / pcibios.c

diff --git a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c
index 012009a..0e993d1 100644 (file)
--- a/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c
+++ b/target/linux/brcm-2.4/files/arch/mips/bcm947xx/pcibios.c
@@ -25,7 +25,6 @@
 
 #include <typedefs.h>
 #include <osl.h>
 
 #include <typedefs.h>
 #include <osl.h>

-#include <bcmutils.h>

 #include <sbconfig.h>
 #include <sbutils.h>
 #include <hndpci.h>
 #include <sbconfig.h>
 #include <sbutils.h>
 #include <hndpci.h>


@@ -134,7 +133,7 @@ pcibios_init(void)
 {
        ulong flags;
 
 {
        ulong flags;
 

-       if (!(sbh = sb_kattach()))
+       if (!(sbh = sb_kattach(SB_OSH)))

                panic("sb_kattach failed");
        spin_lock_init(&sbh_lock);
 
                panic("sb_kattach failed");
        spin_lock_init(&sbh_lock);
 


@@ -143,6 +142,7 @@ pcibios_init(void)
        spin_unlock_irqrestore(&sbh_lock, flags);
 
        set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
        spin_unlock_irqrestore(&sbh_lock, flags);
 
        set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));

+       mdelay(300); /* workaround for atheros cards */

 
        /* Scan the SB bus */
        pci_scan_bus(0, &pcibios_ops, NULL);
 
        /* Scan the SB bus */
        pci_scan_bus(0, &pcibios_ops, NULL);


@@ -292,6 +292,7 @@ pcibios_enable_device(struct pci_dev *dev, int mask)
         * after calling pcibios_enable_device().
         */
        if (sb_coreid(sbh) == SB_USB) {
         * after calling pcibios_enable_device().
         */
        if (sb_coreid(sbh) == SB_USB) {

+               printk(KERN_INFO "SB USB 1.1 init\n");

                sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
                sb_core_reset(sbh, 1 << 29, 0);
        }
                sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
                sb_core_reset(sbh, 1 << 29, 0);
        }


@@ -306,11 +307,39 @@ pcibios_enable_device(struct pci_dev *dev, int mask)
         *    phy components out of reset.
         */
        else if (sb_coreid(sbh) == SB_USB20H) {
         *    phy components out of reset.
         */
        else if (sb_coreid(sbh) == SB_USB20H) {

+               
+               uint corerev = sb_corerev(sbh);
+
+               printk(KERN_INFO "SB USB20H init\n");
+               printk(KERN_INFO "SB COREREV: %d\n", corerev);
+               

                if (!sb_iscoreup(sbh)) {
                if (!sb_iscoreup(sbh)) {

+                                               
+                       printk(KERN_INFO "SB USB20H resetting\n");
+

                        sb_core_reset(sbh, 0, 0);
                        writel(0x7FF, (ulong)regs + 0x200);
                        udelay(1);
                }
                        sb_core_reset(sbh, 0, 0);
                        writel(0x7FF, (ulong)regs + 0x200);
                        udelay(1);
                }

+               /* PRxxxx: War for 5354 failures. */
+               if (corerev == 1 || corerev == 2) {
+                       uint32 tmp;
+
+                       /* Change Flush control reg */
+                       tmp = readl((uintptr)regs + 0x400);
+                       tmp &= ~8;
+                       writel(tmp, (uintptr)regs + 0x400);
+                       tmp = readl((uintptr)regs + 0x400);
+                       printk(KERN_INFO "USB20H fcr: 0x%x\n", tmp);
+
+                       /* Change Shim control reg */
+                       tmp = readl((uintptr)regs + 0x304);
+                       tmp &= ~0x100;
+                       writel(tmp, (uintptr)regs + 0x304);
+                       tmp = readl((uintptr)regs + 0x304);
+                       printk(KERN_INFO "USB20H shim cr: 0x%x\n", tmp);
+               }
+

        } else
                sb_core_reset(sbh, 0, 0);
 
        } else
                sb_core_reset(sbh, 0, 0);