#define IPU_BASE 0xB3080000
#define ETH_BASE 0xB3100000
-/*************************************************************************
- * CPM (Clock reset and Power control Management)
- *************************************************************************/
-#define CPM_CPCCR (CPM_BASE+0x00)
-#define CPM_CPPCR (CPM_BASE+0x10)
-#define CPM_I2SCDR (CPM_BASE+0x60)
-#define CPM_LPCDR (CPM_BASE+0x64)
-#define CPM_MSCCDR (CPM_BASE+0x68)
-#define CPM_UHCCDR (CPM_BASE+0x6C)
-#define CPM_SSICDR (CPM_BASE+0x74)
-
-#define CPM_LCR (CPM_BASE+0x04)
-#define CPM_CLKGR (CPM_BASE+0x20)
-#define CPM_SCR (CPM_BASE+0x24)
-
-#define CPM_HCR (CPM_BASE+0x30)
-#define CPM_HWFCR (CPM_BASE+0x34)
-#define CPM_HRCR (CPM_BASE+0x38)
-#define CPM_HWCR (CPM_BASE+0x3c)
-#define CPM_HWSR (CPM_BASE+0x40)
-#define CPM_HSPR (CPM_BASE+0x44)
-
-#define CPM_RSR (CPM_BASE+0x08)
-
-#define REG_CPM_CPCCR REG32(CPM_CPCCR)
-#define REG_CPM_CPPCR REG32(CPM_CPPCR)
-#define REG_CPM_I2SCDR REG32(CPM_I2SCDR)
-#define REG_CPM_LPCDR REG32(CPM_LPCDR)
-#define REG_CPM_MSCCDR REG32(CPM_MSCCDR)
-#define REG_CPM_UHCCDR REG32(CPM_UHCCDR)
-#define REG_CPM_SSICDR REG32(CPM_SSICDR)
-
-#define REG_CPM_LCR REG32(CPM_LCR)
-#define REG_CPM_CLKGR REG32(CPM_CLKGR)
-#define REG_CPM_SCR REG32(CPM_SCR)
-#define REG_CPM_HCR REG32(CPM_HCR)
-#define REG_CPM_HWFCR REG32(CPM_HWFCR)
-#define REG_CPM_HRCR REG32(CPM_HRCR)
-#define REG_CPM_HWCR REG32(CPM_HWCR)
-#define REG_CPM_HWSR REG32(CPM_HWSR)
-#define REG_CPM_HSPR REG32(CPM_HSPR)
-
-#define REG_CPM_RSR REG32(CPM_RSR)
-
-/* Clock Control Register */
-#define CPM_CPCCR_I2CS (1 << 31)
-#define CPM_CPCCR_CLKOEN (1 << 30)
-#define CPM_CPCCR_UCS (1 << 29)
-#define CPM_CPCCR_UDIV_BIT 23
-#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT)
-#define CPM_CPCCR_CE (1 << 22)
-#define CPM_CPCCR_PCS (1 << 21)
-#define CPM_CPCCR_LDIV_BIT 16
-#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT)
-#define CPM_CPCCR_MDIV_BIT 12
-#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT)
-#define CPM_CPCCR_PDIV_BIT 8
-#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT)
-#define CPM_CPCCR_HDIV_BIT 4
-#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT)
-#define CPM_CPCCR_CDIV_BIT 0
-#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT)
-
-/* I2S Clock Divider Register */
-#define CPM_I2SCDR_I2SDIV_BIT 0
-#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT)
-
-/* LCD Pixel Clock Divider Register */
-#define CPM_LPCDR_PIXDIV_BIT 0
-#define CPM_LPCDR_PIXDIV_MASK (0x7ff << CPM_LPCDR_PIXDIV_BIT)
-
-/* MSC Clock Divider Register */
-#define CPM_MSCCDR_MSCDIV_BIT 0
-#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT)
-
-/* UHC Clock Divider Register */
-#define CPM_UHCCDR_UHCDIV_BIT 0
-#define CPM_UHCCDR_UHCDIV_MASK (0xf << CPM_UHCCDR_UHCDIV_BIT)
-
-/* SSI Clock Divider Register */
-#define CPM_SSICDR_SCS (1<<31) /* SSI clock source selection, 0:EXCLK, 1: PLL */
-#define CPM_SSICDR_SSIDIV_BIT 0
-#define CPM_SSICDR_SSIDIV_MASK (0xf << CPM_SSICDR_SSIDIV_BIT)
-
-/* PLL Control Register */
-#define CPM_CPPCR_PLLM_BIT 23
-#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT)
-#define CPM_CPPCR_PLLN_BIT 18
-#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT)
-#define CPM_CPPCR_PLLOD_BIT 16
-#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT)
-#define CPM_CPPCR_PLLS (1 << 10)
-#define CPM_CPPCR_PLLBP (1 << 9)
-#define CPM_CPPCR_PLLEN (1 << 8)
-#define CPM_CPPCR_PLLST_BIT 0
-#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT)
-
-/* Low Power Control Register */
-#define CPM_LCR_DOZE_DUTY_BIT 3
-#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
-#define CPM_LCR_DOZE_ON (1 << 2)
-#define CPM_LCR_LPM_BIT 0
-#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
- #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT)
- #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT)
-
-/* Clock Gate Register */
-#define CPM_CLKGR_UART1 (1 << 15)
-#define CPM_CLKGR_UHC (1 << 14)
-#define CPM_CLKGR_IPU (1 << 13)
-#define CPM_CLKGR_DMAC (1 << 12)
-#define CPM_CLKGR_UDC (1 << 11)
-#define CPM_CLKGR_LCD (1 << 10)
-#define CPM_CLKGR_CIM (1 << 9)
-#define CPM_CLKGR_SADC (1 << 8)
-#define CPM_CLKGR_MSC (1 << 7)
-#define CPM_CLKGR_AIC1 (1 << 6)
-#define CPM_CLKGR_AIC2 (1 << 5)
-#define CPM_CLKGR_SSI (1 << 4)
-#define CPM_CLKGR_I2C (1 << 3)
-#define CPM_CLKGR_RTC (1 << 2)
-#define CPM_CLKGR_TCU (1 << 1)
-#define CPM_CLKGR_UART0 (1 << 0)
-
-/* Sleep Control Register */
-#define CPM_SCR_O1ST_BIT 8
-#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
-#define CPM_SCR_USBPHY_ENABLE (1 << 6)
-#define CPM_SCR_OSC_ENABLE (1 << 4)
-
-/* Hibernate Control Register */
-#define CPM_HCR_PD (1 << 0)
-
-/* Wakeup Filter Counter Register in Hibernate Mode */
-#define CPM_HWFCR_TIME_BIT 0
-#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)
-
-/* Reset Counter Register in Hibernate Mode */
-#define CPM_HRCR_TIME_BIT 0
-#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)
-
-/* Wakeup Control Register in Hibernate Mode */
-#define CPM_HWCR_WLE_LOW (0 << 2)
-#define CPM_HWCR_WLE_HIGH (1 << 2)
-#define CPM_HWCR_PIN_WAKEUP (1 << 1)
-#define CPM_HWCR_RTC_WAKEUP (1 << 0)
-
-/* Wakeup Status Register in Hibernate Mode */
-#define CPM_HWSR_WSR_PIN (1 << 1)
-#define CPM_HWSR_WSR_RTC (1 << 0)
-
-/* Reset Status Register */
-#define CPM_RSR_HR (1 << 2)
-#define CPM_RSR_WR (1 << 1)
-#define CPM_RSR_PR (1 << 0)
-
/*************************************************************************
* UART
*************************************************************************/
projects / openwrt.git / blobdiff