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Register the second uart on tnetd7300 and fix the watchdog register for 7200/7300...
[openwrt.git]
/
target
/
linux
/
ar7-2.6
/
files
/
arch
/
mips
/
ar7
/
setup.c
diff --git
a/target/linux/ar7-2.6/files/arch/mips/ar7/setup.c
b/target/linux/ar7-2.6/files/arch/mips/ar7/setup.c
index
301abe0
..
4abc39f
100644
(file)
--- a/
target/linux/ar7-2.6/files/arch/mips/ar7/setup.c
+++ b/
target/linux/ar7-2.6/files/arch/mips/ar7/setup.c
@@
-49,15
+49,13
@@
static void ar7_machine_power_off(void);
static void ar7_machine_restart(char *command)
{
static void ar7_machine_restart(char *command)
{
-
volatile u32 *softres_reg = (u32 *)ioremap(AR7_REGS_RESET +
+ volatile u32 *softres_reg = (u32 *)ioremap(AR7_REGS_RESET +
AR7_RESET_SOFTWARE, 1);
AR7_RESET_SOFTWARE, 1);
- prom_printf("Reboot\n");
- *softres_reg = 1;
+ *softres_reg = 1;
}
static void ar7_machine_halt(void)
{
}
static void ar7_machine_halt(void)
{
- prom_printf("Halt\n");
while (1);
}
while (1);
}
@@
-65,20
+63,19
@@
static void ar7_machine_power_off(void)
{
volatile u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1);
u32 power_state = *power_reg | (3 << 30);
{
volatile u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1);
u32 power_state = *power_reg | (3 << 30);
- prom_printf("Power off\n");
- *power_reg = power_state;
+ *power_reg = power_state;
ar7_machine_halt();
}
const char *get_system_type(void)
{
ar7_machine_halt();
}
const char *get_system_type(void)
{
- u16 chip_id =
get
_chip_id();
+ u16 chip_id =
ar7
_chip_id();
switch (chip_id) {
switch (chip_id) {
- case
0x5
:
+ case
AR7_CHIP_7300
:
return "TI AR7 (TNETD7300)";
return "TI AR7 (TNETD7300)";
- case
0x18
:
+ case
AR7_CHIP_7100
:
return "TI AR7 (TNETD7100)";
return "TI AR7 (TNETD7100)";
- case
0x2b
:
+ case
AR7_CHIP_7200
:
return "TI AR7 (TNETD7200)";
default:
return "TI AR7 (Unknown)";
return "TI AR7 (TNETD7200)";
default:
return "TI AR7 (Unknown)";
@@
-95,6
+92,8
@@
static int __init ar7_init_console(void)
* given by the bios and saves the command line.
*/
* given by the bios and saves the command line.
*/
+extern void ar7_init_clocks(void);
+
void __init plat_mem_setup(void)
{
unsigned long io_base;
void __init plat_mem_setup(void)
{
unsigned long io_base;
@@
-110,11
+109,16
@@
void __init plat_mem_setup(void)
set_io_port_base(io_base);
prom_meminit();
set_io_port_base(io_base);
prom_meminit();
+#warning FIXME: clock initialisation
+ ar7_init_clocks();
ioport_resource.start = 0;
ioport_resource.end = ~0;
iomem_resource.start = 0;
iomem_resource.end = ~0;
ioport_resource.start = 0;
ioport_resource.end = ~0;
iomem_resource.start = 0;
iomem_resource.end = ~0;
+
+ printk("%s, ID: 0x%04x, Revision: 0x%02x\n", get_system_type(),
+ ar7_chip_id(), ar7_chip_rev());
}
console_initcall(ar7_init_console);
}
console_initcall(ar7_init_console);
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