ar71xx: add AR934X specific bootstrap and reset register bits

[openwrt.git] / target / linux / ar71xx / files / arch / mips / ar71xx / setup.c

diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c b/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
index 3a73229..c85b02c 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
@@ -28,9 +28,6 @@
 #include "devices.h"
 
 #define AR71XX_SYS_TYPE_LEN    64
 #include "devices.h"
 
 #define AR71XX_SYS_TYPE_LEN    64

-#define AR71XX_BASE_FREQ       40000000
-#define AR91XX_BASE_FREQ       5000000
-#define AR724X_BASE_FREQ       5000000

 
 u32 ar71xx_cpu_freq;
 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
 
 u32 ar71xx_cpu_freq;
 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);


@@ -41,12 +38,15 @@ EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
 u32 ar71xx_ddr_freq;
 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
 
 u32 ar71xx_ddr_freq;
 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
 

-u32 ar934x_ref_freq;
-EXPORT_SYMBOL_GPL(ar934x_ref_freq);
+u32 ar71xx_ref_freq;
+EXPORT_SYMBOL_GPL(ar71xx_ref_freq);

 
 enum ar71xx_soc_type ar71xx_soc;
 EXPORT_SYMBOL_GPL(ar71xx_soc);
 
 
 enum ar71xx_soc_type ar71xx_soc;
 EXPORT_SYMBOL_GPL(ar71xx_soc);
 

+u32 ar71xx_soc_rev;
+EXPORT_SYMBOL_GPL(ar71xx_soc_rev);
+

 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
 
 static void ar71xx_restart(char *command)
 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
 
 static void ar71xx_restart(char *command)


@@ -146,10 +146,16 @@ static void __init ar71xx_detect_sys_type(void)
                }
                break;
 
                }
                break;
 

-       case REV_ID_MAJOR_AR9341:
-               ar71xx_soc = AR71XX_SOC_AR9341;
-               chip = "9341";
-               rev = id & AR934X_REV_ID_REVISION_MASK;
+       case REV_ID_MAJOR_AR9330:
+               ar71xx_soc = AR71XX_SOC_AR9330;
+               chip = "9330";
+               rev = id & AR933X_REV_ID_REVISION_MASK;
+               break;
+
+       case REV_ID_MAJOR_AR9331:
+               ar71xx_soc = AR71XX_SOC_AR9331;
+               chip = "9331";
+               rev = id & AR933X_REV_ID_REVISION_MASK;

                break;
 
        case REV_ID_MAJOR_AR9342:
                break;
 
        case REV_ID_MAJOR_AR9342:


@@ -168,45 +174,78 @@ static void __init ar71xx_detect_sys_type(void)
                panic("ar71xx: unknown chip id:0x%08x\n", id);
        }
 
                panic("ar71xx: unknown chip id:0x%08x\n", id);
        }
 

+       ar71xx_soc_rev = rev;
+

        sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
        sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);

+       pr_info("SoC: %s\n", ar71xx_sys_type);

 }
 
 static void __init ar934x_detect_sys_frequency(void)
 {
 }
 
 static void __init ar934x_detect_sys_frequency(void)
 {

-       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, ref, postdiv;
+       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
+       u32 cpu_pll, ddr_pll;
+       u32 bootstrap;

 
 

-       if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
-               ref = (40 * 1000000);
+       bootstrap = ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
+       if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
+               ar71xx_ref_freq = 40 * 1000 * 1000;

        else
        else

-               ref = (25 * 1000000);
-
-       ar934x_ref_freq = ref;
-
-       clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
+               ar71xx_ref_freq = 25 * 1000 * 1000;

 
        pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
        out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
        ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
        nint    = AR934X_CPU_PLL_CFG_NINT_GET(pll);
        frac    = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
 
        pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
        out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
        ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
        nint    = AR934X_CPU_PLL_CFG_NINT_GET(pll);
        frac    = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);

-       postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
-       ar71xx_cpu_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1);

 
 

+       cpu_pll = nint * ar71xx_ref_freq / ref_div;
+       cpu_pll += frac * ar71xx_ref_freq / (ref_div * (2 << 6));
+       cpu_pll /= (1 << out_div);
+
+       pll = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CONFIG);

        out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
        ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
        nint    = AR934X_DDR_PLL_CFG_NINT_GET(pll);
        frac    = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
        out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
        ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
        nint    = AR934X_DDR_PLL_CFG_NINT_GET(pll);
        frac    = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);

-       postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
-       ar71xx_ddr_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1);

 
 

-       postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
+       ddr_pll = nint * ar71xx_ref_freq / ref_div;
+       ddr_pll += frac * ar71xx_ref_freq / (ref_div * (2 << 10));
+       ddr_pll /= (1 << out_div);
+
+       clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
+
+       if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) {
+               ar71xx_cpu_freq = ar71xx_ref_freq;
+       } else {
+               postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
+
+               if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
+                       ar71xx_cpu_freq = cpu_pll / (postdiv + 1);
+               else
+                       ar71xx_cpu_freq = ddr_pll / (postdiv + 1);
+       }

 
 

-       if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
-               ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1);
+       if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS) {
+               ar71xx_ddr_freq = ar71xx_ref_freq;

        } else {
        } else {

-               ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1);
+               postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
+
+               if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
+                       ar71xx_ddr_freq = ddr_pll / (postdiv + 1);
+               else
+                       ar71xx_ddr_freq = cpu_pll / (postdiv + 1);

        }
 
        }
 

+       if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS) {
+               ar71xx_ahb_freq = ar71xx_ref_freq;
+       } else {
+               postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
+
+               if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
+                       ar71xx_ahb_freq = ddr_pll / (postdiv + 1);
+               else
+                       ar71xx_ahb_freq = cpu_pll / (postdiv + 1);
+       }

 }
 
 static void __init ar91xx_detect_sys_frequency(void)
 }
 
 static void __init ar91xx_detect_sys_frequency(void)


@@ -215,10 +254,12 @@ static void __init ar91xx_detect_sys_frequency(void)
        u32 freq;
        u32 div;
 
        u32 freq;
        u32 div;
 

+       ar71xx_ref_freq = 5 * 1000 * 1000;
+

        pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 
        div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
        pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 
        div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);

-       freq = div * AR91XX_BASE_FREQ;
+       freq = div * ar71xx_ref_freq;

 
        ar71xx_cpu_freq = freq;
 
 
        ar71xx_cpu_freq = freq;
 


@@ -235,10 +276,12 @@ static void __init ar71xx_detect_sys_frequency(void)
        u32 freq;
        u32 div;
 
        u32 freq;
        u32 div;
 

+       ar71xx_ref_freq = 40 * 1000 * 1000;
+

        pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 
        div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
        pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 
        div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;

-       freq = div * AR71XX_BASE_FREQ;
+       freq = div * ar71xx_ref_freq;

 
        div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
        ar71xx_cpu_freq = freq / div;
 
        div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
        ar71xx_cpu_freq = freq / div;


@@ -256,10 +299,12 @@ static void __init ar724x_detect_sys_frequency(void)
        u32 freq;
        u32 div;
 
        u32 freq;
        u32 div;
 

+       ar71xx_ref_freq = 5 * 1000 * 1000;
+

        pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 
        div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
        pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 
        div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);

-       freq = div * AR724X_BASE_FREQ;
+       freq = div * ar71xx_ref_freq;

 
        div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
        freq *= div;
 
        div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
        freq *= div;


@@ -273,6 +318,56 @@ static void __init ar724x_detect_sys_frequency(void)
        ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 }
 
        ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 }
 

+static void __init ar933x_detect_sys_frequency(void)
+{
+       u32 clock_ctrl;
+       u32 cpu_config;
+       u32 freq;
+       u32 t;
+
+       t = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+       if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+               ar71xx_ref_freq = (40 * 1000 * 1000);
+       else
+               ar71xx_ref_freq = (25 * 1000 * 1000);
+
+       clock_ctrl = ar71xx_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
+       if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
+               ar71xx_cpu_freq = ar71xx_ref_freq;
+               ar71xx_ahb_freq = ar71xx_ref_freq;
+               ar71xx_ddr_freq = ar71xx_ref_freq;
+       } else {
+               cpu_config = ar71xx_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
+
+               t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+                   AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+               freq = ar71xx_ref_freq / t;
+
+               t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
+                   AR933X_PLL_CPU_CONFIG_NINT_MASK;
+               freq *= t;
+
+               t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+                   AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+               if (t == 0)
+                       t = 1;
+
+               freq >>= t;
+
+               t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
+                    AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
+               ar71xx_cpu_freq = freq / t;
+
+               t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
+                     AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
+               ar71xx_ddr_freq = freq / t;
+
+               t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
+                    AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
+               ar71xx_ahb_freq = freq / t;
+       }
+}
+

 static void __init detect_sys_frequency(void)
 {
        switch (ar71xx_soc) {
 static void __init detect_sys_frequency(void)
 {
        switch (ar71xx_soc) {


@@ -293,6 +388,11 @@ static void __init detect_sys_frequency(void)
                ar91xx_detect_sys_frequency();
                break;
 
                ar91xx_detect_sys_frequency();
                break;
 

+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               ar933x_detect_sys_frequency();
+               break;
+

        case AR71XX_SOC_AR9341:
        case AR71XX_SOC_AR9342:
        case AR71XX_SOC_AR9344:
        case AR71XX_SOC_AR9341:
        case AR71XX_SOC_AR9342:
        case AR71XX_SOC_AR9344:


@@ -335,12 +435,12 @@ void __init plat_mem_setup(void)
        ar71xx_detect_sys_type();
        detect_sys_frequency();
 
        ar71xx_detect_sys_type();
        detect_sys_frequency();
 

-       printk(KERN_INFO
-               "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
-               ar71xx_sys_type,
+       pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, "
+               "Ref:%u.%03uMHz",

                ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
                ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,

+               ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000,

                ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
                ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,

-               ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
+               ar71xx_ref_freq / 1000000, (ar71xx_ref_freq / 1000) % 1000);

 
        _machine_restart = ar71xx_restart;
        _machine_halt = ar71xx_halt;
 
        _machine_restart = ar71xx_restart;
        _machine_halt = ar71xx_halt;