-From 1306e6b6d72b2bc0b91bcdd15b1d982965210bda Mon Sep 17 00:00:00 2001
+From b9aae7ff9c6ca6864434882cce9c9c6fea88220b Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Mon, 5 Jan 2009 10:57:42 +0100
-Subject: [PATCH v2 03/11] ath9k: introduce bus specific cache size routine
+Subject: [PATCH v3 03/11] ath9k: introduce bus specific cache size routine
The PCI specific bus_read_cachesize routine won't work on the AHB bus,
we have to replace it with a suitable one later.
+Changes-licensed-under: ISC
+
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
---
{
u8 u8tmp;
-@@ -1338,7 +1338,7 @@ static int ath_init(u16 devid, struct at
+@@ -1340,7 +1340,7 @@ static int ath_init(u16 devid, struct at
* Cache line size is used to size and align various
* structures used to communicate with the hardware.
*/
/* XXX assert csz is non-zero */
sc->sc_cachelsz = csz << 2; /* convert to bytes */
-@@ -2529,6 +2529,10 @@ ath_rf_name(u16 rf_version)
+@@ -2538,6 +2538,10 @@ ath_rf_name(u16 rf_version)
return "????";
}
static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
void __iomem *mem;
-@@ -2617,6 +2621,7 @@ static int ath_pci_probe(struct pci_dev
+@@ -2626,6 +2630,7 @@ static int ath_pci_probe(struct pci_dev
sc->hw = hw;
sc->dev = &pdev->dev;
sc->mem = mem;