[brcm63xx] correct SPI register size

[openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h

diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
index cddf3a0..2db35ec 100644 (file)
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -28,6 +28,7 @@
 #include <linux/phy.h>
 #include <linux/skbuff.h>
 #include <linux/dma-mapping.h>
 #include <linux/phy.h>
 #include <linux/skbuff.h>
 #include <linux/dma-mapping.h>

+#include <linux/workqueue.h>

 
 #include <linux/bitops.h>
 
 
 #include <linux/bitops.h>
 


@@ -37,23 +38,17 @@
 #define ETH_FCS_LEN    4
 
 #define AG71XX_DRV_NAME                "ag71xx"
 #define ETH_FCS_LEN    4
 
 #define AG71XX_DRV_NAME                "ag71xx"

-#define AG71XX_DRV_VERSION     "0.5.8"
-
-#define AG71XX_NAPI_TX         1
+#define AG71XX_DRV_VERSION     "0.5.16"

 
 #define AG71XX_NAPI_WEIGHT     64
 
 #define AG71XX_NAPI_WEIGHT     64

+#define AG71XX_OOM_REFILL      (1 + HZ/10)

 
 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
 #define AG71XX_INT_TX  (AG71XX_INT_TX_PS)
 #define AG71XX_INT_RX  (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
 
 
 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
 #define AG71XX_INT_TX  (AG71XX_INT_TX_PS)
 #define AG71XX_INT_RX  (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
 

-#ifdef AG71XX_NAPI_TX

 #define AG71XX_INT_POLL        (AG71XX_INT_RX | AG71XX_INT_TX)
 #define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL)
 #define AG71XX_INT_POLL        (AG71XX_INT_RX | AG71XX_INT_TX)
 #define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL)

-#else
-#define AG71XX_INT_POLL        (AG71XX_INT_RX)
-#define AG71XX_INT_INIT        (AG71XX_INT_ERR | AG71XX_INT_POLL | AG71XX_INT_TX)
-#endif

 
 #define AG71XX_TX_FIFO_LEN     2048
 #define AG71XX_TX_MTU_LEN      1536
 
 #define AG71XX_TX_FIFO_LEN     2048
 #define AG71XX_TX_MTU_LEN      1536


@@ -90,6 +85,7 @@ struct ag71xx_desc {
 #define DESC_MORE      BIT(24)
 #define DESC_PKTLEN_M  0x1fff
        u32     next;
 #define DESC_MORE      BIT(24)
 #define DESC_PKTLEN_M  0x1fff
        u32     next;

+       u32     pad;

 };
 
 struct ag71xx_buf {
 };
 
 struct ag71xx_buf {


@@ -131,6 +127,9 @@ struct ag71xx {
        unsigned int            link;
        unsigned int            speed;
        int                     duplex;
        unsigned int            link;
        unsigned int            speed;
        int                     duplex;

+
+       struct work_struct      restart_work;
+       struct timer_list       oom_timer;

 };
 
 extern struct ethtool_ops ag71xx_ethtool_ops;
 };
 
 extern struct ethtool_ops ag71xx_ethtool_ops;


@@ -229,7 +228,7 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define FIFO_CFG4_DV           BIT(1)  /* RX_DV Event */
 #define FIFO_CFG4_FC           BIT(2)  /* False Carrier */
 #define FIFO_CFG4_CE           BIT(3)  /* Code Error */
 #define FIFO_CFG4_DV           BIT(1)  /* RX_DV Event */
 #define FIFO_CFG4_FC           BIT(2)  /* False Carrier */
 #define FIFO_CFG4_CE           BIT(3)  /* Code Error */

-#define FIFO_CFG4_CRC          BIT(4)  /* CRC error */
+#define FIFO_CFG4_CR           BIT(4)  /* CRC error */

 #define FIFO_CFG4_LM           BIT(5)  /* Length Mismatch */
 #define FIFO_CFG4_LO           BIT(6)  /* Length out of range */
 #define FIFO_CFG4_OK           BIT(7)  /* Packet is OK */
 #define FIFO_CFG4_LM           BIT(5)  /* Length Mismatch */
 #define FIFO_CFG4_LO           BIT(6)  /* Length out of range */
 #define FIFO_CFG4_OK           BIT(7)  /* Packet is OK */


@@ -260,6 +259,8 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
 #define FIFO_CFG5_VT           BIT(13) /* VLAN tag detected */
 #define FIFO_CFG5_LE           BIT(14) /* Long Event */
 #define FIFO_CFG5_FT           BIT(15) /* Frame Truncated */
 #define FIFO_CFG5_VT           BIT(13) /* VLAN tag detected */
 #define FIFO_CFG5_LE           BIT(14) /* Long Event */
 #define FIFO_CFG5_FT           BIT(15) /* Frame Truncated */

+#define FIFO_CFG5_16           BIT(16) /* unknown */
+#define FIFO_CFG5_17           BIT(17) /* unknown */

 #define FIFO_CFG5_SF           BIT(18) /* Short Frame */
 #define FIFO_CFG5_BM           BIT(19) /* Byte Mode */
 
 #define FIFO_CFG5_SF           BIT(18) /* Short Frame */
 #define FIFO_CFG5_BM           BIT(19) /* Byte Mode */