+ int retries;
+
+ retries = RAMIPS_MDIO_RETRY;
+ while (1) {
+ u32 t;
+
+ t = ramips_fe_rr(RAMIPS_MDIO_ACCESS);
+ if ((t & (0x1 << 31)) == 0)
+ return 0;
+
+ if (retries-- == 0)
+ break;
+
+ udelay(1);
+ }
+
+ dev_err(re->parent, "MDIO operation timed out\n");
+ return -ETIMEDOUT;
+}
+
+static int
+ramips_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
+{
+ struct raeth_priv *re = bus->priv;
+ int err;
+ u32 t;
+
+ err = ramips_mdio_wait_ready(re);
+ if (err)
+ return 0xffff;
+
+ t = (phy_addr << 24) | (phy_reg << 16);
+ ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
+ t |= (1 << 31);
+ ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
+
+ err = ramips_mdio_wait_ready(re);
+ if (err)
+ return 0xffff;
+
+ RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
+ phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff);
+
+ return ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff;
+}
+
+static int
+ramips_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
+{
+ struct raeth_priv *re = bus->priv;
+ int err;
+ u32 t;
+
+ RADEBUG("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
+ phy_addr, phy_reg, ramips_fe_rr(RAMIPS_MDIO_ACCESS) & 0xffff);
+
+ err = ramips_mdio_wait_ready(re);
+ if (err)
+ return err;
+
+ t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
+ ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
+ t |= (1 << 31);
+ ramips_fe_wr(t, RAMIPS_MDIO_ACCESS);
+
+ return ramips_mdio_wait_ready(re);
+}
+
+static int
+ramips_mdio_reset(struct mii_bus *bus)
+{
+ /* TODO */
+ return 0;
+}
+
+static int
+ramips_mdio_init(struct raeth_priv *re)
+{
+ int err;
+ int i;
+
+ re->mii_bus = mdiobus_alloc();
+ if (re->mii_bus == NULL)
+ return -ENOMEM;
+
+ re->mii_bus->name = "ramips_mdio";
+ re->mii_bus->read = ramips_mdio_read;
+ re->mii_bus->write = ramips_mdio_write;
+ re->mii_bus->reset = ramips_mdio_reset;
+ re->mii_bus->irq = re->mii_irq;
+ re->mii_bus->priv = re;
+ re->mii_bus->parent = re->parent;
+
+ snprintf(re->mii_bus->id, MII_BUS_ID_SIZE, "%s", "ramips_mdio");
+ re->mii_bus->phy_mask = 0;
+
+ for (i = 0; i < PHY_MAX_ADDR; i++)
+ re->mii_irq[i] = PHY_POLL;
+
+ err = mdiobus_register(re->mii_bus);
+ if (err)
+ goto err_free_bus;
+
+ return 0;
+
+err_free_bus:
+ kfree(re->mii_bus);
+ return err;
+}
+
+static void
+ramips_mdio_cleanup(struct raeth_priv *re)
+{
+ mdiobus_unregister(re->mii_bus);
+ kfree(re->mii_bus);
+}
+
+#else
+static inline void
+ramips_setup_mdio_cfg(struct raeth_priv *re)
+{
+}
+
+static inline int
+ramips_mdio_init(struct raeth_priv *re)
+{
+ return 0;
+}
+
+static inline void
+ramips_mdio_cleanup(struct raeth_priv *re)
+{
+}
+#endif /* CONFIG_RALINK_RT288X */
+
+static void
+ramips_cleanup_dma(struct raeth_priv *re)
+{
+ int i;
+
+ for (i = 0; i < NUM_RX_DESC; i++)
+ if (re->rx_skb[i]) {
+ dma_unmap_single(&re->netdev->dev, re->rx_dma[i],
+ MAX_RX_LENGTH, DMA_FROM_DEVICE);
+ dev_kfree_skb_any(re->rx_skb[i]);
+ }
+
+ if (re->rx)
+ dma_free_coherent(&re->netdev->dev,
+ NUM_RX_DESC * sizeof(struct ramips_rx_dma),
+ re->rx, re->rx_desc_dma);
+
+ if (re->tx)
+ dma_free_coherent(&re->netdev->dev,
+ NUM_TX_DESC * sizeof(struct ramips_tx_dma),
+ re->tx, re->tx_desc_dma);
+}
+
+static int
+ramips_alloc_dma(struct raeth_priv *re)
+{
+ int err = -ENOMEM;