+@@ -951,8 +993,12 @@
+ * Some MIPS CPUs have a dedicated interrupt vector which reduces the
+ * interrupt processing overhead. Use it where available.
+ */
++#ifdef CONFIG_AR7
++ memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x200), &except_vec4, 8);
++#else
+ if (cpu_has_divec)
+ memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
++#endif
+
+ /*
+ * Some CPUs can enable/disable for cache parity detection, but does
+@@ -991,12 +1037,17 @@
+ if (cpu_has_mcheck)
+ set_except_vector(24, handle_mcheck);
+
++memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
++#ifdef CONFIG_AR7
++ memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
++#else
+ if (cpu_has_vce)
+ memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
+ else if (cpu_has_4kex)
+ memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
+ else
+ memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
++#endif
+
+ if (current_cpu_data.cputype == CPU_R6000 ||
+ current_cpu_data.cputype == CPU_R6000A) {
+@@ -1023,7 +1074,11 @@
+ if (board_nmi_handler_setup)
+ board_nmi_handler_setup();
+
++#ifdef CONFIG_AR7
++ flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
++#else
+ flush_icache_range(KSEG0, KSEG0 + 0x400);
++#endif
+
+ per_cpu_trap_init();
+ }
+diff -urN linux-2.4.30/arch/mips/lib/promlib.c linux-2.4.30.dev/arch/mips/lib/promlib.c
+--- linux-2.4.30/arch/mips/lib/promlib.c 2005-06-14 18:42:06.000000000 +0200
++++ linux-2.4.30.dev/arch/mips/lib/promlib.c 2005-06-14 15:36:59.000000000 +0200