-diff -urN kernel-base/arch/mips/ar7/ar7/ar7_jump.S kernel-current/arch/mips/ar7/ar7/ar7_jump.S
---- kernel-base/arch/mips/ar7/ar7/ar7_jump.S 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/ar7/ar7_jump.S 2005-07-10 06:40:39.582267168 +0200
+diff -urN kernel-base/arch/mips/ar7/ar7/jump.S kernel-current/arch/mips/ar7/ar7/jump.S
+--- kernel-base/arch/mips/ar7/ar7/jump.S 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/ar7/jump.S 2005-07-10 06:40:39.582267000 +0200
@@ -0,0 +1,89 @@
+/*
+ * $Id$
+END(jump_dedicated_interrupt)
+
+ .set at
-diff -urN kernel-base/arch/mips/ar7/ar7/ar7_paging.c kernel-current/arch/mips/ar7/ar7/ar7_paging.c
---- kernel-base/arch/mips/ar7/ar7/ar7_paging.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/ar7/ar7_paging.c 2005-07-10 07:08:33.725758672 +0200
+diff -urN kernel-base/arch/mips/ar7/ar7/Makefile kernel-current/arch/mips/ar7/ar7/Makefile
+--- kernel-base/arch/mips/ar7/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/ar7/Makefile 2005-07-10 17:46:24.037377984 +0200
+@@ -0,0 +1,31 @@
++# $Id$
++# Copyright (C) $Date$ $Author$
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the License, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
++
++.S.s:
++ $(CPP) $(AFLAGS) $< -o $*.s
++
++.S.o:
++ $(CC) $(AFLAGS) -c $< -o $*.o
++
++EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
++
++O_TARGET := ar7.o
++
++export-objs := misc.o
++obj-y += paging.o jump.o misc.o
++
++include $(TOPDIR)/Rules.make
+diff -urN kernel-base/arch/mips/ar7/ar7/misc.c kernel-current/arch/mips/ar7/ar7/misc.c
+--- kernel-base/arch/mips/ar7/ar7/misc.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/ar7/misc.c 2005-07-10 19:02:11.699779472 +0200
+@@ -0,0 +1,319 @@
++#include <asm/ar7/sangam.h>
++#include <asm/ar7/avalanche_misc.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++
++#define TRUE 1
++
++static unsigned int avalanche_vbus_freq;
++
++REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
++
++/*****************************************************************************
++ * Reset Control Module.
++ *****************************************************************************/
++void avalanche_reset_ctrl(unsigned int module_reset_bit,
++ AVALANCHE_RESET_CTRL_T reset_ctrl)
++{
++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
++
++ if(module_reset_bit >= 32 && module_reset_bit < 64)
++ return;
++
++ if(module_reset_bit >= 64)
++ {
++ if(p_remote_vlynq_dev_reset_ctrl)
++ return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl));
++ else
++ return;
++ }
++
++ if(reset_ctrl == OUT_OF_RESET)
++ *reset_reg |= 1 << module_reset_bit;
++ else
++ *reset_reg &= ~(1 << module_reset_bit);
++}
++
++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
++{
++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
++
++ return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
++}
++
++void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
++{
++ volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
++ *sw_reset_reg = mode;
++}
++
++#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
++
++AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
++{
++ volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
++
++ return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
++}
++
++
++/*****************************************************************************
++ * Power Control Module
++ *****************************************************************************/
++#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
++#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
++
++
++void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
++{
++ volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++
++ if (power_ctrl == POWER_CTRL_POWER_DOWN)
++ /* power down the module */
++ *power_reg |= (1 << module_power_bit);
++ else
++ /* power on the module */
++ *power_reg &= (~(1 << module_power_bit));
++}
++
++AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
++{
++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++
++ return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
++}
++
++void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
++{
++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++
++ *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
++ *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
++}
++
++AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
++{
++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
++
++ return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
++ >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
++}
++
++/*****************************************************************************
++ * GPIO Control
++ *****************************************************************************/
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_init
++ ***************************************************************************/
++void avalanche_gpio_init(void)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
++ spin_lock_irqsave(&closeLock, closeFlag);
++ *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++}
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_ctrl
++ ***************************************************************************/
++int avalanche_gpio_ctrl(unsigned int gpio_pin,
++ AVALANCHE_GPIO_PIN_MODE_T pin_mode,
++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
++
++ if(gpio_pin >= 32)
++ return(-1);
++
++ spin_lock_irqsave(&closeLock, closeFlag);
++
++ if(pin_mode == GPIO_PIN)
++ {
++ *gpio_ctrl |= (1 << gpio_pin);
++
++ gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
++
++ if(pin_direction == GPIO_INPUT_PIN)
++ *gpio_ctrl |= (1 << gpio_pin);
++ else
++ *gpio_ctrl &= ~(1 << gpio_pin);
++ }
++ else /* FUNCTIONAL PIN */
++ {
++ *gpio_ctrl &= ~(1 << gpio_pin);
++ }
++
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++
++ return (0);
++}
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_out
++ ***************************************************************************/
++int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
++
++ if(gpio_pin >= 32)
++ return(-1);
++
++ spin_lock_irqsave(&closeLock, closeFlag);
++ if(value == TRUE)
++ *gpio_out |= 1 << gpio_pin;
++ else
++ *gpio_out &= ~(1 << gpio_pin);
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++
++ return(0);
++}
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_in
++ ***************************************************************************/
++int avalanche_gpio_in_bit(unsigned int gpio_pin)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
++ int ret_val = 0;
++
++ if(gpio_pin >= 32)
++ return(-1);
++
++ spin_lock_irqsave(&closeLock, closeFlag);
++ ret_val = ((*gpio_in) & (1 << gpio_pin));
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++
++ return (ret_val);
++}
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_out_val
++ ***************************************************************************/
++int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
++ unsigned int reg_index)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
++
++ if(reg_index > 0)
++ return(-1);
++
++ spin_lock_irqsave(&closeLock, closeFlag);
++ *gpio_out &= ~out_mask;
++ *gpio_out |= out_val;
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++
++ return(0);
++}
++
++/****************************************************************************
++ * FUNCTION: avalanche_gpio_in_value
++ ***************************************************************************/
++int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
++{
++ spinlock_t closeLock;
++ unsigned int closeFlag;
++ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
++
++ if(reg_index > 0)
++ return(-1);
++
++ spin_lock_irqsave(&closeLock, closeFlag);
++ *in_val = *gpio_in;
++ spin_unlock_irqrestore(&closeLock, closeFlag);
++
++ return (0);
++}
++
++/***********************************************************************
++ *
++ * Wakeup Control Module for TNETV1050 Communication Processor
++ *
++ ***********************************************************************/
++
++#define AVALANCHE_WAKEUP_POLARITY_BIT 16
++
++void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
++ AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
++ AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
++{
++ volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
++
++ /* enable/disable */
++ if (wakeup_ctrl == WAKEUP_ENABLED)
++ /* enable wakeup */
++ *wakeup_status_reg |= wakeup_int;
++ else
++ /* disable wakeup */
++ *wakeup_status_reg &= (~wakeup_int);
++
++ /* set polarity */
++ if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
++ *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
++ else
++ *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
++}
++
++void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
++{
++ avalanche_vbus_freq = new_vbus_freq;
++}
++
++unsigned int avalanche_get_vbus_freq()
++{
++ return(avalanche_vbus_freq);
++}
++
++unsigned int avalanche_get_chip_version_info()
++{
++ return(*(volatile unsigned int*)AVALANCHE_CVR);
++}
++
++SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
++
++int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
++{
++ if(p_set_mdix_on_chip_fn)
++ return (p_set_mdix_on_chip_fn(base_addr, operation));
++ else
++ return(-1);
++}
++
++unsigned int avalanche_is_mdix_on_chip(void)
++{
++ return(p_set_mdix_on_chip_fn ? 1:0);
++}
++
++EXPORT_SYMBOL(avalanche_reset_ctrl);
++EXPORT_SYMBOL(avalanche_get_reset_status);
++EXPORT_SYMBOL(avalanche_sys_reset);
++EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
++EXPORT_SYMBOL(avalanche_power_ctrl);
++EXPORT_SYMBOL(avalanche_get_power_status);
++EXPORT_SYMBOL(avalanche_set_global_power_mode);
++EXPORT_SYMBOL(avalanche_get_global_power_mode);
++EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
++EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
++
++EXPORT_SYMBOL(avalanche_gpio_init);
++EXPORT_SYMBOL(avalanche_gpio_ctrl);
++EXPORT_SYMBOL(avalanche_gpio_out_bit);
++EXPORT_SYMBOL(avalanche_gpio_in_bit);
++EXPORT_SYMBOL(avalanche_gpio_out_value);
++EXPORT_SYMBOL(avalanche_gpio_in_value);
++
++EXPORT_SYMBOL(avalanche_set_vbus_freq);
++EXPORT_SYMBOL(avalanche_get_vbus_freq);
++
++EXPORT_SYMBOL(avalanche_get_chip_version_info);
++
+diff -urN kernel-base/arch/mips/ar7/ar7/paging.c kernel-current/arch/mips/ar7/ar7/paging.c
+--- kernel-base/arch/mips/ar7/ar7/paging.c 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/arch/mips/ar7/ar7/paging.c 2005-07-10 07:08:33.725758000 +0200
@@ -0,0 +1,314 @@
+/*
+ * -*- linux-c -*-
+ * Determine the low and high memory ranges
+ */
+
-+ max_low_pfn = max_pfn;
-+
-+ /*
-+ * Partially used pages are not usable - thus we are
-+ * rounding upwards:
-+ */
-+
-+ start_pfn = PFN_UP(__pa(&_end));
-+
-+ /*
-+ * Find a proper area for the bootmem bitmap. After this
-+ * bootstrap step all allocations (until the page allocator is
-+ * intact) must be done via bootmem_alloc().
-+ */
-+
-+ bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
-+ __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
-+
-+
-+ /*
-+ * Register fully available low RAM pages with the bootmem allocator.
-+ */
-+
-+ {
-+ unsigned long curr_pfn, last_pfn, pages;
-+
-+ /*
-+ * We are rounding up the start address of usable memory:
-+ */
-+ curr_pfn = PFN_UP(__MEMORY_START);
-+
-+ /*
-+ * ... and at the end of the usable range downwards:
-+ */
-+ last_pfn = PFN_DOWN(__pa(memory_end));
-+
-+ if (last_pfn > max_low_pfn)
-+ last_pfn = max_low_pfn;
-+
-+ pages = last_pfn - curr_pfn;
-+
-+
-+ free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
-+ PFN_PHYS(pages));
-+ }
-+
-+ /*
-+ * Reserve the kernel text and
-+ * Reserve the bootmem bitmap. We do this in two steps (first step
-+ * was init_bootmem()), because this catches the (definitely buggy)
-+ * case of us accidentally initializing the bootmem allocator with
-+ * an invalid RAM area.
-+ */
-+ reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
-+ (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
-+
-+ /*
-+ * reserve physical page 0 - it's a special BIOS page on many boxes,
-+ * enabling clean reboots, SMP operation, laptop functions.
-+ */
-+ reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
-+}
-+
-+extern char __init_begin, __init_end;
-+
-+void free_initmem(void)
-+{
-+ unsigned long addr;
-+ // prom_free_prom_memory ();
-+
-+ addr = (unsigned long) &__init_begin;
-+ while (addr < (unsigned long) &__init_end) {
-+ ClearPageReserved(virt_to_page(addr));
-+ set_page_count(virt_to_page(addr), 1);
-+ free_page(addr);
-+ totalram_pages++;
-+ addr += PAGE_SIZE;
-+ }
-+ printk("Freeing unused kernel memory: %dk freed\n",
-+ (&__init_end - &__init_begin) >> 10);
-+}
-+
-+void si_meminfo(struct sysinfo *val)
-+{
-+ val->totalram = totalram_pages;
-+ val->sharedram = 0;
-+ val->freeram = nr_free_pages();
-+ val->bufferram = atomic_read(&buffermem_pages);
-+ val->totalhigh = 0;
-+ val->freehigh = nr_free_highpages();
-+ val->mem_unit = PAGE_SIZE;
-+
-+ return;
-+}
-diff -urN kernel-base/arch/mips/ar7/ar7/gpio.c kernel-current/arch/mips/ar7/ar7/gpio.c
---- kernel-base/arch/mips/ar7/ar7/gpio.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/ar7/gpio.c 2005-07-10 09:46:52.164776456 +0200
-@@ -0,0 +1,132 @@
-+#include <linux/kernel.h>
-+#include <asm/uaccess.h>
-+#include <linux/spinlock.h>
-+#include <linux/proc_fs.h>
-+#include <linux/fs.h>
-+#include <linux/timer.h>
-+#include <linux/module.h>
-+#include <linux/stddef.h>
-+
-+#include <asm/ar7/tnetd73xx_err.h>
-+#include <asm/ar7/tnetd73xx_misc.h>
-+#include <asm/ar7/ledapp.h>
-+
-+
-+#if defined (CONFIG_AR7RD) || defined(CONFIG_AR7WRD)
-+
-+#define AR7_RESET_FILE "led_mod/ar7reset"
-+#define AR7_RESET_GPIO 11
-+#define RESET_POLL_TIME 1
-+#define RESET_HOLD_TIME 4
-+#define NO_OF_LEDS
-+#define TRUE 1
-+#define FALSE 0
-+
-+static struct proc_dir_entry *reset_file;
-+static int res_state = 0;
-+static int count;
-+static struct timer_list *pTimer = NULL;
-+static ssize_t proc_read_reset_fops(struct file *filp, char *buf, size_t count, loff_t * offp);
-+
-+struct file_operations reset_fops = {
-+ read:proc_read_reset_fops
-+};
-+
-+#endif
-+
-+static spinlock_t device_lock;
-+led_reg_t temp[15];
-+
-+static void gpio_led_on(unsigned long param)
-+{
-+ unsigned int flags;
-+
-+ spin_lock_irqsave(&device_lock, flags);
-+ tnetd73xx_gpio_out(param, FALSE);
-+ spin_unlock_irqrestore(&device_lock, flags);
-+}
-+
-+static void gpio_led_off(unsigned long param)
-+{
-+ unsigned int flags = 0x00;
-+
-+ spin_lock_irqsave(&device_lock, flags);
-+ tnetd73xx_gpio_out(param, TRUE);
-+ spin_unlock_irqrestore(&device_lock, flags);
-+}
-+
-+static void gpio_led_init(unsigned long param)
-+{
-+ tnetd73xx_gpio_ctrl(param, GPIO_PIN, GPIO_OUTPUT_PIN);
-+}
-+
-+static void board_gpio_reset(void)
-+{
-+ tnetd73xx_gpio_init();
-+
-+ /* Initialize the link mask */
-+ device_lock = SPIN_LOCK_UNLOCKED;
-+ return;
-+}
-+
-+#if defined(CONFIG_AR7WRD)
-+
-+static ssize_t proc_read_reset_fops(struct file *filp, char *buf, size_t count, loff_t * offp)
-+{
-+ char *pdata = NULL;
-+ char line[3];
-+ int len = 0;
-+ if (*offp != 0)
-+ return 0;
-+
-+ pdata = buf;
-+ len = sprintf(line, "%d\n", res_state);
-+ res_state = 0;
-+ copy_to_user(buf, line, len);
-+ *offp = len;
-+ return len;
-+}
-+
-+static void reset_timer_func(unsigned long data)
-+{
-+ count = (tnetd73xx_gpio_in(AR7_RESET_GPIO) == 0) ? count + 1 : 0;
-+ if (count >= RESET_HOLD_TIME / RESET_POLL_TIME)
-+ res_state = 1;
-+ pTimer->expires = jiffies + HZ * RESET_POLL_TIME;
-+ add_timer(pTimer);
-+ return;
-+}
-+
-+static void reset_init(void)
-+{
-+ /* Create board reset proc file */
-+ reset_file = create_proc_entry(AR7_RESET_FILE, 0777, NULL);
-+ if (reset_file == NULL)
-+ goto reset_file;
-+ reset_file->owner = THIS_MODULE;
-+ reset_file->proc_fops = &reset_fops;
-+
-+ /* Initialise GPIO 11 for input */
-+ tnetd73xx_gpio_ctrl(AR7_RESET_GPIO, GPIO_PIN, GPIO_INPUT_PIN);
-+
-+ /* Create a timer which fires every seconds */
-+ pTimer = kmalloc(sizeof(struct timer_list), GFP_KERNEL);
-+ init_timer(pTimer);
-+ pTimer->function = reset_timer_func;
-+ pTimer->data = 0;
-+ /* Start the timer */
-+ reset_timer_func(0);
-+ return;
-+
-+ reset_file:
-+ remove_proc_entry(AR7_RESET_FILE, NULL);
-+ return;
-+}
-+#endif
-+
-+
-+void board_gpio_init(void)
-+{
-+ board_gpio_reset();
-+ return;
-+}
-diff -urN kernel-base/arch/mips/ar7/ar7/ledmod.c kernel-current/arch/mips/ar7/ar7/ledmod.c
---- kernel-base/arch/mips/ar7/ar7/ledmod.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/ar7/ledmod.c 2005-07-10 09:45:36.692250024 +0200
-@@ -0,0 +1,712 @@
-+#include <linux/config.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/proc_fs.h>
-+#include <asm/uaccess.h>
-+#include <linux/fs.h>
-+#include <linux/timer.h>
-+#include <linux/delay.h>
-+#include <linux/spinlock.h>
-+#include <asm/ar7/avalanche_regs.h>
-+#include <asm/ar7/ledapp.h>
-+#include <linux/module.h>
-+
-+#define LED_ON 1
-+#define LED_OFF 2
-+#define LED_BLINK 3
-+#define LED_FLASH 4
-+
-+#define LED_BLINK_UP 5
-+#define LED_BLINK_DOWN 6
-+
-+typedef struct state_entry {
-+ unsigned char mode;
-+ unsigned char led;
-+ void (*handler) (struct state_entry * pState);
-+ unsigned long param;
-+} state_entry_t;
-+
-+typedef struct mod_entry {
-+ state_entry_t *states[MAX_STATE_ID];
-+} mod_entry_t;
-+
-+static mod_entry_t *modArr[MAX_MOD_ID];
-+static struct proc_dir_entry *led_proc_dir, *led_file;
-+
-+/* index of the array is the led number HARDWARE SPECIFIC*/
-+typedef struct led_data {
-+ led_reg_t *led;
-+ int state;
-+ struct timer_list *pTimer;
-+ unsigned char timer_running;
-+ unsigned long param;
-+} led_data_t;
-+
-+led_data_t led_arr[MAX_LED_ID + 1];
-+/*!!! The last device is actually being used for ar7 reset to factory default */
-+#if 1
-+/* Ron add for adsl LED blink */
-+#define GPIO_ADSL_ACT (1<<6)
-+#define GPIO_ADSL_DOWN (1<<8)
-+#define BLINK_FAST 5*HZ/100
-+#define BLINK_SLOW 15*HZ/100
-+static struct timer_list my_led_timer;
-+static int my_blink_count = 0;
-+static int my_mode = 1;
-+void led_operation(int mod, int state);
-+
-+static void my_led_on(unsigned long gpio, int logic)
-+{
-+ if (logic > 0)
-+ GPIO_DATA_OUTPUT |= gpio;
-+ else
-+ GPIO_DATA_OUTPUT &= ~gpio;
-+
-+}
-+static void my_led_off(unsigned long gpio, int logic)
-+{
-+ if (logic > 0)
-+ GPIO_DATA_OUTPUT &= ~gpio;
-+ else
-+ GPIO_DATA_OUTPUT |= gpio;
-+
-+}
-+
-+static void my_led_init(unsigned long gpio, int init, int logic)
-+{
-+ GPIO_DATA_ENABLE |= gpio;
-+ GPIO_DATA_DIR &= ~gpio;
-+ if (init)
-+ my_led_on(gpio, logic);
-+ else
-+ my_led_off(gpio, logic);
-+}
-+
-+static void my_led_blink_timer(unsigned long data)
-+{
-+ unsigned long gpio = GPIO_ADSL_ACT;
-+ unsigned int speed = BLINK_FAST;
-+ if (my_mode == 2) {
-+ gpio = GPIO_ADSL_DOWN;
-+ speed = BLINK_SLOW;
-+ }
-+ if (my_blink_count) {
-+ if (GPIO_DATA_OUTPUT & gpio) {
-+ GPIO_DATA_OUTPUT &= ~gpio;
-+ if (my_mode != 2)
-+ my_blink_count = 0;
-+ } else {
-+ GPIO_DATA_OUTPUT |= gpio;
-+ }
-+ }
-+ my_led_timer.expires = jiffies + speed;
-+ add_timer(&my_led_timer);
-+}
-+
-+/* Ron add for ADSL led blink */
-+#endif
-+static spinlock_t config_lock;
-+
-+static void board_led_link_up(state_entry_t * pState);
-+static void board_led_link_down(state_entry_t * pState);
-+static void board_led_activity_on(state_entry_t * pState);
-+static void board_led_activity_off(state_entry_t * pState);
-+static void led_timer_func(unsigned long data);
-+
-+extern void board_gpio_init(void);
-+extern void uart_led_init(void);
-+
-+static ssize_t proc_read_led_fops(struct file *filp, char *buf, size_t count, loff_t * offp);
-+static ssize_t proc_write_led_fops(struct file *filp, const char *buffer, size_t count, loff_t * offp);
-+static int config_led(unsigned long y);
-+
-+struct file_operations led_fops = {
-+ read:proc_read_led_fops,
-+ write:proc_write_led_fops,
-+};
-+
-+static int led_atoi(char *name)
-+{
-+ int val = 0;
-+ for (;; name++) {
-+ switch (*name) {
-+ case '0'...'9':
-+ val = val * 10 + (*name - '0');
-+ break;
-+ default:
-+ return val;
-+ }
-+ }
-+}
-+
-+static int free_memory(void)
-+{
-+ int i, j;
-+
-+ for (i = 0; i < MAX_MOD_ID; i++) {
-+ if (modArr[i] != NULL) {
-+ for (j = 0; j < MAX_STATE_ID; j++) {
-+ if (modArr[i]->states[j] != NULL)
-+ kfree(modArr[i]->states[j]);
-+ }
-+ kfree(modArr[i]);
-+ modArr[i] = NULL;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static int led_on(state_entry_t * pState)
-+{
-+ if (led_arr[pState->led].led == NULL)
-+ return -1;
-+ led_arr[pState->led].led->onfunc(led_arr[pState->led].led->param);
-+ return 0;
-+}
-+
-+static int led_off(state_entry_t * pState)
-+{
-+ if (led_arr[pState->led].led == NULL)
-+ return -1;
-+ led_arr[pState->led].led->offfunc(led_arr[pState->led].led->param);
-+ return 0;
-+}
-+
-+static void board_led_link_up(state_entry_t * pState)
-+{
-+ led_arr[pState->led].state = LED_ON;
-+ if (led_arr[pState->led].timer_running == 0)
-+ led_on(pState);
-+ return;
-+}
-+
-+static void board_led_link_down(state_entry_t * pState)
-+{
-+ led_arr[pState->led].state = LED_OFF;
-+ if (led_arr[pState->led].timer_running == 0)
-+ led_off(pState);
-+ return;
-+}
-+
-+static void add_led_timer(state_entry_t * pState)
-+{
-+ led_arr[pState->led].pTimer->expires =
-+ jiffies + HZ * (pState->param) / 1000;
-+ led_arr[pState->led].param = pState->param;
-+ led_arr[pState->led].pTimer->data = pState;
-+ add_timer(led_arr[pState->led].pTimer);
-+}
-+
-+static void board_led_activity_on(state_entry_t * pState)
-+{
-+ if (led_arr[pState->led].timer_running == 0) {
-+ led_on(pState);
-+ add_led_timer(pState);
-+ led_arr[pState->led].timer_running = 1;
-+ led_arr[pState->led].state = LED_BLINK_UP;
-+ } else if (led_arr[pState->led].timer_running > 0xF0) {
-+ led_arr[pState->led].state = LED_BLINK_UP;
-+ led_arr[pState->led].pTimer->expires =
-+ jiffies + HZ * (pState->param) / 1000;
-+ led_arr[pState->led].param = pState->param;
-+ led_arr[pState->led].pTimer->data = pState;
-+ }
-+ return;
-+}
-+
-+static void board_led_activity_off(state_entry_t * pState)
-+{
-+ if (led_arr[pState->led].timer_running == 0) {
-+ led_off(pState);
-+ add_led_timer(pState);
-+ led_arr[pState->led].timer_running = 1;
-+ led_arr[pState->led].state = LED_BLINK_UP;
-+ } else if (led_arr[pState->led].timer_running > 0xF0) {
-+ led_arr[pState->led].state = LED_BLINK_UP;
-+ led_arr[pState->led].pTimer->expires =
-+ jiffies + HZ * (pState->param) / 1000;
-+ led_arr[pState->led].param = pState->param;
-+ led_arr[pState->led].pTimer->data = pState;
-+ }
-+ return;
-+}
-+
-+static void board_led_link_flash(state_entry_t * pState)
-+{
-+ if (led_on(pState))
-+ return;
-+ if (led_arr[pState->led].timer_running == 0)
-+ add_led_timer(pState);
-+ else
-+ led_arr[pState->led].param = pState->param;
-+ led_arr[pState->led].timer_running = 0xFF;
-+ led_arr[pState->led].state = LED_FLASH;
-+ return;
-+}
-+
-+static void led_timer_func(unsigned long data)
-+{
-+ state_entry_t *pState = NULL;
-+ mod_entry_t *pMod = NULL;
-+ unsigned int flags;
-+
-+ spin_lock_irqsave(&config_lock, flags);
-+
-+ pState = (state_entry_t *) data;
-+
-+ if (led_arr[pState->led].state == LED_BLINK_DOWN) {
-+ led_arr[pState->led].timer_running = 0;
-+ if (pState->mode == 2)
-+ led_arr[pState->led].state = LED_OFF;
-+ else
-+ led_arr[pState->led].state = LED_ON;
-+ } else if (led_arr[pState->led].state == LED_BLINK_UP) {
-+ led_arr[pState->led].pTimer->expires =
-+ jiffies + HZ * (led_arr[pState->led].param) / 1000;
-+ led_arr[pState->led].pTimer->data = pState;
-+ add_timer(led_arr[pState->led].pTimer);
-+ if (pState->mode == 2) {
-+ led_off(pState);
-+ led_arr[pState->led].state = LED_BLINK_DOWN;
-+ } else {
-+ led_on(pState);
-+ led_arr[pState->led].state = LED_BLINK_DOWN;
-+ }
-+ led_arr[pState->led].timer_running = 1;
-+ } else if (led_arr[pState->led].state == LED_FLASH) {
-+ led_arr[pState->led].pTimer->expires =
-+ jiffies + HZ * (led_arr[pState->led].param) / 1000;
-+ led_arr[pState->led].pTimer->data = pState;
-+ add_timer(led_arr[pState->led].pTimer);
-+
-+ if (led_arr[pState->led].timer_running == 0xFF) {
-+ led_off(pState);
-+ led_arr[pState->led].timer_running--;
-+ } else {
-+ led_on(pState);
-+ led_arr[pState->led].timer_running++;
-+ }
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return;
-+ } else if (led_arr[pState->led].state == LED_OFF) {
-+ led_off(pState);
-+ led_arr[pState->led].timer_running = 0;
-+ } else if (led_arr[pState->led].state == LED_ON) {
-+ led_on(pState);
-+ led_arr[pState->led].timer_running = 0;
-+ }
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return;
-+}
-+
-+static ssize_t proc_read_led_fops(struct file *filp,
-+ char *buf, size_t count, loff_t * offp)
-+{
-+ char *pdata = NULL;
-+ int i = 0, j = 0, len = 0, totallen = 0;
-+ char line[255];
-+
-+ if (*offp != 0)
-+ return 0;
-+
-+ pdata = buf;
-+ len += sprintf(line, "LEDS Registered for use are:");
-+ for (i = 0; i < MAX_LED_ID; i++)
-+ if (led_arr[i].led != NULL)
-+ len += sprintf(&line[len], " %d ", i);
-+ line[len++] = '\n';
-+
-+ copy_to_user(pdata, line, len);
-+ pdata += len;
-+ totallen += len;
-+ len = 0;
-+ len = sprintf(line, "USER MODULE INFORMATION:\n");
-+ copy_to_user(pdata, line, len);
-+ pdata += len;
-+ totallen += len;
-+ len = 0;
-+ for (i = 0; i < MAX_MOD_ID; i++) {
-+ if (modArr[i] != NULL) {
-+ len = sprintf(line, " Module ID = %d \n", i);
-+ copy_to_user(pdata, line, len);
-+ pdata += len;
-+ totallen += len;
-+ len = 0;
-+ for (j = 0; j < MAX_STATE_ID; j++) {
-+ if (modArr[i]->states[j] != NULL) {
-+ len = sprintf(line, " State = %d , Led = %d,", j,
-+ modArr[i]->states[j]->led);
-+ copy_to_user(pdata, line, len);
-+ pdata += len;
-+ totallen += len;
-+
-+ len = 0;
-+ switch (modArr[i]->states[j]->mode) {
-+ case 1:
-+ len = sprintf(line, " Mode = OFF\n");
-+ break;
-+ case 2:
-+ len = sprintf(line, " Mode = BLINK_ON , On Time(ms) = %d\n",
-+ (unsigned int) modArr[i]->states[j]->
-+ param);
-+ break;
-+ case 3:
-+ len = sprintf(line, " Mode = BLINK_OFF , Off Time(ms) = %d\n",
-+ (unsigned int) modArr[i]->states[j]->
-+ param);
-+ break;
-+ case 4:
-+ len = sprintf(line, " Mode = ON \n");
-+ break;
-+ case 5:
-+ len = sprintf(line, " Mode = FLASH , Time Period(ms) = %d\n",
-+ (unsigned int) modArr[i]->states[j]->
-+ param);
-+ break;
-+ default:
-+ break;
-+
-+ }
-+ copy_to_user(pdata, line, len);
-+ pdata += len;
-+ totallen += len;
-+
-+ len = 0;
-+ }
-+ }
-+ }
-+ }
-+ /* Return with configuration information for LEDs */
-+ *offp = totallen;
-+ return totallen;
-+}
-+
-+static ssize_t proc_write_led_fops(struct file *filp, const char *buffer, size_t count, loff_t * offp)
-+{
-+ char *pdata = NULL, *ptemp = NULL;
-+ char line[10], temp[10];
-+ int i = 0;
-+ int mod = 0xFFFF, state = 0xFFFF;
-+ int flag = 0;
-+
-+ /* Check if this write is for configuring stuff */
-+ if (*(int *) (buffer) == 0xFFEEDDCC) {
-+ printk("<1>proc write:Calling Configuration\n");
-+ config_led((unsigned long) (buffer + sizeof(int)));
-+ return count;
-+ }
-+
-+ if (count >= 10) {
-+ printk("<1>proc write:Input too long,max length = %d\n", 10);
-+ return count;
-+ }
-+ memset(temp, 0x00, 10);
-+ memset(line, 0x00, 10);
-+ copy_from_user(line, buffer, count);
-+ line[count] = 0x00;
-+ pdata = line;
-+ ptemp = temp;
-+ while (flag == 0) {
-+ if (i > 10)
-+ break;
-+ if (((*pdata) >= '0') && ((*pdata) <= '9')) {
-+ *ptemp = *pdata;
-+ ptemp++;
-+ } else if ((*pdata) == ',') {
-+ *ptemp = 0x00;
-+ flag = 1;
-+ }
-+ pdata++;
-+ i++;
-+ };
-+ if (flag == 1)
-+ mod = led_atoi(temp);
-+ else
-+ return count;
-+
-+ ptemp = temp;
-+ *ptemp = 0x00;
-+ flag = 0;
-+ while (flag == 0) {
-+ if (i > 10)
-+ break;
-+ if (((*pdata) >= '0') && ((*pdata) <= '9')) {
-+ *ptemp = *pdata;
-+ ptemp++;
-+ } else if ((*pdata) == 0x00) {
-+ *ptemp = 0x00;
-+ flag = 1;
-+ }
-+ pdata++;
-+ i++;
-+ };
-+ if (flag == 1)
-+ state = led_atoi(temp);
-+ else
-+ return count;
-+ if ((mod == 0xFFFF) || (state == 0xFFFF))
-+ return count;
-+ else
-+ led_operation(mod, state);
-+ return count;
-+}
-+
-+static int config_led(unsigned long y)
-+{
-+ config_elem_t *pcfg = NULL;
-+ char *pdata = NULL;
-+ int i;
-+ int length = 0, number = 0;
-+ unsigned int flags;
-+
-+ spin_lock_irqsave(&config_lock, flags);
-+
-+ /* ioctl to configure */
-+ length = *((int *) y);
-+ pdata = (char *) y + sizeof(int);
-+ number = (length - sizeof(int)) / sizeof(config_elem_t);
-+ pcfg = (config_elem_t *) (pdata);
-+
-+ /* Check if an earlier configuration exists IF yes free it up */
-+ free_memory();
-+
-+ for (i = 0; i < number; i++) {
-+ /* If no structure has been allocated for the module do so */
-+ if (modArr[pcfg->name] == NULL) {
-+ printk("<1>module = %d\n", pcfg->name);
-+ if (pcfg->name >= MAX_MOD_ID) {
-+ printk
-+ ("<1>Exiting Configuration: Module ID too large %d\n",
-+ pcfg->name);
-+ free_memory();
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return -1;
-+ }
-+ modArr[pcfg->name] = kmalloc(sizeof(mod_entry_t), GFP_KERNEL);
-+ if (modArr[pcfg->name] == NULL) {
-+ printk
-+ ("<1>Exiting Configuration: Error in allocating memory\n");
-+ free_memory();
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return -1;
-+ }
-+ memset(modArr[pcfg->name], 0x00, sizeof(mod_entry_t));
-+ }
-+
-+ /* if no structure is allocated previously for this state
-+ allocate a structure, if it's already there fill it up */
-+ if (modArr[pcfg->name]->states[pcfg->state] == NULL) {
-+ printk("<1>STATE = %d\n", pcfg->state);
-+ if (pcfg->state >= MAX_STATE_ID) {
-+ printk("<1>Exiting Configuration: State ID too large\n");
-+ free_memory();
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return -1;
-+ }
-+ modArr[pcfg->name]->states[pcfg->state] =
-+ kmalloc(sizeof(state_entry_t), GFP_KERNEL);
-+ if (modArr[pcfg->name]->states[pcfg->state] == NULL) {
-+ free_memory();
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return -1;
-+ }
-+ memset(modArr[pcfg->name]->states[pcfg->state], 0x00,
-+ sizeof(state_entry_t));
-+ }
-+ /* Fill up the fields of the state */
-+ if (pcfg->led >= MAX_LED_ID) {
-+ printk("<1>led = %d\n", pcfg->led);
-+ free_memory();
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return -1;
-+ }
-+ modArr[pcfg->name]->states[pcfg->state]->led = pcfg->led;
-+ modArr[pcfg->name]->states[pcfg->state]->mode = pcfg->mode;
-+ modArr[pcfg->name]->states[pcfg->state]->param = pcfg->param;
-+ switch (pcfg->mode) {
-+ case 1:
-+ modArr[pcfg->name]->states[pcfg->state]->handler =
-+ board_led_link_down;
-+ break;
-+ case 2:
-+ case 3:
-+ case 5:
-+ if (pcfg->mode == 2)
-+ modArr[pcfg->name]->states[pcfg->state]->handler =
-+ board_led_activity_on;
-+ else if (pcfg->mode == 3)
-+ modArr[pcfg->name]->states[pcfg->state]->handler =
-+ board_led_activity_off;
-+ else
-+ modArr[pcfg->name]->states[pcfg->state]->handler =
-+ board_led_link_flash;
-+ break;
-+ case 4:
-+ modArr[pcfg->name]->states[pcfg->state]->handler =
-+ board_led_link_up;
-+ break;
-+ default:
-+ printk("<1>Exiting Configuration: Unknown LED Mode\n");
-+ free_memory();
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return -1;
-+ }
-+ pcfg++;
-+ }
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return 0;
-+}
-+
-+
-+int led_init(void)
-+{
-+
-+ /* Clear our memory */
-+ memset(modArr, 0x00, sizeof(mod_entry_t *) * MAX_MOD_ID);
-+ memset(led_arr, 0x00, sizeof(led_data_t *) * MAX_LED_ID);
-+
-+ /* Create spin lock for config data structure */
-+ config_lock = SPIN_LOCK_UNLOCKED;
-+
-+ /* Create directory */
-+ led_proc_dir = proc_mkdir("led_mod", NULL);
-+ if (led_proc_dir == NULL)
-+ goto out;
-+
-+ /* Create adsl file */
-+ led_file = create_proc_entry("led", 0777, led_proc_dir);
-+ if (led_file == NULL)
-+ goto led_file;
-+ led_file->owner = THIS_MODULE;
-+ led_file->proc_fops = &led_fops;
-+
-+ memset(modArr, 0x00, sizeof(mod_entry_t *) * MAX_MOD_ID);
-+ /* Reset the GPIO pins */
-+ board_gpio_init();
-+
-+ /* Ron add for ADSL LED blink */
-+ my_mode = 1;
-+ my_led_init(GPIO_ADSL_ACT, 0, -1);
-+ my_led_init(GPIO_ADSL_DOWN, 0, -1);
-+ init_timer(&my_led_timer);
-+ my_led_timer.function = my_led_blink_timer;
-+ my_led_timer.data = 0;
-+ my_led_timer.expires = jiffies + BLINK_SLOW;
-+ add_timer(&my_led_timer);
-+ /* Ron add for ADSL LED blink */
-+ return 0;
-+
-+ led_file:
-+ remove_proc_entry("led", led_proc_dir);
-+ out:
-+ return 0;
-+
-+}
-+
-+void led_operation(int mod, int state)
-+{
-+
-+ unsigned int flags;
-+
-+ spin_lock_irqsave(&config_lock, flags);
-+#if 1
-+ /* Ron Add for ADSL LED blink */
-+ //printk("mod==%d state==%d\n",mod,state);
-+
-+ if (mod == 1) {
-+ switch (state) {
-+ /* off */
-+ case 1:
-+ my_mode = 1;
-+ my_blink_count = 0;
-+ my_led_off(GPIO_ADSL_ACT, -1);
-+ my_led_off(GPIO_ADSL_DOWN, -1);
-+ break;
-+ /* sync */
-+ case 2:
-+ if (my_mode == 1) {
-+ my_mode = 2;
-+ my_led_off(GPIO_ADSL_ACT, -1);
-+ my_blink_count++;
-+ }
-+ break;
-+ /* on */
-+ case 3:
-+ my_mode = 3;
-+ my_blink_count = 0;
-+ my_led_off(GPIO_ADSL_DOWN, -1);
-+ my_led_on(GPIO_ADSL_ACT, -1);
-+ break;
-+ /* off */
-+ case 4:
-+ my_mode = 4;
-+ my_led_off(GPIO_ADSL_DOWN, -1);
-+ my_blink_count++;
-+ break;
-+ }
-+ } /* Ron add for ADSL LED Blink */
-+#endif
-+ if ((mod >= MAX_MOD_ID) || (state >= MAX_STATE_ID)) {
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return;
-+ }
-+ if (modArr[mod] == NULL) {
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return;
-+ }
-+ if (modArr[mod]->states[state] == NULL) {
-+ spin_unlock_irqrestore(&config_lock, flags);
-+ return;
-+ }
-+ /* Call the function handler */
-+ modArr[mod]->states[state]->handler(modArr[mod]->states[state]);
-+
-+ spin_unlock_irqrestore(&config_lock, flags);
-+}
-+
-+void register_led_drv(int device, led_reg_t * pInfo)
-+{
-+ unsigned int flags;
-+ struct timer_list *pTimer = NULL;
-+
-+ spin_lock_irqsave(&config_lock, flags);
-+
-+ led_arr[device].led = pInfo;
-+ if (led_arr[device].led->init != 0x00)
-+ led_arr[device].led->init(led_arr[device].led->param);
-+ if (led_arr[device].led->offfunc != 0x00)
-+ led_arr[device].led->offfunc(led_arr[device].led->param);
-+
-+ /* Create a timer for blinking */
-+ pTimer = kmalloc(sizeof(struct timer_list), GFP_KERNEL);
-+ init_timer(pTimer);
-+ pTimer->function = led_timer_func;
-+ pTimer->data = 0;
-+ led_arr[device].pTimer = pTimer;
-+ led_arr[device].timer_running = 0;
-+
-+ spin_unlock_irqrestore(&config_lock, flags);
-+
-+ return;
-+}
-+
-+void deregister_led_drv(int device)
-+{
-+ unsigned int flags;
-+
-+ spin_lock_irqsave(&config_lock, flags);
-+ led_arr[device].led = NULL;
-+
-+ if (led_arr[device].pTimer != NULL) {
-+ del_timer(led_arr[device].pTimer);
-+ kfree(led_arr[device].pTimer);
-+ }
-+ spin_unlock_irqrestore(&config_lock, flags);
-+
-+ return;
-+}
-+
-+EXPORT_SYMBOL_NOVERS(led_init);
-+EXPORT_SYMBOL_NOVERS(led_operation);
-+EXPORT_SYMBOL_NOVERS(register_led_drv);
-+EXPORT_SYMBOL_NOVERS(deregister_led_drv);
-diff -urN kernel-base/arch/mips/ar7/ar7/Makefile kernel-current/arch/mips/ar7/ar7/Makefile
---- kernel-base/arch/mips/ar7/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/ar7/Makefile 2005-07-10 09:31:33.038504888 +0200
-@@ -0,0 +1,31 @@
-+# $Id$
-+# Copyright (C) $Date$ $Author$
-+#
-+# This program is free software; you can redistribute it and/or modify
-+# it under the terms of the GNU General Public License as published by
-+# the Free Software Foundation; either version 2 of the License, or
-+# (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+
-+.S.s:
-+ $(CPP) $(AFLAGS) $< -o $*.s
-+
-+.S.o:
-+ $(CC) $(AFLAGS) -c $< -o $*.o
-+
-+EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
-+
-+O_TARGET := ar7.o
-+
-+export-objs:= ledmod.o gpio.o
-+obj-y += ar7_paging.o ar7_jump.o ledmod.o gpio.o tnetd73xx_misc.o
-+
-+include $(TOPDIR)/Rules.make
-diff -urN kernel-base/arch/mips/ar7/ar7/tnetd73xx_misc.c kernel-current/arch/mips/ar7/ar7/tnetd73xx_misc.c
---- kernel-base/arch/mips/ar7/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/ar7/tnetd73xx_misc.c 2005-07-10 09:57:09.935860976 +0200
-@@ -0,0 +1,926 @@
-+/******************************************************************************
-+ * FILE PURPOSE: TNETD73xx Misc modules API Source
-+ ******************************************************************************
-+ * FILE NAME: tnetd73xx_misc.c
-+ *
-+ * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
-+ * FSER Modules API
-+ * As per TNETD73xx specifications
-+ *
-+ * REVISION HISTORY:
-+ * 27 Nov 02 - Sharath Kumar PSP TII
-+ * 14 Feb 03 - Anant Gole PSP TII
-+ *
-+ * (C) Copyright 2002, Texas Instruments, Inc
-+ *******************************************************************************/
-+
-+
-+#include <linux/stddef.h>
-+#include <linux/types.h>
-+#include <asm/ar7/tnetd73xx.h>
-+#include <asm/ar7/tnetd73xx_misc.h>
-+
-+#define TRUE 1
-+#define FALSE 0
-+
-+/* TNETD73XX Revision */
-+__u32 tnetd73xx_get_revision(void)
-+{
-+ /* Read Chip revision register - This register is from GPIO module */
-+ return ( (__u32) REG32_DATA(TNETD73XX_CVR));
-+}
-+
-+/*****************************************************************************
-+ * Reset Control Module
-+ *****************************************************************************/
-+
-+
-+void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
-+{
-+ __u32 reset_status;
-+
-+ /* read current reset register */
-+ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
-+
-+ if (reset_ctrl == OUT_OF_RESET)
-+ {
-+ /* bring module out of reset */
-+ reset_status |= (1 << reset_module);
-+ }
-+ else
-+ {
-+ /* put module in reset */
-+ reset_status &= (~(1 << reset_module));
-+ }
-+
-+ /* write to the reset register */
-+ REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
-+}
-+
-+
-+TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
-+{
-+ __u32 reset_status;
-+
-+ REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
-+ return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
-+}
-+
-+void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
-+{
-+ REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
-+}
-+
-+#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
-+
-+TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
-+{
-+ __u32 sys_reset_status;
-+
-+ REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
-+
-+ return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
-+}
-+
-+
-+/*****************************************************************************
-+ * Power Control Module
-+ *****************************************************************************/
-+#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
-+#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
-+
-+
-+void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
-+{
-+ __u32 power_status;
-+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+
-+ if (power_ctrl == POWER_CTRL_POWER_DOWN)
-+ {
-+ /* power down the module */
-+ power_status |= (1 << power_module);
-+ }
-+ else
-+ {
-+ /* power on the module */
-+ power_status &= (~(1 << power_module));
-+ }
-+
-+ /* write to the reset register */
-+ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+}
-+
-+TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
-+{
-+ __u32 power_status;
-+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+
-+ return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
-+}
-+
-+void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
-+{
-+ __u32 power_status;
-+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+
-+ power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
-+ power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
-+
-+ /* write to power down control register */
-+ REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+}
-+
-+TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
-+{
-+ __u32 power_status;
-+
-+ /* read current power down control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
-+
-+ power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
-+ power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
-+
-+ return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
-+}
-+
-+
-+/*****************************************************************************
-+ * Wakeup Control
-+ *****************************************************************************/
-+
-+#define TNETD73XX_WAKEUP_POLARITY_BIT 16
-+
-+void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
-+ TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
-+ TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
-+{
-+ __u32 wakeup_status;
-+
-+ /* read the wakeup control register */
-+ REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
-+
-+ /* enable/disable */
-+ if (wakeup_ctrl == WAKEUP_ENABLED)
-+ {
-+ /* enable wakeup */
-+ wakeup_status |= wakeup_int;
-+ }
-+ else
-+ {
-+ /* disable wakeup */
-+ wakeup_status &= (~wakeup_int);
-+ }
-+
-+ /* set polarity */
-+ if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
-+ {
-+ wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
-+ }
-+ else
-+ {
-+ wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
-+ }
-+
-+ /* write the wakeup control register */
-+ REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
-+}
-+
-+
-+/*****************************************************************************
-+ * FSER Control
-+ *****************************************************************************/
-+
-+void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
-+{
-+ REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
-+}
-+
-+/*****************************************************************************
-+ * Clock Control
-+ *****************************************************************************/
-+
-+#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
-+#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
-+#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
-+#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
-+
-+#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
-+#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
-+
-+#define CLKC_PRE_DIVIDER 0x0000001F
-+#define CLKC_POST_DIVIDER 0x001F0000
-+
-+#define CLKC_PLL_STATUS 0x1
-+#define CLKC_PLL_FACTOR 0x0000F000
-+
-+#define BOOTCR_PLL_BYPASS (1 << 5)
-+#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
-+
-+#define MIPS_PLL_SELECT 0x00030000
-+#define SYSTEM_PLL_SELECT 0x0000C000
-+#define USB_PLL_SELECT 0x000C0000
-+#define ADSLSS_PLL_SELECT 0x00C00000
-+
-+#define MIPS_AFECLKI_SELECT 0x00000000
-+#define MIPS_REFCLKI_SELECT 0x00010000
-+#define MIPS_XTAL3IN_SELECT 0x00020000
-+
-+#define SYSTEM_AFECLKI_SELECT 0x00000000
-+#define SYSTEM_REFCLKI_SELECT 0x00004000
-+#define SYSTEM_XTAL3IN_SELECT 0x00008000
-+#define SYSTEM_MIPSPLL_SELECT 0x0000C000
-+
-+#define USB_SYSPLL_SELECT 0x00000000
-+#define USB_REFCLKI_SELECT 0x00040000
-+#define USB_XTAL3IN_SELECT 0x00080000
-+#define USB_MIPSPLL_SELECT 0x000C0000
-+
-+#define ADSLSS_AFECLKI_SELECT 0x00000000
-+#define ADSLSS_REFCLKI_SELECT 0x00400000
-+#define ADSLSS_XTAL3IN_SELECT 0x00800000
-+#define ADSLSS_MIPSPLL_SELECT 0x00C00000
-+
-+#define SYS_MAX CLK_MHZ(150)
-+#define SYS_MIN CLK_MHZ(1)
-+
-+#define MIPS_SYNC_MAX SYS_MAX
-+#define MIPS_ASYNC_MAX CLK_MHZ(160)
-+#define MIPS_MIN CLK_MHZ(1)
-+
-+#define USB_MAX CLK_MHZ(100)
-+#define USB_MIN CLK_MHZ(1)
-+
-+#define ADSL_MAX CLK_MHZ(180)
-+#define ADSL_MIN CLK_MHZ(1)
-+
-+#define PLL_MUL_MAXFACTOR 15
-+#define MAX_DIV_VALUE 32
-+#define MIN_DIV_VALUE 1
-+
-+#define MIN_PLL_INP_FREQ CLK_MHZ(8)
-+#define MAX_PLL_INP_FREQ CLK_MHZ(100)
-+
-+#define DIVIDER_LOCK_TIME 10100
-+#define PLL_LOCK_TIME 10100 * 75
-+
-+
-+
-+/****************************************************************************
-+ * DATA PURPOSE: PRIVATE Variables
-+ **************************************************************************/
-+static __u32 *clk_src[4];
-+static __u32 mips_pll_out;
-+static __u32 sys_pll_out;
-+static __u32 afeclk_inp;
-+static __u32 refclk_inp;
-+static __u32 xtal_inp;
-+static __u32 present_min;
-+static __u32 present_max;
-+
-+/* Forward References */
-+static __u32 find_gcd(__u32 min, __u32 max);
-+static __u32 compute_prediv( __u32 divider, __u32 min, __u32 max);
-+static void get_val(__u32 base_freq, __u32 output_freq,__u32 *multiplier, __u32 *divider);
-+static __u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
-+static void find_approx(__u32 *,__u32 *,__u32);
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_clkc_init
-+ ****************************************************************************
-+ * Description: The routine initializes the internal variables depending on
-+ * on the sources selected for different clocks.
-+ ***************************************************************************/
-+void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in)
-+{
-+
-+ __u32 choice;
-+
-+ afeclk_inp = afeclk;
-+ refclk_inp = refclk;
-+ xtal_inp = xtal3in;
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
-+ switch(choice)
-+ {
-+ case MIPS_AFECLKI_SELECT:
-+ clk_src[CLKC_MIPS] = &afeclk_inp;
-+ break;
-+
-+ case MIPS_REFCLKI_SELECT:
-+ clk_src[CLKC_MIPS] = &refclk_inp;
-+ break;
-+
-+ case MIPS_XTAL3IN_SELECT:
-+ clk_src[CLKC_MIPS] = &xtal_inp;
-+ break;
-+
-+ default :
-+ clk_src[CLKC_MIPS] = 0;
-+
-+ }
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
-+ switch(choice)
-+ {
-+ case SYSTEM_AFECLKI_SELECT:
-+ clk_src[CLKC_SYS] = &afeclk_inp;
-+ break;
-+
-+ case SYSTEM_REFCLKI_SELECT:
-+ clk_src[CLKC_SYS] = &refclk_inp;
-+ break;
-+
-+ case SYSTEM_XTAL3IN_SELECT:
-+ clk_src[CLKC_SYS] = &xtal_inp;
-+ break;
-+
-+ case SYSTEM_MIPSPLL_SELECT:
-+ clk_src[CLKC_SYS] = &mips_pll_out;
-+ break;
-+
-+ default :
-+ clk_src[CLKC_SYS] = 0;
-+
-+ }
-+
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
-+ switch(choice)
-+ {
-+ case ADSLSS_AFECLKI_SELECT:
-+ clk_src[CLKC_ADSLSS] = &afeclk_inp;
-+ break;
-+
-+ case ADSLSS_REFCLKI_SELECT:
-+ clk_src[CLKC_ADSLSS] = &refclk_inp;
-+ break;
-+
-+ case ADSLSS_XTAL3IN_SELECT:
-+ clk_src[CLKC_ADSLSS] = &xtal_inp;
-+ break;
-+
-+ case ADSLSS_MIPSPLL_SELECT:
-+ clk_src[CLKC_ADSLSS] = &mips_pll_out;
-+ break;
-+
-+ default :
-+ clk_src[CLKC_ADSLSS] = 0;
-+
-+ }
-+
-+
-+ choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
-+ switch(choice)
-+ {
-+ case USB_SYSPLL_SELECT:
-+ clk_src[CLKC_USB] = &sys_pll_out ;
-+ break;
-+
-+ case USB_REFCLKI_SELECT:
-+ clk_src[CLKC_USB] = &refclk_inp;
-+ break;
-+
-+ case USB_XTAL3IN_SELECT:
-+ clk_src[CLKC_USB] = &xtal_inp;
-+ break;
-+
-+ case USB_MIPSPLL_SELECT:
-+ clk_src[CLKC_USB] = &mips_pll_out;
-+ break;
-+
-+ default :
-+ clk_src[CLKC_USB] = 0;
-+
-+ }
-+}
-+
-+
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_clkc_set_freq
-+ ****************************************************************************
-+ * Description: The above routine is called to set the output_frequency of the
-+ * selected clock(using clk_id) to the required value given
-+ * by the variable output_freq.
-+ ***************************************************************************/
-+TNETD73XX_ERR tnetd73xx_clkc_set_freq
-+(
-+ TNETD73XX_CLKC_ID_T clk_id,
-+ __u32 output_freq
-+)
-+{
-+ __u32 base_freq;
-+ __u32 multiplier;
-+ __u32 divider;
-+ __u32 min_prediv;
-+ __u32 max_prediv;
-+ __u32 prediv;
-+ __u32 postdiv;
-+ __u32 temp;
-+
-+ /* check if PLLs are bypassed*/
-+ if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+
-+ /*check if the requested output_frequency is in valid range*/
-+ switch( clk_id )
-+ {
-+ case CLKC_SYS:
-+ if( output_freq < SYS_MIN || output_freq > SYS_MAX)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = SYS_MIN;
-+ present_max = SYS_MAX;
-+ break;
-+
-+ case CLKC_MIPS:
-+ if((output_freq < MIPS_MIN) ||
-+ (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = MIPS_MIN;
-+ present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
-+ break;
-+
-+ case CLKC_USB:
-+ if( output_freq < USB_MIN || output_freq > USB_MAX)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = USB_MIN;
-+ present_max = USB_MAX;
-+ break;
-+
-+ case CLKC_ADSLSS:
-+ if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+ present_min = ADSL_MIN;
-+ present_max = ADSL_MAX;
-+ break;
-+ }
-+
-+
-+ base_freq = get_base_frequency(clk_id);
-+
-+
-+ /* check for minimum base frequency value */
-+ if( base_freq < MIN_PLL_INP_FREQ)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+
-+ get_val(output_freq, base_freq, &multiplier, ÷r);
-+
-+ /* check multiplier range */
-+ if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+
-+ /* check divider value */
-+ if( divider == 0 )
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+
-+ /*compute minimum and maximum predivider values */
-+ min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
-+ max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
-+
-+ /*adjust the value of divider so that it not less than minimum predivider value*/
-+ if (divider < min_prediv)
-+ {
-+ temp = CEIL(min_prediv, divider);
-+ if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
-+ {
-+ return TNETD73XX_ERR_ERROR ;
-+ }
-+ else
-+ {
-+ multiplier = temp * multiplier;
-+ divider = min_prediv;
-+ }
-+
-+ }
-+
-+ /* compute predivider and postdivider values */
-+ prediv = compute_prediv (divider, min_prediv, max_prediv);
-+ postdiv = CEIL(divider,prediv);
-+
-+ /*return fail if postdivider value falls out of range */
-+ if(postdiv > MAX_DIV_VALUE)
-+ {
-+ return TNETD73XX_ERR_ERROR;
-+ }
-+
-+
-+ /*write predivider and postdivider values*/
-+ /* pre-Divider and post-divider are 5 bit N+1 dividers */
-+ REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
-+
-+ /*wait for divider output to stabilise*/
-+ for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
-+
-+ /*write to PLL clock register*/
-+
-+ if(clk_id == CLKC_SYS)
-+ {
-+ /* but before writing put DRAM to hold mode */
-+ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
-+ }
-+ /*Bring PLL into div mode */
-+ REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
-+
-+ /*compute the word to be written to PLLCR
-+ *corresponding to multiplier value
-+ */
-+ multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
-+
-+ /* wait till PLL enters div mode */
-+ while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
-+ /*nothing*/;
-+
-+ REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
-+
-+ while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
-+ /*nothing*/;
-+
-+
-+ /*wait for External pll to lock*/
-+ for(temp =0; temp < PLL_LOCK_TIME; temp++);
-+
-+ if(clk_id == CLKC_SYS)
-+ {
-+ /* Bring DRAM out of hold */
-+ REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
-+ }
-+
-+ return TNETD73XX_ERR_OK ;
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_clkc_get_freq
-+ ****************************************************************************
-+ * Description: The above routine is called to get the output_frequency of the
-+ * selected clock( clk_id)
-+ ***************************************************************************/
-+__u32 tnetd73xx_clkc_get_freq
-+(
-+ TNETD73XX_CLKC_ID_T clk_id
-+)
-+{
-+
-+ __u32 clk_ctrl_register;
-+ __u32 clk_pll_setting;
-+ __u32 clk_predivider;
-+ __u32 clk_postdivider;
-+ __u16 pll_factor;
-+ __u32 base_freq;
-+ __u32 divider;
-+
-+ base_freq = get_base_frequency(clk_id);
-+
-+ clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
-+
-+ /* pre-Divider and post-divider are 5 bit N+1 dividers */
-+ clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
-+ clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
-+
-+ divider = clk_predivider * clk_postdivider;
-+
-+
-+ if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
-+ {
-+ return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
-+ }
-+
-+
-+ else
-+ {
-+ /* return the current clock speed based upon the PLL setting */
-+ clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
-+
-+ /* Get the PLL multiplication factor */
-+ pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
-+
-+ /* Check if we're in divide mode or multiply mode */
-+ if((clk_pll_setting & 0x1) == 0)
-+ {
-+ /* We're in divide mode */
-+ if(pll_factor < 0x10)
-+ return (CEIL(base_freq >> 1, divider));
-+ else
-+ return (CEIL(base_freq >> 2, divider));
-+ }
-+
-+ else /* We're in PLL mode */
-+ {
-+ /* See if PLLNDIV & PLLDIV are set */
-+ if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
-+ {
-+ if(clk_pll_setting & 0x1000)
-+ {
-+ /* clk = base_freq * k/2 */
-+ return(CEIL((base_freq * pll_factor) >> 1, divider));
-+ }
-+ else
-+ {
-+ /* clk = base_freq * (k-1) / 4)*/
-+ return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
-+ }
-+ }
-+ else
-+ {
-+ if(pll_factor < 0x10)
-+ {
-+ /* clk = base_freq * k */
-+ return(CEIL(base_freq * pll_factor, divider));
-+ }
-+
-+ else
-+ {
-+ /* clk = base_freq */
-+ return(CEIL(base_freq, divider));
-+ }
-+ }
-+ }
-+ return(0); /* Should never reach here */
-+
-+ }
-+
-+}
-+
-+
-+/* local helper functions */
-+
-+ /****************************************************************************
-+ * FUNCTION: get_base_frequency
-+ ****************************************************************************
-+ * Description: The above routine is called to get base frequency of the clocks.
-+ ***************************************************************************/
-+
-+static __u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
-+{
-+ /* update the current MIPs PLL output value, if the required
-+ * source is MIPS PLL
-+ */
-+ if ( clk_src[clk_id] == &mips_pll_out)
-+ {
-+ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
-+ }
-+
-+
-+ /* update the current System PLL output value, if the required
-+ * source is system PLL
-+ */
-+ if ( clk_src[clk_id] == &sys_pll_out)
-+ {
-+ *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
-+ }
-+
-+ return (*clk_src[clk_id]);
-+
-+}
-+
-+
-+
-+/****************************************************************************
-+ * FUNCTION: find_gcd
-+ ****************************************************************************
-+ * Description: The above routine is called to find gcd of 2 numbers.
-+ ***************************************************************************/
-+static __u32 find_gcd
-+(
-+__u32 min,
-+__u32 max
-+)
-+{
-+ if (max % min == 0)
-+ {
-+ return min;
-+ }
-+ else
-+ {
-+ return find_gcd(max % min, min);
-+ }
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: compute_prediv
-+ ****************************************************************************
-+ * Description: The above routine is called to compute predivider value
-+ ***************************************************************************/
-+static __u32 compute_prediv(__u32 divider, __u32 min, __u32 max)
-+{
-+__u16 prediv;
-+
-+/* return the divider itself it it falls within the range of predivider*/
-+if (min <= divider && divider <= max)
-+{
-+ return divider;
-+}
-+
-+/* find a value for prediv such that it is a factor of divider */
-+for (prediv = max; prediv >= min ; prediv--)
-+{
-+ if ( (divider % prediv) == 0 )
-+ {
-+ return prediv;
-+ }
-+}
-+
-+/* No such factor exists, return min as prediv */
-+return min;
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: get_val
-+ ****************************************************************************
-+ * Description: This routine is called to get values of divider and multiplier.
-+ ***************************************************************************/
++ max_low_pfn = max_pfn;
+
-+static void get_val(__u32 output_freq, __u32 base_freq,__u32 *multiplier, __u32 *divider)
-+{
-+ __u32 temp_mul;
-+ __u32 temp_div;
-+ __u32 gcd;
-+ __u32 min_freq;
-+ __u32 max_freq;
++ /*
++ * Partially used pages are not usable - thus we are
++ * rounding upwards:
++ */
+
-+ /* find gcd of base_freq, output_freq */
-+ min_freq = (base_freq < output_freq) ? base_freq : output_freq;
-+ max_freq = (base_freq > output_freq) ? base_freq : output_freq;
-+ gcd = find_gcd(min_freq , max_freq);
++ start_pfn = PFN_UP(__pa(&_end));
+
-+ if(gcd == 0)
-+ return; /* ERROR */
++ /*
++ * Find a proper area for the bootmem bitmap. After this
++ * bootstrap step all allocations (until the page allocator is
++ * intact) must be done via bootmem_alloc().
++ */
+
-+ /* compute values of multiplier and divider */
-+ temp_mul = output_freq / gcd;
-+ temp_div = base_freq / gcd;
++ bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
++ __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
+
+
-+ /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
-+ if( temp_mul > PLL_MUL_MAXFACTOR )
-+ {
-+ if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
-+ return;
++ /*
++ * Register fully available low RAM pages with the bootmem allocator.
++ */
+
-+ find_approx(&temp_mul,&temp_div,base_freq);
-+ }
++ {
++ unsigned long curr_pfn, last_pfn, pages;
+
-+ *multiplier = temp_mul;
-+ *divider = temp_div;
-+}
++ /*
++ * We are rounding up the start address of usable memory:
++ */
++ curr_pfn = PFN_UP(__MEMORY_START);
+
-+/****************************************************************************
-+ * FUNCTION: find_approx
-+ ****************************************************************************
-+ * Description: This function gets the approx value of num/denom.
-+ ***************************************************************************/
++ /*
++ * ... and at the end of the usable range downwards:
++ */
++ last_pfn = PFN_DOWN(__pa(memory_end));
+
-+static void find_approx(__u32 *num,__u32 *denom,__u32 base_freq)
-+{
-+ __u32 num1;
-+ __u32 denom1;
-+ __u32 num2;
-+ __u32 denom2;
-+ int closest;
-+ int prev_closest;
-+ __u32 temp_num;
-+ __u32 temp_denom;
-+ __u32 normalize;
-+ __u32 gcd;
-+ __u32 output_freq;
-+
-+ num1 = *num;
-+ denom1 = *denom;
-+
-+ prev_closest = 0x7fffffff; /* maximum possible value */
-+ num2 = num1;
-+ denom2 = denom1;
-+
-+ /* start with max */
-+ for(temp_num = 15; temp_num >=1; temp_num--)
-+ {
++ if (last_pfn > max_low_pfn)
++ last_pfn = max_low_pfn;
+
-+ temp_denom = CEIL(temp_num * denom1, num1);
-+ output_freq = (temp_num * base_freq) / temp_denom;
++ pages = last_pfn - curr_pfn;
+
-+ if(temp_denom < 1)
-+ {
-+ break;
-+ }
-+ else
-+ {
-+ normalize = CEIL(num1,temp_num);
-+ closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
-+ if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
-+ {
-+ prev_closest = closest;
-+ num2 = temp_num;
-+ denom2 = temp_denom;
-+ }
-+
-+ }
+
-+ }
++ free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
++ PFN_PHYS(pages));
++ }
+
-+ gcd = find_gcd(num2,denom2);
-+ num2 = num2 / gcd;
-+ denom2 = denom2 /gcd;
++ /*
++ * Reserve the kernel text and
++ * Reserve the bootmem bitmap. We do this in two steps (first step
++ * was init_bootmem()), because this catches the (definitely buggy)
++ * case of us accidentally initializing the bootmem allocator with
++ * an invalid RAM area.
++ */
++ reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
++ (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
+
-+ *num = num2;
-+ *denom = denom2;
++ /*
++ * reserve physical page 0 - it's a special BIOS page on many boxes,
++ * enabling clean reboots, SMP operation, laptop functions.
++ */
++ reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
+}
+
++extern char __init_begin, __init_end;
+
-+/*****************************************************************************
-+ * GPIO Control
-+ *****************************************************************************/
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_init
-+ ***************************************************************************/
-+void tnetd73xx_gpio_init()
++void free_initmem(void)
+{
-+ /* Bring module out of reset */
-+ tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
-+ REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
-+}
++ unsigned long addr;
++ // prom_free_prom_memory ();
+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_ctrl
-+ ***************************************************************************/
-+void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
-+ TNETD73XX_GPIO_PIN_MODE_T pin_mode,
-+ TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
-+{
-+ __u32 pin_status;
-+ REG32_READ(TNETD73XX_GPIOENR, pin_status);
-+ if (pin_mode == GPIO_PIN)
-+ {
-+ pin_status |= (1 << gpio_pin);
-+ REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
-+
-+ /* Set pin direction */
-+ REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
-+ if (pin_direction == GPIO_INPUT_PIN)
-+ {
-+ pin_status |= (1 << gpio_pin);
-+ }
-+ else /* GPIO_OUTPUT_PIN */
-+ {
-+ pin_status &= (~(1 << gpio_pin));
-+ }
-+ REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
-+ }
-+ else /* FUNCTIONAL PIN */
-+ {
-+ pin_status &= (~(1 << gpio_pin));
-+ REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
-+ }
-+
-+}
-+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_out
-+ ***************************************************************************/
-+void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
-+{
-+ __u32 pin_value;
-+
-+ REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
-+ if (value == TRUE)
-+ {
-+ pin_value |= (1 << gpio_pin);
-+ }
-+ else
-+ {
-+ pin_value &= (~(1 << gpio_pin));
-+ }
-+ REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
++ addr = (unsigned long) &__init_begin;
++ while (addr < (unsigned long) &__init_end) {
++ ClearPageReserved(virt_to_page(addr));
++ set_page_count(virt_to_page(addr), 1);
++ free_page(addr);
++ totalram_pages++;
++ addr += PAGE_SIZE;
++ }
++ printk("Freeing unused kernel memory: %dk freed\n",
++ (&__init_end - &__init_begin) >> 10);
+}
+
-+/****************************************************************************
-+ * FUNCTION: tnetd73xx_gpio_in
-+ ***************************************************************************/
-+int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
++void si_meminfo(struct sysinfo *val)
+{
-+ __u32 pin_value;
-+ REG32_READ(TNETD73XX_GPIODINR, pin_value);
-+ return ( (pin_value & (1 << gpio_pin)) ? TRUE : FALSE );
-+}
++ val->totalram = totalram_pages;
++ val->sharedram = 0;
++ val->freeram = nr_free_pages();
++ val->bufferram = atomic_read(&buffermem_pages);
++ val->totalhigh = 0;
++ val->freehigh = nr_free_highpages();
++ val->mem_unit = PAGE_SIZE;
+
++ return;
++}
diff -urN kernel-base/arch/mips/ar7/cmdline.c kernel-current/arch/mips/ar7/cmdline.c
--- kernel-base/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/cmdline.c 2005-07-10 06:40:39.584266864 +0200
++++ kernel-current/arch/mips/ar7/cmdline.c 2005-07-10 06:40:39.584266000 +0200
@@ -0,0 +1,64 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+}
diff -urN kernel-base/arch/mips/ar7/init.c kernel-current/arch/mips/ar7/init.c
--- kernel-base/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/init.c 2005-07-10 06:40:39.584266864 +0200
-@@ -0,0 +1,146 @@
++++ kernel-current/arch/mips/ar7/init.c 2005-07-10 17:53:38.565319696 +0200
+@@ -0,0 +1,144 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
+
+ return 0;
+}
-+
-+EXPORT_SYMBOL(prom_getenv);
diff -urN kernel-base/arch/mips/ar7/irq.c kernel-current/arch/mips/ar7/irq.c
--- kernel-base/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/irq.c 2005-07-10 10:02:30.212171576 +0200
++++ kernel-current/arch/mips/ar7/irq.c 2005-07-10 17:53:17.841470200 +0200
@@ -0,0 +1,705 @@
+/*
+ * Nitin Dhingra, iamnd@ti.com
+}
diff -urN kernel-base/arch/mips/ar7/Makefile kernel-current/arch/mips/ar7/Makefile
--- kernel-base/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/Makefile 2005-07-10 08:23:55.081408136 +0200
-@@ -0,0 +1,29 @@
++++ kernel-current/arch/mips/ar7/Makefile 2005-07-10 17:53:46.635092904 +0200
+@@ -0,0 +1,28 @@
+# $Id$
+# Copyright (C) $Date$ $Author$
+#
+
+O_TARGET := ar7.o
+
-+export-objs := init.o irq.o
+obj-y := setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
+
+include $(TOPDIR)/Rules.make
diff -urN kernel-base/arch/mips/ar7/memory.c kernel-current/arch/mips/ar7/memory.c
--- kernel-base/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/memory.c 2005-07-10 06:40:39.586266560 +0200
++++ kernel-current/arch/mips/ar7/memory.c 2005-07-10 06:40:39.586266000 +0200
@@ -0,0 +1,130 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+}
diff -urN kernel-base/arch/mips/ar7/mipsIRQ.S kernel-current/arch/mips/ar7/mipsIRQ.S
--- kernel-base/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/mipsIRQ.S 2005-07-10 06:40:39.587266408 +0200
++++ kernel-current/arch/mips/ar7/mipsIRQ.S 2005-07-10 06:40:39.587266000 +0200
@@ -0,0 +1,120 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+END(mipsIRQ)
diff -urN kernel-base/arch/mips/ar7/printf.c kernel-current/arch/mips/ar7/printf.c
--- kernel-base/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/printf.c 2005-07-10 06:40:39.587266408 +0200
++++ kernel-current/arch/mips/ar7/printf.c 2005-07-10 06:40:39.587266000 +0200
@@ -0,0 +1,54 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+}
diff -urN kernel-base/arch/mips/ar7/reset.c kernel-current/arch/mips/ar7/reset.c
--- kernel-base/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/reset.c 2005-07-10 06:40:39.587266408 +0200
++++ kernel-current/arch/mips/ar7/reset.c 2005-07-10 06:40:39.587266000 +0200
@@ -0,0 +1,54 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+}
diff -urN kernel-base/arch/mips/ar7/setup.c kernel-current/arch/mips/ar7/setup.c
--- kernel-base/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/setup.c 2005-07-10 06:40:39.588266256 +0200
++++ kernel-current/arch/mips/ar7/setup.c 2005-07-10 06:40:39.588266000 +0200
@@ -0,0 +1,120 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+}
diff -urN kernel-base/arch/mips/ar7/time.c kernel-current/arch/mips/ar7/time.c
--- kernel-base/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/arch/mips/ar7/time.c 2005-07-10 06:40:39.588266256 +0200
++++ kernel-current/arch/mips/ar7/time.c 2005-07-10 06:40:39.588266000 +0200
@@ -0,0 +1,125 @@
+/*
+ * Carsten Langgaard, carstenl@mips.com
+}
diff -urN kernel-base/arch/mips/config-shared.in kernel-current/arch/mips/config-shared.in
--- kernel-base/arch/mips/config-shared.in 2005-07-10 03:00:44.784181376 +0200
-+++ kernel-current/arch/mips/config-shared.in 2005-07-10 06:40:39.589266104 +0200
++++ kernel-current/arch/mips/config-shared.in 2005-07-10 06:40:39.589266000 +0200
@@ -20,6 +20,16 @@
mainmenu_option next_comment
comment 'Machine selection'
"$CONFIG_IBM_WORKPAD" = "y" -o \
diff -urN kernel-base/arch/mips/kernel/irq.c kernel-current/arch/mips/kernel/irq.c
--- kernel-base/arch/mips/kernel/irq.c 2005-07-10 03:00:44.784181376 +0200
-+++ kernel-current/arch/mips/kernel/irq.c 2005-07-10 06:40:39.589266104 +0200
++++ kernel-current/arch/mips/kernel/irq.c 2005-07-10 06:40:39.589266000 +0200
@@ -76,6 +76,7 @@
* Generic, controller-independent functions:
*/
* IRQ autodetection code..
diff -urN kernel-base/arch/mips/kernel/mips_ksyms.c kernel-current/arch/mips/kernel/mips_ksyms.c
--- kernel-base/arch/mips/kernel/mips_ksyms.c 2004-02-18 14:36:30.000000000 +0100
-+++ kernel-current/arch/mips/kernel/mips_ksyms.c 2005-07-10 10:08:15.469684456 +0200
-@@ -40,6 +40,10 @@
++++ kernel-current/arch/mips/kernel/mips_ksyms.c 2005-07-10 17:55:55.738466208 +0200
+@@ -40,6 +40,12 @@
extern long __strnlen_user_nocheck_asm(const char *s);
extern long __strnlen_user_asm(const char *s);
+#ifdef CONFIG_AR7
-+extern int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
++int avalanche_request_pacing(int irq_nr, unsigned int blk_num, unsigned int pace_value);
++char *prom_getenv(char *envname);
+#endif
++
+
EXPORT_SYMBOL(mips_machtype);
#ifdef CONFIG_EISA
EXPORT_SYMBOL(EISA_bus);
-@@ -102,4 +106,8 @@
- EXPORT_SYMBOL(ide_ops);
+@@ -103,3 +109,9 @@
#endif
+ EXPORT_SYMBOL(get_wchan);
++
+#ifdef CONFIG_AR7
+EXPORT_SYMBOL_NOVERS(avalanche_request_pacing);
++EXPORT_SYMBOL_NOVERS(prom_getenv);
+#endif
+
- EXPORT_SYMBOL(get_wchan);
diff -urN kernel-base/arch/mips/kernel/setup.c kernel-current/arch/mips/kernel/setup.c
--- kernel-base/arch/mips/kernel/setup.c 2005-07-10 03:00:44.785181224 +0200
-+++ kernel-current/arch/mips/kernel/setup.c 2005-07-10 06:40:39.590265952 +0200
++++ kernel-current/arch/mips/kernel/setup.c 2005-07-10 06:40:39.590265000 +0200
@@ -109,6 +109,7 @@
unsigned long isa_slot_offset;
EXPORT_SYMBOL(isa_slot_offset);
}
diff -urN kernel-base/arch/mips/kernel/traps.c kernel-current/arch/mips/kernel/traps.c
--- kernel-base/arch/mips/kernel/traps.c 2005-07-10 03:00:44.786181072 +0200
-+++ kernel-current/arch/mips/kernel/traps.c 2005-07-10 06:40:39.591265800 +0200
++++ kernel-current/arch/mips/kernel/traps.c 2005-07-10 06:40:39.591265000 +0200
@@ -40,6 +40,10 @@
#include <asm/uaccess.h>
#include <asm/mmu_context.h>
}
diff -urN kernel-base/arch/mips/lib/promlib.c kernel-current/arch/mips/lib/promlib.c
--- kernel-base/arch/mips/lib/promlib.c 2005-07-10 03:00:44.786181072 +0200
-+++ kernel-current/arch/mips/lib/promlib.c 2005-07-10 06:40:39.591265800 +0200
++++ kernel-current/arch/mips/lib/promlib.c 2005-07-10 06:40:39.591265000 +0200
@@ -1,3 +1,4 @@
+#ifndef CONFIG_AR7
#include <stdarg.h>
+#endif
diff -urN kernel-base/arch/mips/Makefile kernel-current/arch/mips/Makefile
--- kernel-base/arch/mips/Makefile 2005-07-10 03:00:44.786181072 +0200
-+++ kernel-current/arch/mips/Makefile 2005-07-10 06:40:39.591265800 +0200
++++ kernel-current/arch/mips/Makefile 2005-07-10 06:40:39.591265000 +0200
@@ -369,6 +369,16 @@
endif
ifdef CONFIG_DECSTATION
diff -urN kernel-base/arch/mips/mm/init.c kernel-current/arch/mips/mm/init.c
--- kernel-base/arch/mips/mm/init.c 2005-07-10 03:00:44.787180920 +0200
-+++ kernel-current/arch/mips/mm/init.c 2005-07-10 07:09:29.914216728 +0200
++++ kernel-current/arch/mips/mm/init.c 2005-07-10 07:09:29.914216000 +0200
@@ -40,8 +40,10 @@
mmu_gather_t mmu_gathers[NR_CPUS];
+#endif
diff -urN kernel-base/arch/mips/mm/tlb-r4k.c kernel-current/arch/mips/mm/tlb-r4k.c
--- kernel-base/arch/mips/mm/tlb-r4k.c 2005-07-10 03:00:44.787180920 +0200
-+++ kernel-current/arch/mips/mm/tlb-r4k.c 2005-07-10 06:40:39.592265648 +0200
++++ kernel-current/arch/mips/mm/tlb-r4k.c 2005-07-10 06:40:39.592265000 +0200
@@ -20,6 +20,10 @@
#include <asm/pgtable.h>
#include <asm/system.h>
}
diff -urN kernel-base/drivers/char/serial.c kernel-current/drivers/char/serial.c
--- kernel-base/drivers/char/serial.c 2005-07-10 03:00:44.789180616 +0200
-+++ kernel-current/drivers/char/serial.c 2005-07-10 06:42:02.902600552 +0200
++++ kernel-current/drivers/char/serial.c 2005-07-10 06:42:02.902600000 +0200
@@ -419,7 +419,40 @@
return 0;
}
cval >>= 8;
diff -urN kernel-base/include/asm-mips/ar7/ar7.h kernel-current/include/asm-mips/ar7/ar7.h
--- kernel-base/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/include/asm-mips/ar7/ar7.h 2005-07-10 06:40:39.622261088 +0200
++++ kernel-current/include/asm-mips/ar7/ar7.h 2005-07-10 06:40:39.622261000 +0200
@@ -0,0 +1,33 @@
+/*
+ * $Id$
+#endif
diff -urN kernel-base/include/asm-mips/ar7/avalanche_intc.h kernel-current/include/asm-mips/ar7/avalanche_intc.h
--- kernel-base/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/include/asm-mips/ar7/avalanche_intc.h 2005-07-10 06:40:39.622261088 +0200
++++ kernel-current/include/asm-mips/ar7/avalanche_intc.h 2005-07-10 06:40:39.622261000 +0200
@@ -0,0 +1,278 @@
+ /*
+ * Nitin Dhingra, iamnd@ti.com
+};
+
+
-+/* Interrupt Line #'s (Sangam peripherals) */
++/* Interrupt Line #'s (Sangam peripherals) */
++
++/*------------------------------*/
++/* Sangam primary interrupts */
++/*------------------------------*/
++
++#define UNIFIED_SECONDARY_INTERRUPT 0
++#define AVALANCHE_EXT_INT_0 1
++#define AVALANCHE_EXT_INT_1 2
++/* Line #3 Reserved */
++/* Line #4 Reserved */
++#define AVALANCHE_TIMER_0_INT 5
++#define AVALANCHE_TIMER_1_INT 6
++#define AVALANCHE_UART0_INT 7
++#define AVALANCHE_UART1_INT 8
++#define AVALANCHE_PDMA_INT0 9
++#define AVALANCHE_PDMA_INT1 10
++/* Line #11 Reserved */
++/* Line #12 Reserved */
++/* Line #13 Reserved */
++/* Line #14 Reserved */
++#define AVALANCHE_ATM_SAR_INT 15
++/* Line #16 Reserved */
++/* Line #17 Reserved */
++/* Line #18 Reserved */
++#define AVALANCHE_MAC0_INT 19
++/* Line #20 Reserved */
++#define AVALANCHE_VLYNQ0_INT 21
++#define AVALANCHE_CODEC_WAKE_INT 22
++/* Line #23 Reserved */
++#define AVALANCHE_USB_INT 24
++#define AVALANCHE_VLYNQ1_INT 25
++/* Line #26 Reserved */
++/* Line #27 Reserved */
++#define AVALANCHE_MAC1_INT 28
++#define AVALANCHE_I2CM_INT 29
++#define AVALANCHE_PDMA_INT2 30
++#define AVALANCHE_PDMA_INT3 31
++/* Line #32 Reserved */
++/* Line #33 Reserved */
++/* Line #34 Reserved */
++/* Line #35 Reserved */
++/* Line #36 Reserved */
++#define AVALANCHE_VDMA_VT_RX_INT 37
++#define AVALANCHE_VDMA_VT_TX_INT 38
++#define AVALANCHE_ADSLSS_INT 39
++
++/*-----------------------------------*/
++/* Sangam Secondary Interrupts */
++/*-----------------------------------*/
++#define PRIMARY_INTS 40
++
++#define EMIF_INT (7 + PRIMARY_INTS)
++
++
++extern void avalanche_int_set(int channel, int line);
++
++
++#endif /* _AVALANCHE_INTC_H */
+diff -urN kernel-base/include/asm-mips/ar7/avalanche_misc.h kernel-current/include/asm-mips/ar7/avalanche_misc.h
+--- kernel-base/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100
++++ kernel-current/include/asm-mips/ar7/avalanche_misc.h 2005-07-10 18:45:35.089287296 +0200
+@@ -0,0 +1,174 @@
++#ifndef _AVALANCHE_MISC_H_
++#define _AVALANCHE_MISC_H_
++
++typedef enum AVALANCHE_ERR_t
++{
++ AVALANCHE_ERR_OK = 0, /* OK or SUCCESS */
++ AVALANCHE_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
++
++ /* Pointers and args */
++ AVALANCHE_ERR_INVARG = -2, /* Invaild argument to the call */
++ AVALANCHE_ERR_NULLPTR = -3, /* NULL pointer */
++ AVALANCHE_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
++
++ /* Memory issues */
++ AVALANCHE_ERR_ALLOC_FAIL = -10, /* allocation failed */
++ AVALANCHE_ERR_FREE_FAIL = -11, /* free failed */
++ AVALANCHE_ERR_MEM_CORRUPT = -12, /* corrupted memory */
++ AVALANCHE_ERR_BUF_LINK = -13, /* buffer linking failed */
++
++ /* Device issues */
++ AVALANCHE_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
++ AVALANCHE_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
++
++ AVALANCHE_ERR_INVID = -30 /* Invalid ID */
++
++} AVALANCHE_ERR;
++
++/*****************************************************************************
++ * Reset Control Module
++ *****************************************************************************/
++
++typedef enum AVALANCHE_RESET_MODULE_tag
++{
++ RESET_MODULE_UART0 = 0,
++ RESET_MODULE_UART1 = 1,
++ RESET_MODULE_I2C = 2,
++ RESET_MODULE_TIMER0 = 3,
++ RESET_MODULE_TIMER1 = 4,
++ RESET_MODULE_GPIO = 6,
++ RESET_MODULE_ADSLSS = 7,
++ RESET_MODULE_USBS = 8,
++ RESET_MODULE_SAR = 9,
++ RESET_MODULE_VDMA_VT = 11,
++ RESET_MODULE_FSER = 12,
++ RESET_MODULE_VLYNQ1 = 16,
++ RESET_MODULE_EMAC0 = 17,
++ RESET_MODULE_DMA = 18,
++ RESET_MODULE_BIST = 19,
++ RESET_MODULE_VLYNQ0 = 20,
++ RESET_MODULE_EMAC1 = 21,
++ RESET_MODULE_MDIO = 22,
++ RESET_MODULE_ADSLSS_DSP = 23,
++ RESET_MODULE_EPHY = 26
++} AVALANCHE_RESET_MODULE_T;
++
++typedef enum AVALANCHE_RESET_CTRL_tag
++{
++ IN_RESET = 0,
++ OUT_OF_RESET
++} AVALANCHE_RESET_CTRL_T;
++
++typedef enum AVALANCHE_SYS_RST_MODE_tag
++{
++ RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
++ RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
++} AVALANCHE_SYS_RST_MODE_T;
++
++typedef enum AVALANCHE_SYS_RESET_STATUS_tag
++{
++ HARDWARE_RESET = 0,
++ SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
++ WATCHDOG_RESET,
++ SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
++} AVALANCHE_SYS_RESET_STATUS_T;
++
++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(AVALANCHE_RESET_MODULE_T reset_module);
++void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
++AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
++
++typedef int (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, AVALANCHE_RESET_CTRL_T reset_ctrl);
++
++/*****************************************************************************
++ * Power Control Module
++ *****************************************************************************/
++
++typedef enum AVALANCHE_POWER_CTRL_tag
++{
++ POWER_CTRL_POWER_UP = 0,
++ POWER_CTRL_POWER_DOWN
++} AVALANCHE_POWER_CTRL_T;
++
++typedef enum AVALANCHE_SYS_POWER_MODE_tag
++{
++ GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
++ GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
++ GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
++ GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
++} AVALANCHE_SYS_POWER_MODE_T;
++
++void avalanche_power_ctrl(unsigned int power_module, AVALANCHE_POWER_CTRL_T power_ctrl);
++AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
++void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
++AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);
++
++/*****************************************************************************
++ * Wakeup Control
++ *****************************************************************************/
++
++typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
++{
++ WAKEUP_INT0 = 1,
++ WAKEUP_INT1 = 2,
++ WAKEUP_INT2 = 4,
++ WAKEUP_INT3 = 8
++} AVALANCHE_WAKEUP_INTERRUPT_T;
++
++typedef enum TNETV1050_WAKEUP_CTRL_tag
++{
++ WAKEUP_DISABLED = 0,
++ WAKEUP_ENABLED
++} AVALANCHE_WAKEUP_CTRL_T;
++
++typedef enum TNETV1050_WAKEUP_POLARITY_tag
++{
++ WAKEUP_ACTIVE_HIGH = 0,
++ WAKEUP_ACTIVE_LOW
++} AVALANCHE_WAKEUP_POLARITY_T;
++
++void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
++ AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
++ AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
+
-+/*------------------------------*/
-+/* Sangam primary interrupts */
-+/*------------------------------*/
++/*****************************************************************************
++ * GPIO Control
++ *****************************************************************************/
+
-+#define UNIFIED_SECONDARY_INTERRUPT 0
-+#define AVALANCHE_EXT_INT_0 1
-+#define AVALANCHE_EXT_INT_1 2
-+/* Line #3 Reserved */
-+/* Line #4 Reserved */
-+#define AVALANCHE_TIMER_0_INT 5
-+#define AVALANCHE_TIMER_1_INT 6
-+#define AVALANCHE_UART0_INT 7
-+#define AVALANCHE_UART1_INT 8
-+#define AVALANCHE_PDMA_INT0 9
-+#define AVALANCHE_PDMA_INT1 10
-+/* Line #11 Reserved */
-+/* Line #12 Reserved */
-+/* Line #13 Reserved */
-+/* Line #14 Reserved */
-+#define AVALANCHE_ATM_SAR_INT 15
-+/* Line #16 Reserved */
-+/* Line #17 Reserved */
-+/* Line #18 Reserved */
-+#define AVALANCHE_MAC0_INT 19
-+/* Line #20 Reserved */
-+#define AVALANCHE_VLYNQ0_INT 21
-+#define AVALANCHE_CODEC_WAKE_INT 22
-+/* Line #23 Reserved */
-+#define AVALANCHE_USB_INT 24
-+#define AVALANCHE_VLYNQ1_INT 25
-+/* Line #26 Reserved */
-+/* Line #27 Reserved */
-+#define AVALANCHE_MAC1_INT 28
-+#define AVALANCHE_I2CM_INT 29
-+#define AVALANCHE_PDMA_INT2 30
-+#define AVALANCHE_PDMA_INT3 31
-+/* Line #32 Reserved */
-+/* Line #33 Reserved */
-+/* Line #34 Reserved */
-+/* Line #35 Reserved */
-+/* Line #36 Reserved */
-+#define AVALANCHE_VDMA_VT_RX_INT 37
-+#define AVALANCHE_VDMA_VT_TX_INT 38
-+#define AVALANCHE_ADSLSS_INT 39
++typedef enum AVALANCHE_GPIO_PIN_MODE_tag
++{
++ FUNCTIONAL_PIN = 0,
++ GPIO_PIN = 1
++} AVALANCHE_GPIO_PIN_MODE_T;
+
-+/*-----------------------------------*/
-+/* Sangam Secondary Interrupts */
-+/*-----------------------------------*/
-+#define PRIMARY_INTS 40
++typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
++{
++ GPIO_OUTPUT_PIN = 0,
++ GPIO_INPUT_PIN = 1
++} AVALANCHE_GPIO_PIN_DIRECTION_T;
+
-+#define EMIF_INT (7 + PRIMARY_INTS)
++typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
+
++void avalanche_gpio_init(void);
++int avalanche_gpio_ctrl(unsigned int gpio_pin,
++ AVALANCHE_GPIO_PIN_MODE_T pin_mode,
++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
++int avalanche_gpio_ctrl_with_link_count(unsigned int gpio_pin,
++ AVALANCHE_GPIO_PIN_MODE_T pin_mode,
++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
++int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
++int avalanche_gpio_in_bit(unsigned int gpio_pin);
++int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
++int avalanche_gpio_out_value_with_link_count(unsigned int out_val, unsigned int set_mask, unsigned int reg_index);
++int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
+
-+extern void avalanche_int_set(int channel, int line);
++unsigned int avalanche_get_chip_version_info(void);
+
++unsigned int avalanche_get_vbus_freq(void);
++void avalanche_set_vbus_freq(unsigned int);
+
-+#endif /* _AVALANCHE_INTC_H */
++
++typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
++int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
++unsigned int avalanche_is_mdix_on_chip(void);
++
++#endif
diff -urN kernel-base/include/asm-mips/ar7/avalanche_regs.h kernel-current/include/asm-mips/ar7/avalanche_regs.h
--- kernel-base/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/include/asm-mips/ar7/avalanche_regs.h 2005-07-10 09:27:48.638618856 +0200
++++ kernel-current/include/asm-mips/ar7/avalanche_regs.h 2005-07-10 18:48:26.333254256 +0200
@@ -0,0 +1,567 @@
+/*
+ * $Id$
+
diff -urN kernel-base/include/asm-mips/ar7/if_port.h kernel-current/include/asm-mips/ar7/if_port.h
--- kernel-base/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/include/asm-mips/ar7/if_port.h 2005-07-10 06:40:39.623260936 +0200
++++ kernel-current/include/asm-mips/ar7/if_port.h 2005-07-10 06:40:39.623260000 +0200
@@ -0,0 +1,26 @@
+/*******************************************************************************
+ * FILE PURPOSE: Interface port id Header file
+
+
+#endif /* _IF_PORT_H_ */
-diff -urN kernel-base/include/asm-mips/ar7/ledapp.h kernel-current/include/asm-mips/ar7/ledapp.h
---- kernel-base/include/asm-mips/ar7/ledapp.h 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/include/asm-mips/ar7/ledapp.h 2005-07-10 08:26:11.663644480 +0200
-@@ -0,0 +1,59 @@
-+#ifndef __LED_APP__
-+#define __LED_APP__
-+
-+#define CONF_FILE "/etc/led.conf"
-+#define LED_PROC_FILE "/proc/led_mod/led"
-+
-+#define CONFIG_LED_MODULE
-+
-+#define MAX_MOD_ID 25
-+#define MAX_STATE_ID 25
-+#define MAX_LED_ID 25
-+
-+#define MOD_ADSL 1
-+#define DEF_ADSL_IDLE 1
-+#define DEF_ADSL_TRAINING 2
-+#define DEF_ADSL_SYNC 3
-+#define DEF_ADSL_ACTIVITY 4
-+
-+#define MOD_WAN 2
-+#define DEF_WAN_IDLE 1
-+#define DEF_WAN_NEGOTIATE 2
-+#define DEF_WAN_SESSION 3
-+
-+#define MOD_LAN 3
-+#define DEF_LAN_IDLE 1
-+#define DEF_LAN_LINK_UP 2
-+#define DEF_LAN_ACTIVITY 3
-+
-+#define MOD_WLAN 4
-+#define DEF_WLAN_IDLE 1
-+#define DEF_WLAN_LINK_UP 2
-+#define DEF_WLAN_ACTIVITY 3
-+
-+#define MOD_USB 5
-+#define DEF_USB_IDLE 1
-+#define DEF_USB_LINK_UP 2
-+#define DEF_USB_ACTIVITY 3
-+
-+#define MOD_ETH 6
-+#define DEF_ETH_IDLE 1
-+#define DEF_ETH_LINK_UP 2
-+#define DEF_ETH_ACTIVITY 3
-+
-+typedef struct config_elem{
-+ unsigned char name;
-+ unsigned char state;
-+ unsigned char mode;
-+ unsigned char led;
-+ int param;
-+}config_elem_t;
-+
-+typedef struct led_reg{
-+ unsigned int param;
-+ void (*init)(unsigned long param);
-+ void (*onfunc)(unsigned long param);
-+ void (*offfunc)(unsigned long param);
-+}led_reg_t;
-+
-+#endif
diff -urN kernel-base/include/asm-mips/ar7/sangam_boards.h kernel-current/include/asm-mips/ar7/sangam_boards.h
--- kernel-base/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/include/asm-mips/ar7/sangam_boards.h 2005-07-10 06:40:39.623260936 +0200
++++ kernel-current/include/asm-mips/ar7/sangam_boards.h 2005-07-10 06:40:39.623260000 +0200
@@ -0,0 +1,77 @@
+#ifndef _SANGAM_BOARDS_H
+#define _SANGAM_BOARDS_H
+#endif
diff -urN kernel-base/include/asm-mips/ar7/sangam.h kernel-current/include/asm-mips/ar7/sangam.h
--- kernel-base/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/include/asm-mips/ar7/sangam.h 2005-07-10 06:40:39.624260784 +0200
++++ kernel-current/include/asm-mips/ar7/sangam.h 2005-07-10 06:40:39.624260000 +0200
@@ -0,0 +1,180 @@
+#ifndef _SANGAM_H_
+#define _SANGAM_H_
+#include "sangam_boards.h"
+
+#endif /*_SANGAM_H_ */
-diff -urN kernel-base/include/asm-mips/ar7/tnetd73xx_err.h kernel-current/include/asm-mips/ar7/tnetd73xx_err.h
---- kernel-base/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/include/asm-mips/ar7/tnetd73xx_err.h 2005-07-10 09:34:36.482617144 +0200
-@@ -0,0 +1,42 @@
-+/******************************************************************************
-+ * FILE PURPOSE: TNETD73xx Error Definations Header File
-+ ******************************************************************************
-+ * FILE NAME: tnetd73xx_err.h
-+ *
-+ * DESCRIPTION: Error definations for TNETD73XX
-+ *
-+ * REVISION HISTORY:
-+ * 27 Nov 02 - PSP TII
-+ *
-+ * (C) Copyright 2002, Texas Instruments, Inc
-+ *******************************************************************************/
-+
-+
-+#ifndef __TNETD73XX_ERR_H__
-+#define __TNETD73XX_ERR_H__
-+
-+typedef enum TNETD73XX_ERR_t
-+{
-+ TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
-+ TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
-+
-+ /* Pointers and args */
-+ TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
-+ TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
-+ TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
-+
-+ /* Memory issues */
-+ TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
-+ TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
-+ TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
-+ TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
-+
-+ /* Device issues */
-+ TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
-+ TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
-+
-+ TNETD73XX_ERR_INVID = -30 /* Invalid ID */
-+
-+} TNETD73XX_ERR;
-+
-+#endif /* __TNETD73XX_ERR_H__ */
-diff -urN kernel-base/include/asm-mips/ar7/tnetd73xx.h kernel-current/include/asm-mips/ar7/tnetd73xx.h
---- kernel-base/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/include/asm-mips/ar7/tnetd73xx.h 2005-07-10 09:51:18.910224984 +0200
-@@ -0,0 +1,338 @@
-+/******************************************************************************
-+ * FILE PURPOSE: TNETD73xx Common Header File
-+ ******************************************************************************
-+ * FILE NAME: tnetd73xx.h
-+ *
-+ * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
-+ *
-+ * REVISION HISTORY:
-+ * 27 Nov 02 - PSP TII
-+ *
-+ * (C) Copyright 2002, Texas Instruments, Inc
-+ *******************************************************************************/
-+
-+/*
-+ *
-+ *
-+ * These are const, typedef, and api definitions for tnetd73xx.
-+ *
-+ * NOTES:
-+ * 1. This file may be included into both C and Assembly files.
-+ * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
-+ * avoid C data types (typedefs) below;
-+ * - for .c files, you don't have to do anything special.
-+ *
-+ * 2. This file has a number of sections for each SOC subsystem. When adding
-+ * a new constant, find the subsystem you are working on and follow the
-+ * name pattern. If you are adding another typedef for your interface, please,
-+ * place it with other typedefs and function prototypes.
-+ *
-+ * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
-+ * cluttering. Include such items directly into the module's .c file or have a
-+ * local .h file to pass data between smaller modules. This file defines only
-+ * shared items.
-+ */
-+
-+#ifndef __TNETD73XX_H__
-+#define __TNETD73XX_H__
-+
-+#ifndef _ASMLANGUAGE /* This part not for assembly language */
-+
-+extern unsigned int tnetd73xx_mips_freq;
-+extern unsigned int tnetd73xx_vbus_freq;
-+
-+#include "tnetd73xx_err.h"
-+
-+#endif /* _ASMLANGUAGE */
-+
-+
-+/*******************************************************************************************
-+* Emerald core specific
-+******************************************************************************************** */
-+
-+#ifdef BIG_ENDIAN
-+#elif defined(LITTLE_ENDIAN)
-+#else
-+#error Need to define endianism
-+#endif
-+
-+#ifndef KSEG_MSK
-+#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
-+#endif
-+
-+#ifndef KSEG_INV_MASK
-+#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
-+#endif
-+
-+#ifndef KSEG0_BASE
-+#define KSEG0_BASE 0x80000000
-+#endif
-+
-+#ifndef KSEG1_BASE
-+#define KSEG1_BASE 0xA0000000
-+#endif
-+
-+#ifndef KSEG0
-+#define KSEG0(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
-+#endif
-+
-+#ifndef KSEG1
-+#define KSEG1(addr) (((__u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
-+#endif
-+
-+#ifndef KUSEG
-+#define KUSEG(addr) ((__u32)(addr) & ~KSEG_MSK)
-+#endif
-+
-+#ifndef PHYS_ADDR
-+#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
-+#endif
-+
-+#ifndef PHYS_TO_K0
-+#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
-+#endif
-+
-+#ifndef PHYS_TO_K1
-+#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
-+#endif
-+
-+#ifndef REG8_ADDR
-+#define REG8_ADDR(addr) (volatile __u8 *)(PHYS_TO_K1(addr))
-+#define REG8_DATA(addr) (*(volatile __u8 *)(PHYS_TO_K1(addr)))
-+#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
-+#define REG8_READ(addr, data) data = (__u8) REG8_DATA(addr);
-+#endif
-+
-+#ifndef REG16_ADDR
-+#define REG16_ADDR(addr) (volatile __u16 *)(PHYS_TO_K1(addr))
-+#define REG16_DATA(addr) (*(volatile __u16 *)(PHYS_TO_K1(addr)))
-+#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
-+#define REG16_READ(addr, data) data = (__u16) REG16_DATA(addr);
-+#endif
-+
-+#ifndef REG32_ADDR
-+#define REG32_ADDR(addr) (volatile __u32 *)(PHYS_TO_K1(addr))
-+#define REG32_DATA(addr) (*(volatile __u32 *)(PHYS_TO_K1(addr)))
-+#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
-+#define REG32_READ(addr, data) data = (__u32) REG32_DATA(addr);
-+#endif
-+
-+#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
-+#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
-+#endif
-+
-+#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
-+#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
-+#endif
-+
-+#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
-+#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
-+#endif
-+
-+/* TNETD73XX chip definations */
-+
-+#define FREQ_1MHZ 1000000
-+#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
-+#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
-+
-+#ifdef AR7SEAD2
-+#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
-+#else
-+#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
-+#endif
-+#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
-+
-+
-+
-+/* Module base addresses */
-+#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
-+#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
-+#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
-+#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
-+#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
-+#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
-+#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
-+#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
-+#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
-+#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
-+#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
-+#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
-+#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
-+#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
-+#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
-+#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
-+#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
-+#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
-+#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
-+#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
-+#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
-+#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
-+#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
-+#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
-+#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
-+#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
-+#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
-+#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
-+
-+/* BBIF Registers */
-+#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
-+
-+/* Device Configuration Latch Registers */
-+#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
-+#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
-+#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
-+#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
-+#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
-+
-+/* GPIO Control */
-+#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
-+#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
-+#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
-+#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
-+#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
-+#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
-+#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
-+
-+/* Reset Control */
-+#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
-+#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
-+#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
-+
-+/* Power Control */
-+#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
-+#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
-+#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
-+#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
-+
-+/* Clock Control */
-+#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
-+#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
-+#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
-+#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
-+#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
-+#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
-+#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
-+#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
-+#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
-+#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
-+
-+/* EMIF control */
-+#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
-+
-+/* UART */
-+#ifdef AR7SEAD2
-+#define TNETD73XX_UART_FREQ 3686400
-+#else
-+#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
-+#endif
-+
-+/* Interrupt Controller */
-+
-+/* Primary interrupts */
-+#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
-+#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
-+#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
-+#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
-+#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
-+#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
-+#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
-+#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
-+#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
-+#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
-+#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
-+#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
-+#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
-+#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
-+#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
-+#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
-+#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
-+#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
-+#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
-+#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
-+#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
-+#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
-+#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
-+#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
-+#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
-+#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
-+#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
-+#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
-+#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
-+#define TNETD73XX_INTC_I2C 29 /* I2C int */
-+#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
-+#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
-+#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
-+#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
-+#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
-+#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
-+#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
-+#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
-+#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
-+#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
-+
-+/* Secondary interrupts */
-+#define TNETD73XX_INTC_SEC0 40 /* Secondary */
-+#define TNETD73XX_INTC_SEC1 41 /* Secondary */
-+#define TNETD73XX_INTC_SEC2 42 /* Secondary */
-+#define TNETD73XX_INTC_SEC3 43 /* Secondary */
-+#define TNETD73XX_INTC_SEC4 44 /* Secondary */
-+#define TNETD73XX_INTC_SEC5 45 /* Secondary */
-+#define TNETD73XX_INTC_SEC6 46 /* Secondary */
-+#define TNETD73XX_INTC_EMIF 47 /* EMIF */
-+#define TNETD73XX_INTC_SEC8 48 /* Secondary */
-+#define TNETD73XX_INTC_SEC9 49 /* Secondary */
-+#define TNETD73XX_INTC_SEC10 50 /* Secondary */
-+#define TNETD73XX_INTC_SEC11 51 /* Secondary */
-+#define TNETD73XX_INTC_SEC12 52 /* Secondary */
-+#define TNETD73XX_INTC_SEC13 53 /* Secondary */
-+#define TNETD73XX_INTC_SEC14 54 /* Secondary */
-+#define TNETD73XX_INTC_SEC15 55 /* Secondary */
-+#define TNETD73XX_INTC_SEC16 56 /* Secondary */
-+#define TNETD73XX_INTC_SEC17 57 /* Secondary */
-+#define TNETD73XX_INTC_SEC18 58 /* Secondary */
-+#define TNETD73XX_INTC_SEC19 59 /* Secondary */
-+#define TNETD73XX_INTC_SEC20 60 /* Secondary */
-+#define TNETD73XX_INTC_SEC21 61 /* Secondary */
-+#define TNETD73XX_INTC_SEC22 62 /* Secondary */
-+#define TNETD73XX_INTC_SEC23 63 /* Secondary */
-+#define TNETD73XX_INTC_SEC24 64 /* Secondary */
-+#define TNETD73XX_INTC_SEC25 65 /* Secondary */
-+#define TNETD73XX_INTC_SEC26 66 /* Secondary */
-+#define TNETD73XX_INTC_SEC27 67 /* Secondary */
-+#define TNETD73XX_INTC_SEC28 68 /* Secondary */
-+#define TNETD73XX_INTC_SEC29 69 /* Secondary */
-+#define TNETD73XX_INTC_SEC30 70 /* Secondary */
-+#define TNETD73XX_INTC_SEC31 71 /* Secondary */
-+
-+/* These ugly macros are to access the -1 registers, like config1 */
-+#define MFC0_SEL1_OPCODE(dst, src)\
-+ .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
-+ nop; \
-+ nop; \
-+ nop
-+
-+#define MTC0_SEL1_OPCODE(dst, src)\
-+ .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
-+ nop; \
-+ nop; \
-+ nop
-+
-+
-+/* Below are Jade core specific */
-+#define CFG0_4K_IL_MASK 0x00380000
-+#define CFG0_4K_IL_SHIFT 19
-+#define CFG0_4K_IA_MASK 0x00070000
-+#define CFG0_4K_IA_SHIFT 16
-+#define CFG0_4K_IS_MASK 0x01c00000
-+#define CFG0_4K_IS_SHIFT 22
-+
-+#define CFG0_4K_DL_MASK 0x00001c00
-+#define CFG0_4K_DL_SHIFT 10
-+#define CFG0_4K_DA_MASK 0x00000380
-+#define CFG0_4K_DA_SHIFT 7
-+#define CFG0_4K_DS_MASK 0x0000E000
-+#define CFG0_4K_DS_SHIFT 13
-+
-+
-+
-+#endif /* __TNETD73XX_H_ */
-diff -urN kernel-base/include/asm-mips/ar7/tnetd73xx_misc.h kernel-current/include/asm-mips/ar7/tnetd73xx_misc.h
---- kernel-base/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
-+++ kernel-current/include/asm-mips/ar7/tnetd73xx_misc.h 2005-07-10 09:53:49.418344272 +0200
-@@ -0,0 +1,239 @@
-+/******************************************************************************
-+ * FILE PURPOSE: TNETD73xx Misc modules API Header
-+ ******************************************************************************
-+ * FILE NAME: tnetd73xx_misc.h
-+ *
-+ * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
-+ * FSER Modules API
-+ * As per TNETD73xx specifications
-+ *
-+ * REVISION HISTORY:
-+ * 27 Nov 02 - Sharath Kumar PSP TII
-+ * 14 Feb 03 - Anant Gole PSP TII
-+ *
-+ * (C) Copyright 2002, Texas Instruments, Inc
-+ *******************************************************************************/
-+
-+#ifndef __TNETD73XX_MISC_H__
-+#define __TNETD73XX_MISC_H__
-+
-+/*****************************************************************************
-+ * Reset Control Module
-+ *****************************************************************************/
-+
-+typedef enum TNETD73XX_RESET_MODULE_tag
-+{
-+ RESET_MODULE_UART0 = 0,
-+ RESET_MODULE_UART1 = 1,
-+ RESET_MODULE_I2C = 2,
-+ RESET_MODULE_TIMER0 = 3,
-+ RESET_MODULE_TIMER1 = 4,
-+ RESET_MODULE_GPIO = 6,
-+ RESET_MODULE_ADSLSS = 7,
-+ RESET_MODULE_USBS = 8,
-+ RESET_MODULE_SAR = 9,
-+ RESET_MODULE_VDMA_VT = 11,
-+ RESET_MODULE_FSER = 12,
-+ RESET_MODULE_VLYNQ1 = 16,
-+ RESET_MODULE_EMAC0 = 17,
-+ RESET_MODULE_DMA = 18,
-+ RESET_MODULE_BIST = 19,
-+ RESET_MODULE_VLYNQ0 = 20,
-+ RESET_MODULE_EMAC1 = 21,
-+ RESET_MODULE_MDIO = 22,
-+ RESET_MODULE_ADSLSS_DSP = 23,
-+ RESET_MODULE_EPHY = 26
-+} TNETD73XX_RESET_MODULE_T;
-+
-+typedef enum TNETD73XX_RESET_CTRL_tag
-+{
-+ IN_RESET = 0,
-+ OUT_OF_RESET
-+} TNETD73XX_RESET_CTRL_T;
-+
-+typedef enum TNETD73XX_SYS_RST_MODE_tag
-+{
-+ RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
-+ RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
-+} TNETD73XX_SYS_RST_MODE_T;
-+
-+typedef enum TNETD73XX_SYS_RESET_STATUS_tag
-+{
-+ HARDWARE_RESET = 0,
-+ SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
-+ WATCHDOG_RESET,
-+ SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
-+} TNETD73XX_SYS_RESET_STATUS_T;
-+
-+void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
-+ TNETD73XX_RESET_CTRL_T reset_ctrl);
-+TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
-+void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
-+TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
-+
-+/*****************************************************************************
-+ * Power Control Module
-+ *****************************************************************************/
-+
-+typedef enum TNETD73XX_POWER_MODULE_tag
-+{
-+ POWER_MODULE_USBSP = 0,
-+ POWER_MODULE_WDTP = 1,
-+ POWER_MODULE_UT0P = 2,
-+ POWER_MODULE_UT1P = 3,
-+ POWER_MODULE_IICP = 4,
-+ POWER_MODULE_VDMAP = 5,
-+ POWER_MODULE_GPIOP = 6,
-+ POWER_MODULE_VLYNQ1P = 7,
-+ POWER_MODULE_SARP = 8,
-+ POWER_MODULE_ADSLP = 9,
-+ POWER_MODULE_EMIFP = 10,
-+ POWER_MODULE_ADSPP = 12,
-+ POWER_MODULE_RAMP = 13,
-+ POWER_MODULE_ROMP = 14,
-+ POWER_MODULE_DMAP = 15,
-+ POWER_MODULE_BISTP = 16,
-+ POWER_MODULE_TIMER0P = 18,
-+ POWER_MODULE_TIMER1P = 19,
-+ POWER_MODULE_EMAC0P = 20,
-+ POWER_MODULE_EMAC1P = 22,
-+ POWER_MODULE_EPHYP = 24,
-+ POWER_MODULE_VLYNQ0P = 27,
-+} TNETD73XX_POWER_MODULE_T;
-+
-+typedef enum TNETD73XX_POWER_CTRL_tag
-+{
-+ POWER_CTRL_POWER_UP = 0,
-+ POWER_CTRL_POWER_DOWN
-+} TNETD73XX_POWER_CTRL_T;
-+
-+typedef enum TNETD73XX_SYS_POWER_MODE_tag
-+{
-+ GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
-+ GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
-+ GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
-+ GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
-+} TNETD73XX_SYS_POWER_MODE_T;
-+
-+void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
-+TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
-+void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
-+TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
-+
-+/*****************************************************************************
-+ * Wakeup Control
-+ *****************************************************************************/
-+
-+typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
-+{
-+ WAKEUP_INT0 = 1,
-+ WAKEUP_INT1 = 2,
-+ WAKEUP_INT2 = 4,
-+ WAKEUP_INT3 = 8
-+} TNETD73XX_WAKEUP_INTERRUPT_T;
-+
-+typedef enum TNETD73XX_WAKEUP_CTRL_tag
-+{
-+ WAKEUP_DISABLED = 0,
-+ WAKEUP_ENABLED
-+} TNETD73XX_WAKEUP_CTRL_T;
-+
-+typedef enum TNETD73XX_WAKEUP_POLARITY_tag
-+{
-+ WAKEUP_ACTIVE_HIGH = 0,
-+ WAKEUP_ACTIVE_LOW
-+} TNETD73XX_WAKEUP_POLARITY_T;
-+
-+void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
-+ TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
-+ TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
-+
-+/*****************************************************************************
-+ * FSER Control
-+ *****************************************************************************/
-+
-+typedef enum TNETD73XX_FSER_MODE_tag
-+{
-+ FSER_I2C = 0,
-+ FSER_UART = 1
-+} TNETD73XX_FSER_MODE_T;
-+
-+void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
-+
-+/*****************************************************************************
-+ * Clock Control
-+ *****************************************************************************/
-+
-+#define CLK_MHZ(x) ( (x) * 1000000 )
-+
-+typedef enum TNETD73XX_CLKC_ID_tag
-+{
-+ CLKC_SYS = 0,
-+ CLKC_MIPS,
-+ CLKC_USB,
-+ CLKC_ADSLSS
-+} TNETD73XX_CLKC_ID_T;
-+
-+void tnetd73xx_clkc_init(__u32 afeclk, __u32 refclk, __u32 xtal3in);
-+TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, __u32 output_freq);
-+__u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
-+
-+/*****************************************************************************
-+ * GPIO Control
-+ *****************************************************************************/
-+
-+typedef enum TNETD73XX_GPIO_PIN_tag
-+{
-+ GPIO_UART0_RD = 0,
-+ GPIO_UART0_TD = 1,
-+ GPIO_UART0_RTS = 2,
-+ GPIO_UART0_CTS = 3,
-+ GPIO_FSER_CLK = 4,
-+ GPIO_FSER_D = 5,
-+ GPIO_EXT_AFE_SCLK = 6,
-+ GPIO_EXT_AFE_TX_FS = 7,
-+ GPIO_EXT_AFE_TXD = 8,
-+ GPIO_EXT_AFE_RS_FS = 9,
-+ GPIO_EXT_AFE_RXD1 = 10,
-+ GPIO_EXT_AFE_RXD0 = 11,
-+ GPIO_EXT_AFE_CDIN = 12,
-+ GPIO_EXT_AFE_CDOUT = 13,
-+ GPIO_EPHY_SPEED100 = 14,
-+ GPIO_EPHY_LINKON = 15,
-+ GPIO_EPHY_ACTIVITY = 16,
-+ GPIO_EPHY_FDUPLEX = 17,
-+ GPIO_EINT0 = 18,
-+ GPIO_EINT1 = 19,
-+ GPIO_MBSP0_TCLK = 20,
-+ GPIO_MBSP0_RCLK = 21,
-+ GPIO_MBSP0_RD = 22,
-+ GPIO_MBSP0_TD = 23,
-+ GPIO_MBSP0_RFS = 24,
-+ GPIO_MBSP0_TFS = 25,
-+ GPIO_MII_DIO = 26,
-+ GPIO_MII_DCLK = 27,
-+} TNETD73XX_GPIO_PIN_T;
-+
-+typedef enum TNETD73XX_GPIO_PIN_MODE_tag
-+{
-+ FUNCTIONAL_PIN = 0,
-+ GPIO_PIN = 1
-+} TNETD73XX_GPIO_PIN_MODE_T;
-+
-+typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
-+{
-+ GPIO_OUTPUT_PIN = 0,
-+ GPIO_INPUT_PIN = 1
-+} TNETD73XX_GPIO_PIN_DIRECTION_T;
-+
-+void tnetd73xx_gpio_init(void);
-+void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
-+ TNETD73XX_GPIO_PIN_MODE_T pin_mode,
-+ TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
-+void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
-+int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
-+
-+/* TNETD73XX Revision */
-+__u32 tnetd73xx_get_revision(void);
-+
-+#endif /* __TNETD73XX_MISC_H__ */
diff -urN kernel-base/include/asm-mips/io.h kernel-current/include/asm-mips/io.h
--- kernel-base/include/asm-mips/io.h 2005-07-10 03:00:44.797179400 +0200
-+++ kernel-current/include/asm-mips/io.h 2005-07-10 06:40:39.624260784 +0200
++++ kernel-current/include/asm-mips/io.h 2005-07-10 06:40:39.624260000 +0200
@@ -63,8 +63,12 @@
#ifdef CONFIG_64BIT_PHYS_ADDR
#define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
diff -urN kernel-base/include/asm-mips/irq.h kernel-current/include/asm-mips/irq.h
--- kernel-base/include/asm-mips/irq.h 2005-07-10 03:00:44.798179248 +0200
-+++ kernel-current/include/asm-mips/irq.h 2005-07-10 06:40:39.624260784 +0200
++++ kernel-current/include/asm-mips/irq.h 2005-07-10 06:40:39.624260000 +0200
@@ -14,7 +14,12 @@
#include <linux/config.h>
#include <linux/linkage.h>
static inline int irq_cannonicalize(int irq)
diff -urN kernel-base/include/asm-mips/page.h kernel-current/include/asm-mips/page.h
--- kernel-base/include/asm-mips/page.h 2005-07-10 03:00:44.798179248 +0200
-+++ kernel-current/include/asm-mips/page.h 2005-07-10 06:40:39.625260632 +0200
++++ kernel-current/include/asm-mips/page.h 2005-07-10 06:40:39.625260000 +0200
@@ -129,7 +129,11 @@
#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
diff -urN kernel-base/include/asm-mips/pgtable-32.h kernel-current/include/asm-mips/pgtable-32.h
--- kernel-base/include/asm-mips/pgtable-32.h 2005-07-10 03:00:44.798179248 +0200
-+++ kernel-current/include/asm-mips/pgtable-32.h 2005-07-10 06:40:39.625260632 +0200
++++ kernel-current/include/asm-mips/pgtable-32.h 2005-07-10 06:40:39.625260000 +0200
@@ -108,7 +108,18 @@
* and a page entry and page directory to the page they refer to.
*/
#else
diff -urN kernel-base/include/asm-mips/serial.h kernel-current/include/asm-mips/serial.h
--- kernel-base/include/asm-mips/serial.h 2005-07-10 03:00:44.799179096 +0200
-+++ kernel-current/include/asm-mips/serial.h 2005-07-10 06:40:39.625260632 +0200
++++ kernel-current/include/asm-mips/serial.h 2005-07-10 06:40:39.625260000 +0200
@@ -65,6 +65,15 @@
#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
COBALT_SERIAL_PORT_DEFNS \
diff -urN kernel-base/Makefile kernel-current/Makefile
--- kernel-base/Makefile 2005-07-10 03:00:44.799179096 +0200
-+++ kernel-current/Makefile 2005-07-10 06:40:39.626260480 +0200
++++ kernel-current/Makefile 2005-07-10 06:40:39.626260000 +0200
@@ -91,7 +91,7 @@
CPPFLAGS := -D__KERNEL__ -I$(HPATH)
projects / openwrt.git / blobdiff