#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
#define AR91XX_WMAC_SIZE 0x30000
+#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE 0x14
+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE 0x04
+#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define AR933X_WMAC_SIZE 0x20000
+
+#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define AR934X_WMAC_SIZE 0x20000
+
#define AR71XX_MEM_SIZE_MIN 0x0200000
#define AR71XX_MEM_SIZE_MAX 0x10000000
#define AR71XX_CPU_IRQ_BASE 0
#define AR71XX_MISC_IRQ_BASE 8
-#define AR71XX_MISC_IRQ_COUNT 8
-#define AR71XX_GPIO_IRQ_BASE 16
+#define AR71XX_MISC_IRQ_COUNT 32
+#define AR71XX_GPIO_IRQ_BASE 40
#define AR71XX_GPIO_IRQ_COUNT 32
-#define AR71XX_PCI_IRQ_BASE 48
+#define AR71XX_PCI_IRQ_BASE 72
#define AR71XX_PCI_IRQ_COUNT 8
#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
+#define AR71XX_MISC_IRQ_TIMER2 (AR71XX_MISC_IRQ_BASE + 8)
+#define AR71XX_MISC_IRQ_TIMER3 (AR71XX_MISC_IRQ_BASE + 9)
+#define AR71XX_MISC_IRQ_TIMER4 (AR71XX_MISC_IRQ_BASE + 10)
+#define AR71XX_MISC_IRQ_DDR_PERF (AR71XX_MISC_IRQ_BASE + 11)
+#define AR71XX_MISC_IRQ_ENET_LINK (AR71XX_MISC_IRQ_BASE + 12)
#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
extern u32 ar71xx_ahb_freq;
extern u32 ar71xx_cpu_freq;
extern u32 ar71xx_ddr_freq;
-extern u32 ar934x_ref_freq;
+extern u32 ar71xx_ref_freq;
enum ar71xx_soc_type {
AR71XX_SOC_UNKNOWN,
AR71XX_SOC_AR7242,
AR71XX_SOC_AR9130,
AR71XX_SOC_AR9132,
+ AR71XX_SOC_AR9330,
+ AR71XX_SOC_AR9331,
AR71XX_SOC_AR9341,
AR71XX_SOC_AR9342,
AR71XX_SOC_AR9344,
};
+extern u32 ar71xx_soc_rev;
extern enum ar71xx_soc_type ar71xx_soc;
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
+
#define AR91XX_PLL_REG_CPU_CONFIG 0x00
#define AR91XX_PLL_REG_ETH_CONFIG 0x04
#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
#define AR91XX_ETH0_PLL_SHIFT 20
#define AR91XX_ETH1_PLL_SHIFT 22
+#define AR933X_PLL_CPU_CONFIG_REG 0x00
+#define AR933X_PLL_CLOCK_CTRL_REG 0x08
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
+
#define AR934X_PLL_REG_CPU_CONFIG 0x00
+#define AR934X_PLL_REG_DDR_CONFIG 0x04
#define AR934X_PLL_REG_DDR_CTRL_CLOCK 0x8
#define AR934X_CPU_PLL_CFG_OUTDIV_MSB 21
#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_RESET 1
+#define AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define AR934X_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define AR934X_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+#define AR934X_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+#define AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
extern void __iomem *ar71xx_pll_base;
static inline void ar71xx_pll_wr(unsigned reg, u32 val)
#define AR91XX_GPIO_COUNT 22
+#define AR933X_GPIO_COUNT 30
+
+#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
+#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
+
+#define AR934X_GPIO_COUNT 32
+#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
+
extern void __iomem *ar71xx_gpio_base;
static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
#define AR91XX_DDR_REG_FLUSH_USB 0x84
#define AR91XX_DDR_REG_FLUSH_WMAC 0x88
+#define AR933X_DDR_REG_FLUSH_GE0 0x7c
+#define AR933X_DDR_REG_FLUSH_GE1 0x80
+#define AR933X_DDR_REG_FLUSH_USB 0x84
+#define AR933X_DDR_REG_FLUSH_WMAC 0x88
+
+#define AR934X_DDR_REG_FLUSH_GE0 0x9c
+#define AR934X_DDR_REG_FLUSH_GE1 0xa0
+#define AR934X_DDR_REG_FLUSH_USB 0xa4
+#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
+
+
#define PCI_WIN0_OFFS 0x10000000
#define PCI_WIN1_OFFS 0x11000000
#define PCI_WIN2_OFFS 0x12000000
#define AR724X_RESET_REG_RESET_MODULE 0x1c
+#define AR933X_RESET_REG_RESET_MODULE 0x1c
+#define AR933X_RESET_REG_BOOTSTRAP 0xac
+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
+#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
+
#define AR934X_RESET_REG_RESET_MODULE 0x1c
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
-/* 0 - 25MHz 1 - 40 MHz */
-#define AR934X_REF_CLK_40 (1 << 4)
+#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
+#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
+#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
+#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
+#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
+#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
+#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
+#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
+#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
+#define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
+#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
+#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
+#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define AR934X_BOOTSTRAP_DDR1 BIT(0)
#define WDOG_CTRL_LAST_RESET BIT(31)
#define WDOG_CTRL_ACTION_MASK 3
#define WDOG_CTRL_ACTION_NMI 2 /* NMI */
#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
+#define MISC_INT_ENET_LINK BIT(12)
+#define MISC_INT_DDR_PERF BIT(11)
+#define MISC_INT_TIMER4 BIT(10)
+#define MISC_INT_TIMER3 BIT(9)
+#define MISC_INT_TIMER2 BIT(8)
#define MISC_INT_DMA BIT(7)
#define MISC_INT_OHCI BIT(6)
#define MISC_INT_PERFC BIT(5)
#define AR724X_RESET_USB_PHY BIT(4)
#define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
+#define AR933X_RESET_WMAC BIT(11)
+#define AR933X_RESET_GE1_MDIO BIT(23)
+#define AR933X_RESET_GE0_MDIO BIT(22)
+#define AR933X_RESET_GE1_MAC BIT(13)
+#define AR933X_RESET_GE0_MAC BIT(9)
+#define AR933X_RESET_USB_HOST BIT(5)
+#define AR933X_RESET_USB_PHY BIT(4)
+#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define AR934X_RESET_HOST BIT(31)
+#define AR934X_RESET_SLIC BIT(30)
+#define AR934X_RESET_HDMA BIT(29)
+#define AR934X_RESET_EXTERNAL BIT(28)
+#define AR934X_RESET_RTC BIT(27)
+#define AR934X_RESET_PCIE_EP_INT BIT(26)
+#define AR934X_RESET_CHKSUM_ACC BIT(25)
+#define AR934X_RESET_FULL_CHIP BIT(24)
+#define AR934X_RESET_GE1_MDIO BIT(23)
+#define AR934X_RESET_GE0_MDIO BIT(22)
+#define AR934X_RESET_CPU_NMI BIT(21)
+#define AR934X_RESET_CPU_COLD BIT(20)
+#define AR934X_RESET_HOST_RESET_INT BIT(19)
+#define AR934X_RESET_PCIE_EP BIT(18)
+#define AR934X_RESET_UART1 BIT(17)
+#define AR934X_RESET_DDR BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define AR934X_RESET_NANDF BIT(14)
+#define AR934X_RESET_GE1_MAC BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
+#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
+#define AR934X_RESET_HOST_DMA_INT BIT(10)
+#define AR934X_RESET_GE0_MAC BIT(9)
+#define AR934X_RESET_ETH_SIWTCH BIT(8)
+#define AR934X_RESET_PCIE_PHY BIT(7)
+#define AR934X_RESET_PCIE BIT(6)
+#define AR934X_RESET_USB_HOST BIT(5)
+#define AR934X_RESET_USB_PHY BIT(4)
+#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
+#define AR934X_RESET_LUT BIT(2)
+#define AR934X_RESET_MBOX BIT(1)
+#define AR934X_RESET_I2S BIT(0)
+
#define REV_ID_MAJOR_MASK 0xfff0
#define REV_ID_MAJOR_AR71XX 0x00a0
#define REV_ID_MAJOR_AR913X 0x00b0
#define REV_ID_MAJOR_AR7240 0x00c0
#define REV_ID_MAJOR_AR7241 0x0100
#define REV_ID_MAJOR_AR7242 0x1100
+#define REV_ID_MAJOR_AR9330 0x0110
+#define REV_ID_MAJOR_AR9331 0x1110
#define REV_ID_MAJOR_AR9341 0x0120
#define REV_ID_MAJOR_AR9342 0x1120
#define REV_ID_MAJOR_AR9344 0x2120
#define AR724X_REV_ID_REVISION_MASK 0x3
+#define AR933X_REV_ID_REVISION_MASK 0xf
+
#define AR934X_REV_ID_REVISION_MASK 0xf
extern void __iomem *ar71xx_reset_base;
void ar71xx_device_stop(u32 mask);
void ar71xx_device_start(u32 mask);
+void ar71xx_device_reset_rmw(u32 clear, u32 set);
int ar71xx_device_stopped(u32 mask);
/*
#define MII1_CTRL_IF_RGMII 0
#define MII1_CTRL_IF_RMII 1
+/*
+ * AR933X GMAC
+ */
+#define AR933X_GMAC_REG_ETH_CFG 0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
+#define AR933X_ETH_CFG_MII_GE0 BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
+
#endif /* __ASSEMBLER__ */
#endif /* __ASM_MACH_AR71XX_H */
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