ar71xx: add AR933x specific frequency initialization code

[openwrt.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 9dc15fe..759c8e6 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -70,6 +70,9 @@
 #define AR91XX_WMAC_BASE       (AR71XX_APB_BASE + 0x000C0000)
 #define AR91XX_WMAC_SIZE       0x30000
 
+#define AR933X_UART_BASE       (AR71XX_APB_BASE + 0x00020000)
+#define AR933X_UART_SIZE       0x14
+
 #define AR934X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
 #define AR934X_WMAC_SIZE       0x20000
 
@@ -185,6 +188,24 @@ extern enum ar71xx_soc_type ar71xx_soc;
 #define AR91XX_ETH0_PLL_SHIFT          20
 #define AR91XX_ETH1_PLL_SHIFT          22
 
+#define AR933X_PLL_CPU_CONFIG_REG      0x00
+#define AR933X_PLL_CLOCK_CTRL_REG      0x08
+
+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT       10
+#define AR933X_PLL_CPU_CONFIG_NINT_MASK                0x3f
+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT     16
+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK      0x1f
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT     23
+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK      0x7
+
+#define AR933X_PLL_CLOCK_CTRL_BYPASS           BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT    5
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK     0x3
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT    10
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK     0x3
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT    15
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK     0x7
+
 #define AR934X_PLL_REG_CPU_CONFIG      0x00
 #define AR934X_PLL_REG_DDR_CTRL_CLOCK  0x8
 
@@ -576,6 +597,9 @@ void ar71xx_ddr_flush(u32 reg);
 
 #define AR724X_RESET_REG_RESET_MODULE          0x1c
 
+#define AR933X_RESET_REG_BOOTSTRAP             0xac
+#define AR933X_BOOTSTRAP_REF_CLK_40            BIT(0)
+
 #define AR934X_RESET_REG_RESET_MODULE          0x1c
 #define AR934X_RESET_REG_BOOTSTRAP             0xb0
 /* 0 - 25MHz   1 - 40 MHz */