/* Interrupts */
#define AR7_IRQ_UART0 15
-@@ -97,14 +117,22 @@ extern int ar7_cpu_clock, ar7_bus_clock,
+@@ -95,14 +115,22 @@ struct plat_dsl_data {
- extern void __init ar7_init_clocks(void);
+ extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
+static inline int ar7_is_titan(void)
+{
+ * GPIO Control
+ **********************************************************************/
+
-+typedef struct
++typedef struct
+{
+ int pinSelReg;
+ int shift;
+ GPIO_CFG gpio_cfg;
+ volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE;
+ volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
-+
++
+ if (gpio_pin > 51 )
+ return(-1);
+