+--- a/cpu/mips/cache.S
++++ b/cpu/mips/cache.S
+@@ -29,7 +29,9 @@
+ #include <asm/mipsregs.h>
+ #include <asm/addrspace.h>
+ #include <asm/cacheops.h>
+-
++#if defined(CONFIG_IFX_MIPS)
++# include "danube/ifx_cache.S"
++#endif
+
+ /* 16KB is the maximum size of instruction and data caches on
+ * MIPS 4K.
+@@ -155,6 +157,9 @@
+ */
+
+ mtc0 zero, CP0_TAGLO
++#if defined(CONFIG_IFX_MIPS) && defined(IFX_CACHE_EXTRA_INVALID_TAG)
++ IFX_CACHE_EXTRA_INVALID_TAG
++#endif
+
+ /*
+ * The caches are probably in an indeterminate state,
+@@ -171,6 +176,9 @@
+ move a1, a2
+ icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill))
+
++#if defined(CONFIG_IFX_MIPS) && defined(IFX_CACHE_EXTRA_OPERATION)
++ IFX_CACHE_EXTRA_OPERATION
++#else
+ /* To support Orion/R4600, we initialise the data cache in 3 passes.
+ */
+
+@@ -200,6 +208,7 @@
+ move a3, t5 # dcacheLineSize
+ move a1, a2
+ icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
++#endif
+
+ j ra
+ .end mips_cache_reset
+--- a/cpu/mips/config.mk
++++ b/cpu/mips/config.mk
+@@ -20,20 +20,26 @@
+ # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ # MA 02111-1307 USA
+ #
+-v=$(shell \
+-$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}')
+-MIPSFLAGS=$(shell \
+-if [ "$v" -lt "14" ]; then \
+- echo "-mcpu=4kc"; \
+-else \
+- echo "-march=4kc -mtune=4kc"; \
+-fi)
+
++ifndef PLATFORM_CPU
++PLATFORM_CPU = mips32
++endif
++
++MIPSFLAGS +=$(call cc-option,-march=$(PLATFORM_CPU) -mtune=$(PLATFORM_CPU),-mcpu=$(PLATFORM_CPU))
++
++ifeq ($(CROSS_COMPILE_UCLIBC),1)
++ifneq (,$(findstring mipsel,$(CROSS_COMIPLE)))
++ENDIANNESS = -el
++else
++ENDIANNESS = -eb
++endif
++else
+ ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
+ ENDIANNESS = -EL
+ else
+ ENDIANNESS = -EB
+ endif
++endif
+
+ MIPSFLAGS += $(ENDIANNESS) -mabicalls
+
+--- a/cpu/mips/cpu.c
++++ b/cpu/mips/cpu.c
+@@ -23,7 +23,12 @@
+
+ #include <common.h>
+ #include <command.h>
+-#include <asm/inca-ip.h>
++#if defined(CONFIG_INCA_IP)
++# include <asm/inca-ip.h>
++#elif defined(CONFIG_IFX_MIPS)
++# include <asm/danube.h>
++# include "danube/ifx_cpu.c"
++#endif
+ #include <asm/mipsregs.h>
+
+ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+@@ -34,6 +39,8 @@
+ void (*f)(void) = (void *) 0xbfc00000;
+
+ f();
++#elif defined(CONFIG_IFX_MIPS)
++ IFX_CPU_RESET;
+ #endif
+ fprintf(stderr, "*** reset failed ***\n");
+ return 0;
+--- a/cpu/mips/incaip_clock.c
++++ b/cpu/mips/incaip_clock.c
+@@ -22,8 +22,9 @@
+ */
+
+ #include <common.h>
+-#include <asm/inca-ip.h>
+
++#ifdef CONFIG_INCA_IP
++#include <asm/inca-ip.h>
+
+ /*******************************************************************************
+ *
+@@ -114,3 +115,5 @@
+
+ return 0;
+ }
++
++#endif /* CONFIG_INCA_IP */
+--- a/cpu/mips/start.S
++++ b/cpu/mips/start.S
+@@ -27,7 +27,9 @@
+ #include <version.h>
+ #include <asm/regdef.h>
+ #include <asm/mipsregs.h>
+-
++#if defined(CONFIG_IFX_MIPS)
++# include "danube/ifx_start.S"
++#endif
+
+ #define RVECENT(f,n) \
+ b f; nop
+@@ -36,15 +38,24 @@
+ li k0,bev
+
+ .set noreorder
+-
++#ifdef CFG_BOOTSTRAP_CODE
++ .globl _start_bootstrap
++#else
+ .globl _start
++#endif
+ .text
++#ifdef CFG_BOOTSTRAP_CODE
++_start_bootstrap:
++#else
+ _start:
++#endif
+ RVECENT(reset,0) /* U-boot entry point */
+ RVECENT(reset,1) /* software reboot */
+-#if defined(CONFIG_INCA_IP)
++#if defined(CONFIG_INCA_IP) || defined(CONFIG_INCA_IP2)
+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+ .word 0x00000000 /* phase of the flash */
++#elif defined(CONFIG_IFX_MIPS) && defined(IFX_EBU_BOOTCFG_DWORD)
++ IFX_EBU_BOOTCFG_DWORD
+ #elif defined(CONFIG_PURPLE)
+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+ .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
+@@ -181,6 +192,9 @@
+ * 128 * 8 == 1024 == 0x400
+ * so this is address R_VEC+0x400 == 0xbfc00400
+ */
++#if defined(CONFIG_IFX_MIPS) && defined(IFX_MORE_RESERVED_VECTORS)
++ IFX_MORE_RESERVED_VECTORS
++#else
+ #ifdef CONFIG_PURPLE
+ /* 0xbfc00400 */
+ .word 0xdc870000
+@@ -205,8 +219,12 @@
+ .word 0x00000000
+ .word 0x00000000
+ #endif /* CONFIG_PURPLE */
++#endif /* CONFIG_IFX_MIPS */
+ .align 4
+ reset:
++#if defined(CONFIG_IFX_MIPS) && defined(IFX_RESET_PRECHECK)
++ IFX_RESET_PRECHECK
++#endif
+
+ /* Clear watch registers.
+ */
+@@ -226,6 +244,10 @@
+ /* CAUSE register */
+ mtc0 zero, CP0_CAUSE
+
++#if defined(CONFIG_IFX_MIPS) && defined(IFX_CPU_EXTRA_INIT)
++ IFX_CPU_EXTRA_INIT
++#endif
++
+ /* Init Timer */
+ mtc0 zero, CP0_COUNT
+ mtc0 zero, CP0_COMPARE
+@@ -252,12 +274,26 @@
+ nop
+ #endif
+
++#if defined(CONFIG_IFX_MIPS) && defined(IFX_CPU1_SUPPORT) && defined(IFX_SKIP_LOWLEVEL_INIT)
++ IFX_SKIP_LOWLEVEL_INIT
++#endif
++#ifdef CFG_BOOTSTRAP_CODE
+ /* Initialize any external memory.
+ */
+ la t9, lowlevel_init
+ jalr t9
+ nop
++#endif
++lowlevel_init_done:
++
++ beq s0, zero, init_cache_0
++ nop
++
++#if defined(CONFIG_IFX_MIPS) && defined(IFX_CPU1_SUPPORT) && defined(IFX_CPU1_INIT)
++ IFX_CPU1_INIT
++#endif
+
++init_cache_0:
+ /* Initialize caches...
+ */
+ la t9, mips_cache_reset
+@@ -266,7 +302,11 @@
+
+ /* ... and enable them.
+ */
++#if defined(CONFIG_IFX_MIPS) && defined(IFX_CACHE_OPER_MODE)
++ IFX_CACHE_OPER_MODE
++#else
+ li t0, CONF_CM_CACHABLE_NONCOHERENT
++#endif
+ mtc0 t0, CP0_CONFIG
+
+
+@@ -280,13 +320,38 @@
+ li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET
+ la sp, 0(t0)
+
++#if defined(CONFIG_IFX_MIPS) && defined(IFX_CPU1_SUPPORT) && defined(IFX_BOOT_CLEAR)
++ IFX_BOOT_CLEAR
++#endif
++
++#ifdef CFG_BOOTSTRAP_CODE
++ la t9, bootstrap_board_init_f
++#else
+ la t9, board_init_f
++#endif
+ j t9
+ nop
+
++#ifdef CFG_BOOTSTRAP_CODE
++/*
++ * void jump_unconditional (addr)
++ * This function simply jumps to the location pointed by a0.
++ * a0 = target_location
++ *
++ */
++ .globl jump_unconditional
++ .ent jump_unconditional
++jump_unconditional:
++ move t9, a0
++ j t9
++ nop
++ .end jump_unconditional
++
++#endif
+
+ /*
+ * void relocate_code (addr_sp, gd, addr_moni)
++ * void bootstrap_relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+@@ -295,12 +360,22 @@
+ * a1 = gd
+ * a2 = destination address
+ */
++#ifdef CFG_BOOTSTRAP_CODE
++ .globl bootstrap_relocate_code
++ .ent bootstrap_relocate_code
++bootstrap_relocate_code:
++#else
+ .globl relocate_code
+ .ent relocate_code
+ relocate_code:
++#endif
+ move sp, a0 /* Set new stack pointer */
+
++#ifdef CFG_BOOTSTRAP_CODE
++ li t0, BOOTSTRAP_CFG_MONITOR_BASE
++#else
+ li t0, CFG_MONITOR_BASE
++#endif
+ la t3, in_ram
+ lw t2, -12(t3) /* t2 <-- uboot_end_data */
+ move t1, a2
+@@ -311,7 +386,11 @@
+ * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ */
+ move t6, gp
++#ifdef CFG_BOOTSTRAP_CODE
++ sub gp, BOOTSTRAP_CFG_MONITOR_BASE
++#else
+ sub gp, CFG_MONITOR_BASE
++#endif
+ add gp, a2 /* gp now adjusted */
+ sub t6, gp, t6 /* t6 <-- relocation offset */
+
+@@ -337,12 +416,21 @@
+
+ /* Jump to where we've relocated ourselves.
+ */
++#ifdef CFG_BOOTSTRAP_CODE
++ addi t0, a2, in_ram - _start_bootstrap
++#else
+ addi t0, a2, in_ram - _start
++#endif
+ j t0
+ nop
+
++#ifdef CFG_BOOTSTRAP_CODE
++ .word uboot_end_data_bootstrap
++ .word uboot_end_bootstrap
++#else
+ .word uboot_end_data
+ .word uboot_end
++#endif
+ .word num_got_entries
+
+ in_ram:
+@@ -374,12 +462,19 @@
+ sw zero, 0(t1) /* delay slot */
+
+ move a0, a1
++#ifdef CFG_BOOTSTRAP_CODE
++ la t9, bootstrap_board_init_r
++#else
+ la t9, board_init_r
++#endif
+ j t9
+ move a1, a2 /* delay slot */
+
++#ifdef CFG_BOOTSTRAP_CODE
++ .end bootstrap_relocate_code
++#else
+ .end relocate_code
+-
++#endif
+
+ /* Exception handlers.
+ */
+@@ -388,3 +483,20 @@
+
+ romExcHandle:
+ b romExcHandle
++
++romEjtagHandle:
++#ifdef CFG_BOOTSTRAP_CODE
++ deret
++ nop
++#endif /* CFG_BOOTSTRAP_CODE */
++1:
++ b 1b
++
++ /* Additional handlers.
++ */
++#if defined(CONFIG_IFX_MIPS)
++#if defined(IFX_MIPS_HANDLER_1)
++ifx_mips_handler_1:
++ IFX_MIPS_HANDLER_1
++#endif
++#endif