adds pci support for rt288x

[openwrt.git] / target / linux / ramips / files / arch / mips / ralink / common / setup.c

diff --git a/target/linux/ramips/files/arch/mips/ralink/common/setup.c b/target/linux/ramips/files/arch/mips/ralink/common/setup.c
index 6440ccb..3030fcd 100644 (file)
--- a/target/linux/ramips/files/arch/mips/ralink/common/setup.c
+++ b/target/linux/ramips/files/arch/mips/ralink/common/setup.c
@@ -12,13 +12,80 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/serial_8250.h>
 
+#include <asm/bootinfo.h>
 #include <asm/addrspace.h>
+#include <asm/mips_machine.h>
+
 #include <asm/mach-ralink/common.h>
+#include <asm/mach-ralink/machine.h>
+#include <ralink_soc.h>
+
+unsigned char ramips_sys_type[RAMIPS_SYS_TYPE_LEN];
+enum ramips_mach_type ramips_mach = RAMIPS_MACH_GENERIC;
+
+const char *get_system_type(void)
+{
+       return ramips_sys_type;
+}
+
+static void __init detect_mem_size(void)
+{
+       unsigned long size;
+
+       for (size = RALINK_SOC_MEM_SIZE_MIN; size < RALINK_SOC_MEM_SIZE_MAX;
+            size <<= 1 ) {
+               if (!memcmp(detect_mem_size,
+                           detect_mem_size + size, 1024))
+                       break;
+       }
+
+       add_memory_region(RALINK_SOC_SDRAM_BASE, size, BOOT_MEM_RAM);
+}
+
+void __init ramips_early_serial_setup(int line, unsigned base, unsigned freq,
+                                     unsigned irq)
+{
+       struct uart_port p;
+       int err;
+
+       memset(&p, 0, sizeof(p));
+       p.flags         = UPF_SKIP_TEST;
+       p.iotype        = UPIO_AU;
+       p.uartclk       = freq;
+       p.regshift      = 2;
+       p.type          = PORT_16550A;
+
+       p.mapbase       = base;
+       p.membase       = ioremap_nocache(p.mapbase, PAGE_SIZE);
+       p.line          = line;
+       p.irq           = irq;
+
+       err = early_serial_setup(&p);
+       if (err)
+               printk(KERN_ERR "early serial%d registration failed %d\n",
+                      line, err);
+}
 
 void __init plat_mem_setup(void)
 {
        set_io_port_base(KSEG1);
 
+       detect_mem_size();
        ramips_soc_setup();
 }
+
+static int __init ramips_machine_setup(void)
+{
+       mips_machine_setup(ramips_mach);
+       return 0;
+}
+
+arch_initcall(ramips_machine_setup);
+
+static void __init ramips_generic_init(void)
+{
+}
+
+MIPS_MACHINE(RAMIPS_MACH_GENERIC, "Generic Ralink board", ramips_generic_init);