generic: rename ip175c driver to ip17xx on 2.6.35 as well

[openwrt.git] / target / linux / ar71xx / files / arch / mips / pci / pci-ar71xx.c

diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
index f27c171..7d0eee9 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
+++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c
@@ -1,7 +1,7 @@
 /*
  *  Atheros AR71xx PCI host controller driver
  *
 /*
  *  Atheros AR71xx PCI host controller driver
  *

- *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>

  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Parts of this file are based on Atheros' 2.6.15 BSP
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
  *  Parts of this file are based on Atheros' 2.6.15 BSP


@@ -17,6 +17,7 @@
 #include <linux/bitops.h>
 #include <linux/pci.h>
 #include <linux/pci_regs.h>
 #include <linux/bitops.h>
 #include <linux/pci.h>
 #include <linux/pci_regs.h>

+#include <linux/interrupt.h>

 
 #include <asm/mach-ar71xx/ar71xx.h>
 #include <asm/mach-ar71xx/pci.h>
 
 #include <asm/mach-ar71xx/ar71xx.h>
 #include <asm/mach-ar71xx/pci.h>


@@ -36,27 +37,15 @@
 #define PCI_IDSEL_BASE 0
 #endif
 
 #define PCI_IDSEL_BASE 0
 #endif
 

-static unsigned ar71xx_pci_nr_irqs;
-static struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata;

 static void __iomem *ar71xx_pcicfg_base;
 static void __iomem *ar71xx_pcicfg_base;

-

 static DEFINE_SPINLOCK(ar71xx_pci_lock);
 static DEFINE_SPINLOCK(ar71xx_pci_lock);

+static int ar71xx_pci_fixup_enable;

 
 static inline void ar71xx_pci_delay(void)
 {
        mdelay(AR71XX_PCI_DELAY);
 }
 
 
 static inline void ar71xx_pci_delay(void)
 {
        mdelay(AR71XX_PCI_DELAY);
 }
 

-static inline u32 ar71xx_pcicfg_rr(unsigned int reg)
-{
-       return __raw_readl(ar71xx_pcicfg_base + reg);
-}
-
-static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
-{
-       __raw_writel(val, ar71xx_pcicfg_base + reg);
-}
-

 /* Byte lane enable bits */
 static u8 ble_table[4][4] = {
        {0x0, 0xf, 0xf, 0xf},
 /* Byte lane enable bits */
 static u8 ble_table[4][4] = {
        {0x0, 0xf, 0xf, 0xf},


@@ -93,28 +82,29 @@ static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
        return ret;
 }
 
        return ret;
 }
 

-static int __ar71xx_pci_be_handler(int is_fixup)
+int ar71xx_pci_be_handler(int is_fixup)

 {
 {

+       void __iomem *base = ar71xx_pcicfg_base;

        u32 pci_err;
        u32 ahb_err;
 
        u32 pci_err;
        u32 ahb_err;
 

-       pci_err = ar71xx_pcicfg_rr(PCI_REG_PCI_ERR) & 3;
+       pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3;

        if (pci_err) {
                if (!is_fixup)
                        printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
                                pci_err,
        if (pci_err) {
                if (!is_fixup)
                        printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
                                pci_err,

-                               ar71xx_pcicfg_rr(PCI_REG_PCI_ERR_ADDR));
+                               __raw_readl(base + PCI_REG_PCI_ERR_ADDR));

 
 

-               ar71xx_pcicfg_wr(PCI_REG_PCI_ERR, pci_err);
+               __raw_writel(pci_err, base + PCI_REG_PCI_ERR);

        }
 
        }
 

-       ahb_err = ar71xx_pcicfg_rr(PCI_REG_AHB_ERR) & 1;
+       ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1;

        if (ahb_err) {
                if (!is_fixup)
                        printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
        if (ahb_err) {
                if (!is_fixup)
                        printk(KERN_ALERT "AHB error at AHB address 0x%x\n",

-                               ar71xx_pcicfg_rr(PCI_REG_AHB_ERR_ADDR));
+                               __raw_readl(base + PCI_REG_AHB_ERR_ADDR));

 
 

-               ar71xx_pcicfg_wr(PCI_REG_AHB_ERR, ahb_err);
+               __raw_writel(ahb_err, base + PCI_REG_AHB_ERR);

        }
 
        return ((ahb_err | pci_err) ? 1 : 0);
        }
 
        return ((ahb_err | pci_err) ? 1 : 0);


@@ -123,6 +113,7 @@ static int __ar71xx_pci_be_handler(int is_fixup)
 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
                        unsigned int devfn, int where, int size, u32 cmd)
 {
 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
                        unsigned int devfn, int where, int size, u32 cmd)
 {

+       void __iomem *base = ar71xx_pcicfg_base;

        u32 addr;
 
        addr = ar71xx_pci_bus_addr(bus, devfn, where);
        u32 addr;
 
        addr = ar71xx_pci_bus_addr(bus, devfn, where);


@@ -131,16 +122,17 @@ static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
                bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
                where, size, addr);
 
                bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
                where, size, addr);
 

-       ar71xx_pcicfg_wr(PCI_REG_CFG_AD, addr);
-       ar71xx_pcicfg_wr(PCI_REG_CFG_CBE,
-                       cmd | ar71xx_pci_get_ble(where, size, 0));
+       __raw_writel(addr, base + PCI_REG_CFG_AD);
+       __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
+                    base + PCI_REG_CFG_CBE);

 
 

-       return __ar71xx_pci_be_handler(1);
+       return ar71xx_pci_be_handler(1);

 }
 
 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
                                  int where, int size, u32 *value)
 {
 }
 
 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
                                  int where, int size, u32 *value)
 {

+       void __iomem *base = ar71xx_pcicfg_base;

        static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
        unsigned long flags;
        u32 data;
        static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
        unsigned long flags;
        u32 data;


@@ -158,8 +150,8 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 
                t = PCI_CRP_CMD_READ | (where & ~3);
 
 
                t = PCI_CRP_CMD_READ | (where & ~3);
 

-               ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
-               data = ar71xx_pcicfg_rr(PCI_REG_CRP_RDDATA);
+               __raw_writel(t, base + PCI_REG_CRP_AD_CBE);
+               data = __raw_readl(base + PCI_REG_CRP_RDDATA);

 
                DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
 
 
                DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
 


@@ -170,7 +162,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
                                                PCI_CFG_CMD_READ);
 
                if (err == 0) {
                                                PCI_CFG_CMD_READ);
 
                if (err == 0) {

-                       data = ar71xx_pcicfg_rr(PCI_REG_CFG_RDDATA);
+                       data = __raw_readl(base + PCI_REG_CFG_RDDATA);

                } else {
                        ret = PCIBIOS_DEVICE_NOT_FOUND;
                        data = ~0;
                } else {
                        ret = PCIBIOS_DEVICE_NOT_FOUND;
                        data = ~0;


@@ -190,6 +182,7 @@ static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
                                   int where, int size, u32 value)
 {
 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
                                   int where, int size, u32 value)
 {

+       void __iomem *base = ar71xx_pcicfg_base;

        unsigned long flags;
        int ret;
 
        unsigned long flags;
        int ret;
 


@@ -209,8 +202,8 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 
                DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
 
 
                DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
 

-               ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
-               ar71xx_pcicfg_wr(PCI_REG_CRP_WRDATA, value);
+               __raw_writel(t, base + PCI_REG_CRP_AD_CBE);
+               __raw_writel(value, base + PCI_REG_CRP_WRDATA);

        } else {
                int err;
 
        } else {
                int err;
 


@@ -218,7 +211,7 @@ static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
                                                PCI_CFG_CMD_WRITE);
 
                if (err == 0)
                                                PCI_CFG_CMD_WRITE);
 
                if (err == 0)

-                       ar71xx_pcicfg_wr(PCI_REG_CFG_WRDATA, value);
+                       __raw_writel(value, base + PCI_REG_CFG_WRDATA);

                else
                        ret = PCIBIOS_DEVICE_NOT_FOUND;
        }
                else
                        ret = PCIBIOS_DEVICE_NOT_FOUND;
        }


@@ -231,6 +224,9 @@ static void ar71xx_pci_fixup(struct pci_dev *dev)
 {
        u32 t;
 
 {
        u32 t;
 

+       if (!ar71xx_pci_fixup_enable)
+               return;
+

        if (dev->bus->number != 0 || dev->devfn != 0)
                return;
 
        if (dev->bus->number != 0 || dev->devfn != 0)
                return;
 


@@ -243,10 +239,10 @@ static void ar71xx_pci_fixup(struct pci_dev *dev)
 
        pci_write_config_word(dev, PCI_COMMAND, t);
 }
 
        pci_write_config_word(dev, PCI_COMMAND, t);
 }

-

 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
 
 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
 

-int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
+int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
+                                 uint8_t pin)

 {
        int irq = -1;
        int i;
 {
        int irq = -1;
        int i;


@@ -274,11 +270,6 @@ int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
        return irq;
 }
 
        return irq;
 }
 

-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-       return 0;
-}
-

 static struct pci_ops ar71xx_pci_ops = {
        .read   = ar71xx_pci_read_config,
        .write  = ar71xx_pci_write_config,
 static struct pci_ops ar71xx_pci_ops = {
        .read   = ar71xx_pci_read_config,
        .write  = ar71xx_pci_write_config,


@@ -304,9 +295,87 @@ static struct pci_controller ar71xx_pci_controller = {
        .io_resource    = &ar71xx_pci_io_resource,
 };
 
        .io_resource    = &ar71xx_pci_io_resource,
 };
 

-static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
-                                        struct ar71xx_pci_irq *map)
+static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+       void __iomem *base = ar71xx_reset_base;
+       u32 pending;
+
+       pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
+                 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+
+       if (pending & PCI_INT_DEV0)
+               generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
+
+       else if (pending & PCI_INT_DEV1)
+               generic_handle_irq(AR71XX_PCI_IRQ_DEV1);
+
+       else if (pending & PCI_INT_DEV2)
+               generic_handle_irq(AR71XX_PCI_IRQ_DEV2);
+
+       else if (pending & PCI_INT_CORE)
+               generic_handle_irq(AR71XX_PCI_IRQ_CORE);
+
+       else
+               spurious_interrupt();
+}
+
+static void ar71xx_pci_irq_unmask(unsigned int irq)
+{
+       void __iomem *base = ar71xx_reset_base;
+       u32 t;
+
+       irq -= AR71XX_PCI_IRQ_BASE;
+
+       t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+       __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+
+       /* flush write */
+       (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+}
+
+static void ar71xx_pci_irq_mask(unsigned int irq)
+{
+       void __iomem *base = ar71xx_reset_base;
+       u32 t;
+
+       irq -= AR71XX_PCI_IRQ_BASE;
+
+       t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+       __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+
+       /* flush write */
+       (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+}
+
+static struct irq_chip ar71xx_pci_irq_chip = {
+       .name           = "AR71XX PCI ",
+       .mask           = ar71xx_pci_irq_mask,
+       .unmask         = ar71xx_pci_irq_unmask,
+       .mask_ack       = ar71xx_pci_irq_mask,
+};
+
+static void __init ar71xx_pci_irq_init(void)

 {
 {

+       void __iomem *base = ar71xx_reset_base;
+       int i;
+
+       __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
+       __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
+
+       for (i = AR71XX_PCI_IRQ_BASE;
+            i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
+               irq_desc[i].status = IRQ_DISABLED;
+               set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
+                                        handle_level_irq);
+       }
+
+       set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
+}
+
+int __init ar71xx_pcibios_init(void)
+{
+       void __iomem *ddr_base = ar71xx_ddr_base;
+

        ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
        ar71xx_pci_delay();
 
        ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
        ar71xx_pci_delay();
 


@@ -315,33 +384,26 @@ static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
 
        ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
                                                AR71XX_PCI_CFG_SIZE);
 
        ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
                                                AR71XX_PCI_CFG_SIZE);

-
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
-       ar71xx_ddr_wr(DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
+       if (ar71xx_pcicfg_base == NULL)
+               return -ENOMEM;
+
+       __raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
+       __raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
+       __raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
+       __raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
+       __raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
+       __raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
+       __raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
+       __raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);

 
        ar71xx_pci_delay();
 
        /* clear bus errors */
 
        ar71xx_pci_delay();
 
        /* clear bus errors */

-       (void)__ar71xx_pci_be_handler(1);
-
-       ar71xx_pci_nr_irqs = nr_irqs;
-       ar71xx_pci_irq_map = map;
-       ar71xx_pci_be_handler = __ar71xx_pci_be_handler;
+       (void)ar71xx_pci_be_handler(1);

 
 

+       ar71xx_pci_fixup_enable = 1;
+       ar71xx_pci_irq_init();

        register_pci_controller(&ar71xx_pci_controller);
 
        return 0;
 }
        register_pci_controller(&ar71xx_pci_controller);
 
        return 0;
 }

-
-static int __init __ar71xx_pci_init(void)
-{
-       ar71xx_pci_bios_init = __ar71xx_pci_bios_init;
-       return 0;
-}
-pure_initcall(__ar71xx_pci_init);