[ar71xx] create platform data for the EHCI driver

[openwrt.git] / target / linux / ar71xx / files / include / asm-mips / mach-ar71xx / ar71xx.h

diff --git a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
index 92e662e..78cf1ca 100644 (file)
--- a/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/include/asm-mips/mach-ar71xx/ar71xx.h
@@ -92,16 +92,35 @@ extern u32 ar71xx_ahb_freq;
 extern u32 ar71xx_cpu_freq;
 extern u32 ar71xx_ddr_freq;
 
 extern u32 ar71xx_cpu_freq;
 extern u32 ar71xx_ddr_freq;
 

+enum ar71xx_soc_type {
+       AR71XX_SOC_UNKNOWN,
+       AR71XX_SOC_AR7130,
+       AR71XX_SOC_AR7141,
+       AR71XX_SOC_AR7161,
+       AR71XX_SOC_AR9130,
+       AR71XX_SOC_AR9132
+};
+
+extern enum ar71xx_soc_type ar71xx_soc;
+
+extern unsigned long ar71xx_mach_type;
+
+#define AR71XX_MACH_GENERIC    0
+#define AR71XX_MACH_WP543      1       /* Compex WP543 */
+#define AR71XX_MACH_RB_411     2       /* MikroTik RouterBOARD 411/411A/411AH */
+#define AR71XX_MACH_RB_433     3       /* MikroTik RouterBOARD 433/433AH */
+#define AR71XX_MACH_RB_450     4       /* MikroTik RouterBOARD 450 */
+#define AR71XX_MACH_RB_493     5       /* Mikrotik RouterBOARD 493/493AH */
+#define AR71XX_MACH_AW_NR580   6       /* AzureWave AW-NR580 */
+#define AR71XX_MACH_AP83       7       /* Atheros AP83 */
+

 /*
  * PLL block
  */
 /*
  * PLL block
  */

-#define PLL_REG_CPU_PLL_CFG    0x00
-#define PLL_REG_SEC_PLL_CFG    0x04
-#define PLL_REG_CPU_CLK_CTRL   0x08
-#define PLL_REG_ETH_INT0_CLK   0x10
-#define PLL_REG_ETH_INT1_CLK   0x14
-#define PLL_REG_ETH_EXT_CLK    0x18
-#define PLL_REG_PCI_CLK                0x1c
+#define AR71XX_PLL_REG_CPU_CONFIG      0x00
+#define AR71XX_PLL_REG_SEC_CONFIG      0x04
+#define AR71XX_PLL_REG_ETH0_INT_CLOCK  0x10
+#define AR71XX_PLL_REG_ETH1_INT_CLOCK  0x14

 
 #define AR71XX_PLL_DIV_SHIFT           3
 #define AR71XX_PLL_DIV_MASK            0x1f
 
 #define AR71XX_PLL_DIV_SHIFT           3
 #define AR71XX_PLL_DIV_MASK            0x1f


@@ -112,6 +131,14 @@ extern u32 ar71xx_ddr_freq;
 #define AR71XX_AHB_DIV_SHIFT           20
 #define AR71XX_AHB_DIV_MASK            0x7
 
 #define AR71XX_AHB_DIV_SHIFT           20
 #define AR71XX_AHB_DIV_MASK            0x7
 

+#define AR71XX_ETH0_PLL_SHIFT          17
+#define AR71XX_ETH1_PLL_SHIFT          19
+
+#define AR91XX_PLL_REG_CPU_CONFIG      0x00
+#define AR91XX_PLL_REG_ETH_CONFIG      0x04
+#define AR91XX_PLL_REG_ETH0_INT_CLOCK  0x14
+#define AR91XX_PLL_REG_ETH1_INT_CLOCK  0x18
+

 #define AR91XX_PLL_DIV_SHIFT           0
 #define AR91XX_PLL_DIV_MASK            0x3ff
 #define AR91XX_DDR_DIV_SHIFT           22
 #define AR91XX_PLL_DIV_SHIFT           0
 #define AR91XX_PLL_DIV_MASK            0x3ff
 #define AR91XX_DDR_DIV_SHIFT           22


@@ -119,6 +146,9 @@ extern u32 ar71xx_ddr_freq;
 #define AR91XX_AHB_DIV_SHIFT           19
 #define AR91XX_AHB_DIV_MASK            0x1
 
 #define AR91XX_AHB_DIV_SHIFT           19
 #define AR91XX_AHB_DIV_MASK            0x1
 

+#define AR91XX_ETH0_PLL_SHIFT          20
+#define AR91XX_ETH1_PLL_SHIFT          22
+

 extern void __iomem *ar71xx_pll_base;
 
 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
 extern void __iomem *ar71xx_pll_base;
 
 static inline void ar71xx_pll_wr(unsigned reg, u32 val)


@@ -196,18 +226,23 @@ extern void ar71xx_gpio_function_disable(u32 mask);
 /*
  * DDR_CTRL block
  */
 /*
  * DDR_CTRL block
  */

-#define DDR_REG_PCI_WIN0       0x7c
-#define DDR_REG_PCI_WIN1       0x80
-#define DDR_REG_PCI_WIN2       0x84
-#define DDR_REG_PCI_WIN3       0x88
-#define DDR_REG_PCI_WIN4       0x8c
-#define DDR_REG_PCI_WIN5       0x90
-#define DDR_REG_PCI_WIN6       0x94
-#define DDR_REG_PCI_WIN7       0x98
-#define DDR_REG_FLUSH_GE0      0x9c
-#define DDR_REG_FLUSH_GE1      0xa0
-#define DDR_REG_FLUSH_USB      0xa4
-#define DDR_REG_FLUSH_PCI      0xa8
+#define AR71XX_DDR_REG_PCI_WIN0                0x7c
+#define AR71XX_DDR_REG_PCI_WIN1                0x80
+#define AR71XX_DDR_REG_PCI_WIN2                0x84
+#define AR71XX_DDR_REG_PCI_WIN3                0x88
+#define AR71XX_DDR_REG_PCI_WIN4                0x8c
+#define AR71XX_DDR_REG_PCI_WIN5                0x90
+#define AR71XX_DDR_REG_PCI_WIN6                0x94
+#define AR71XX_DDR_REG_PCI_WIN7                0x98
+#define AR71XX_DDR_REG_FLUSH_GE0       0x9c
+#define AR71XX_DDR_REG_FLUSH_GE1       0xa0
+#define AR71XX_DDR_REG_FLUSH_USB       0xa4
+#define AR71XX_DDR_REG_FLUSH_PCI       0xa8
+
+#define AR91XX_DDR_REG_FLUSH_GE0       0x7c
+#define AR91XX_DDR_REG_FLUSH_GE1       0x80
+#define AR91XX_DDR_REG_FLUSH_USB       0x84
+#define AR91XX_DDR_REG_FLUSH_WMAC      0x88

 
 #define PCI_WIN0_OFFS  0x10000000
 #define PCI_WIN1_OFFS  0x11000000
 
 #define PCI_WIN0_OFFS  0x10000000
 #define PCI_WIN1_OFFS  0x11000000


@@ -275,6 +310,13 @@ extern void ar71xx_ddr_flush(u32 reg);
 #define RESET_REG_PERFC1               0x34
 #define RESET_REG_REV_ID               0x90
 
 #define RESET_REG_PERFC1               0x34
 #define RESET_REG_REV_ID               0x90
 

+#define WDOG_CTRL_LAST_RESET           BIT(31)
+#define WDOG_CTRL_ACTION_MASK          3
+#define WDOG_CTRL_ACTION_NONE          0       /* no action */
+#define WDOG_CTRL_ACTION_GPI           1       /* general purpose interrupt */
+#define WDOG_CTRL_ACTION_NMI           2       /* NMI */
+#define WDOG_CTRL_ACTION_FCR           3       /* full chip reset */
+

 #define MISC_INT_DMA                   BIT(7)
 #define MISC_INT_OHCI                  BIT(6)
 #define MISC_INT_PERFC                 BIT(5)
 #define MISC_INT_DMA                   BIT(7)
 #define MISC_INT_OHCI                  BIT(6)
 #define MISC_INT_PERFC                 BIT(5)


@@ -314,6 +356,7 @@ extern void ar71xx_ddr_flush(u32 reg);
 #define REV_ID_CHIP_AR7141     0xa1
 #define REV_ID_CHIP_AR7161     0xa2
 #define REV_ID_CHIP_AR9130     0xb0
 #define REV_ID_CHIP_AR7141     0xa1
 #define REV_ID_CHIP_AR7161     0xa2
 #define REV_ID_CHIP_AR9130     0xb0

+#define REV_ID_CHIP_AR9132     0xb1

 
 #define REV_ID_REVISION_MASK   0x3
 #define REV_ID_REVISION_SHIFT  2
 
 #define REV_ID_REVISION_MASK   0x3
 #define REV_ID_REVISION_SHIFT  2