[kernel] generic-2.6/2.6.28: show machine name in /proc/cpuinfo if CONFIG_MIPS_MACHIN...

[openwrt.git] / target / linux / brcm63xx / files / include / asm-mips / mach-bcm63xx / bcm63xx_cpu.h

diff --git a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
index 29b61fd..6fa8825 100644 (file)
--- a/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
+++ b/target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
  * compile time if only one CPU support is enabled (idea stolen from
  * arm mach-types)
  */
  * compile time if only one CPU support is enabled (idea stolen from
  * arm mach-types)
  */

+#define BCM6338_CPU_ID         0x6338

 #define BCM6348_CPU_ID         0x6348
 #define BCM6358_CPU_ID         0x6358
 
 #define BCM6348_CPU_ID         0x6348
 #define BCM6358_CPU_ID         0x6358
 


@@ -17,6 +18,19 @@ u16 __bcm63xx_get_cpu_id(void);
 u16 bcm63xx_get_cpu_rev(void);
 unsigned int bcm63xx_get_cpu_freq(void);
 
 u16 bcm63xx_get_cpu_rev(void);
 unsigned int bcm63xx_get_cpu_freq(void);
 

+#ifdef CONFIG_BCM63XX_CPU_6338
+# ifdef bcm63xx_get_cpu_id
+#  undef bcm63xx_get_cpu_id
+#  define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
+#  define BCMCPU_RUNTIME_DETECT
+# else
+#  define bcm63xx_get_cpu_id() BCM6338_CPU_ID
+# endif
+# define BCMCPU_IS_6338()      (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
+#else
+# define BCMCPU_IS_6338()      (0)
+#endif
+

 #ifdef CONFIG_BCM63XX_CPU_6348
 # ifdef bcm63xx_get_cpu_id
 #  undef bcm63xx_get_cpu_id
 #ifdef CONFIG_BCM63XX_CPU_6348
 # ifdef bcm63xx_get_cpu_id
 #  undef bcm63xx_get_cpu_id


@@ -81,11 +95,25 @@ enum bcm63xx_regs_set {
 #define RSET_ENET_SIZE                 2048
 #define RSET_ENETDMA_SIZE              2048
 #define RSET_UART_SIZE                 24
 #define RSET_ENET_SIZE                 2048
 #define RSET_ENETDMA_SIZE              2048
 #define RSET_UART_SIZE                 24

+#define RSET_SPI_SIZE                  256

 #define RSET_UDC_SIZE                  256
 #define RSET_OHCI_SIZE                 256
 #define RSET_EHCI_SIZE                 256
 #define RSET_PCMCIA_SIZE               12
 
 #define RSET_UDC_SIZE                  256
 #define RSET_OHCI_SIZE                 256
 #define RSET_EHCI_SIZE                 256
 #define RSET_PCMCIA_SIZE               12
 

+/*
+ * 6338 register sets base address
+ */
+
+#define BCM_6338_PERF_BASE             (0xfffe0000)
+#define BCM_6338_TIMER_BASE            (0xfffe0000)
+#define BCM_6338_WDT_BASE              (0xfffe001c)
+#define BCM_6338_UART0_BASE            (0xfffe0300)
+#define BCM_6338_GPIO_BASE             (0xfffe0400)
+#define BCM_6338_SPI_BASE              (0xfffe0c00)
+#define BCM_6338_SAR_BASE              (0xfffe2000)
+#define BCM_6338_MEMC_BASE             (0xfffe3100)
+

 /*
  * 6348 register sets base address
  */
 /*
  * 6348 register sets base address
  */


@@ -119,15 +147,15 @@ enum bcm63xx_regs_set {
 #define BCM_6358_PERF_BASE             (0xfffe0000)
 #define BCM_6358_TIMER_BASE            (0xfffe0040)
 #define BCM_6358_WDT_BASE              (0xfffe005c)
 #define BCM_6358_PERF_BASE             (0xfffe0000)
 #define BCM_6358_TIMER_BASE            (0xfffe0040)
 #define BCM_6358_WDT_BASE              (0xfffe005c)

-#define BCM_6358_UART0_BASE            (0xfffe0100)

 #define BCM_6358_GPIO_BASE             (0xfffe0080)
 #define BCM_6358_GPIO_BASE             (0xfffe0080)

-#define BCM_6358_SPI_BASE              (0xdeadbeef)
-#define BCM_6358_UDC0_BASE             (0xfffe0800)
+#define BCM_6358_UART0_BASE            (0xfffe0100)
+#define BCM_6358_UDC0_BASE             (0xfffe0400)
+#define BCM_6358_SPI_BASE              (0xfffe0800)
+#define BCM_6358_MPI_BASE              (0xfffe1000)
+#define BCM_6358_PCMCIA_BASE           (0xfffe1054)

 #define BCM_6358_OHCI0_BASE            (0xfffe1400)
 #define BCM_6358_OHCI_PRIV_BASE                (0xdeadbeef)
 #define BCM_6358_USBH_PRIV_BASE                (0xfffe1500)
 #define BCM_6358_OHCI0_BASE            (0xfffe1400)
 #define BCM_6358_OHCI_PRIV_BASE                (0xdeadbeef)
 #define BCM_6358_USBH_PRIV_BASE                (0xfffe1500)

-#define BCM_6358_MPI_BASE              (0xfffe1000)
-#define BCM_6358_PCMCIA_BASE           (0xfffe1054)

 #define BCM_6358_SDRAM_REGS_BASE       (0xfffe2300)
 #define BCM_6358_DSL_BASE              (0xfffe3000)
 #define BCM_6358_ENET0_BASE            (0xfffe4000)
 #define BCM_6358_SDRAM_REGS_BASE       (0xfffe2300)
 #define BCM_6358_DSL_BASE              (0xfffe3000)
 #define BCM_6358_ENET0_BASE            (0xfffe4000)


@@ -146,6 +174,24 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 #ifdef BCMCPU_RUNTIME_DETECT
        return bcm63xx_regs_base[set];
 #else
 #ifdef BCMCPU_RUNTIME_DETECT
        return bcm63xx_regs_base[set];
 #else

+#ifdef CONFIG_BCM63XX_CPU_6338
+       switch (set) {
+       case RSET_PERF:
+               return BCM_6338_PERF_BASE;
+       case RSET_TIMER:
+               return BCM_6338_TIMER_BASE;
+       case RSET_WDT:
+               return BCM_6338_WDT_BASE;
+       case RSET_UART0:
+               return BCM_6338_UART0_BASE;
+       case RSET_GPIO:
+               return BCM_6338_GPIO_BASE;
+       case RSET_SPI:
+               return BCM_6338_SPI_BASE;
+       case RSET_MEMC:
+               return BCM_6338_MEMC_BASE;
+       }
+#endif

 #ifdef CONFIG_BCM63XX_CPU_6348
        switch (set) {
        case RSET_DSL_LMEM:
 #ifdef CONFIG_BCM63XX_CPU_6348
        switch (set) {
        case RSET_DSL_LMEM:


@@ -249,6 +295,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 enum bcm63xx_irq {
        IRQ_TIMER = 0,
        IRQ_UART0,
 enum bcm63xx_irq {
        IRQ_TIMER = 0,
        IRQ_UART0,

+       IRQ_SPI,

        IRQ_DSL,
        IRQ_ENET0,
        IRQ_ENET1,
        IRQ_DSL,
        IRQ_ENET0,
        IRQ_ENET1,


@@ -264,10 +311,32 @@ enum bcm63xx_irq {
        IRQ_PCMCIA,
 };
 
        IRQ_PCMCIA,
 };
 

+/*
+ * 6338 irqs
+ */
+#define BCM_6338_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
+#define BCM_6338_SPI_IR                        (IRQ_INTERNAL_BASE + 1)
+#define BCM_6338_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
+#define BCM_6338_DG_IRQ                        (IRQ_INTERNAL_BASE + 4)
+#define BCM_6338_DSL_IRQ               (IRQ_INTERNAL_BASE + 5)
+#define BCM_6338_ATM_IRQ               (IRQ_INTERNAL_BASE + 6)
+#define BCM_6338_USBS_IRQ              (IRQ_INTERNAL_BASE + 7)
+#define BCM_6338_ENET0_IRQ             (IRQ_INTERNAL_BASE + 8)
+#define BCM_6338_ENET_PHY_IRQ          (IRQ_INTERNAL_BASE + 9)
+#define BCM_6338_SDRAM_IRQ             (IRQ_INTERNAL_BASE + 10)
+#define BCM_6338_USB_CNTL_RX_DMA_IRQ   (IRQ_INTERNAL_BASE + 11)
+#define BCM_6338_USB_CNTL_TX_DMA_IRQ   (IRQ_INTERNAL_BASE + 12)
+#define BCM_6338_USB_BULK_RX_DMA_IRQ   (IRQ_INTERNAL_BASE + 13)
+#define BCM_6338_USB_BULK_TX_DMA_IRQ   (IRQ_INTERNAL_BASE + 14)
+#define BCM_6338_ENET0_RXDMA_IRQ       (IRQ_INTERNAL_BASE + 15)
+#define BCM_6338_ENET0_TXDMA_IRQ       (IRQ_INTERNAL_BASE + 16)
+#define BCM_6338_SDIO_IRQ              (IRQ_INTERNAL_BASE + 17)
+

 /*
  * 6348 irqs
  */
 #define BCM_6348_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
 /*
  * 6348 irqs
  */
 #define BCM_6348_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)

+#define BCM_6348_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)

 #define BCM_6348_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 #define BCM_6348_DSL_IRQ               (IRQ_INTERNAL_BASE + 4)
 #define BCM_6348_ENET1_IRQ             (IRQ_INTERNAL_BASE + 7)
 #define BCM_6348_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 #define BCM_6348_DSL_IRQ               (IRQ_INTERNAL_BASE + 4)
 #define BCM_6348_ENET1_IRQ             (IRQ_INTERNAL_BASE + 7)


@@ -285,6 +354,7 @@ enum bcm63xx_irq {
  * 6358 irqs
  */
 #define BCM_6358_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)
  * 6358 irqs
  */
 #define BCM_6358_TIMER_IRQ             (IRQ_INTERNAL_BASE + 0)

+#define BCM_6358_SPI_IRQ               (IRQ_INTERNAL_BASE + 1)

 #define BCM_6358_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 #define BCM_6358_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_ENET1_IRQ             (IRQ_INTERNAL_BASE + 6)
 #define BCM_6358_UART0_IRQ             (IRQ_INTERNAL_BASE + 2)
 #define BCM_6358_OHCI0_IRQ             (IRQ_INTERNAL_BASE + 5)
 #define BCM_6358_ENET1_IRQ             (IRQ_INTERNAL_BASE + 6)