/* Clock Control register */
#define PERF_CKCTL_REG 0x4
+#define CKCTL_6338_ADSLPHY_EN (1 << 0)
+#define CKCTL_6338_MPI_EN (1 << 1)
+#define CKCTL_6338_DRAM_EN (1 << 2)
+#define CKCTL_6338_ENET_EN (1 << 4)
+#define CKCTL_6338_USBS_EN (1 << 4)
+#define CKCTL_6338_SAR_EN (1 << 5)
+#define CKCTL_6338_SPI_EN (1 << 9)
+
+#define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \
+ CKCTL_6338_MPI_EN | \
+ CKCTL_6338_ENET_EN | \
+ CKCTL_6338_SAR_EN | \
+ CKCTL_6338_SPI_EN)
+
+#define CKCTL_6345_CPU_EN (1 << 0)
+#define CKCTL_6345_BUS_EN (1 << 1)
+#define CKCTL_6345_EBI_EN (1 << 2)
+#define CKCTL_6345_UART_EN (1 << 3)
+#define CKCTL_6345_ADSLPHY_EN (1 << 4)
+#define CKCTL_6345_ENET_EN (1 << 7)
+#define CKCTL_6345_USBS_EN (1 << 8)
+
+#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
+ CKCTL_6345_USBS_EN | \
+ CKCTL_6345_ADSLPHY_EN)
+
#define CKCTL_6348_ADSLPHY_EN (1 << 0)
#define CKCTL_6348_MPI_EN (1 << 1)
#define CKCTL_6348_SDRAM_EN (1 << 2)
/* Interrupt Mask register */
#define PERF_IRQMASK_REG 0xc
-#define PERF_IRQSTAT_REG 0x10
/* Interrupt Status register */
#define PERF_IRQSTAT_REG 0x10
/* Soft Reset register */
#define PERF_SOFTRESET_REG 0x28
+#define SOFTRESET_6338_SPI_MASK (1 << 0)
+#define SOFTRESET_6338_ENET_MASK (1 << 2)
+#define SOFTRESET_6338_USBH_MASK (1 << 3)
+#define SOFTRESET_6338_USBS_MASK (1 << 4)
+#define SOFTRESET_6338_ADSL_MASK (1 << 5)
+#define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
+#define SOFTRESET_6338_SAR_MASK (1 << 7)
+#define SOFTRESET_6338_ACLC_MASK (1 << 8)
+#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
+#define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
+ SOFTRESET_6338_ENET_MASK | \
+ SOFTRESET_6338_USBH_MASK | \
+ SOFTRESET_6338_USBS_MASK | \
+ SOFTRESET_6338_ADSL_MASK | \
+ SOFTRESET_6338_DMAMEM_MASK | \
+ SOFTRESET_6338_SAR_MASK | \
+ SOFTRESET_6338_ACLC_MASK | \
+ SOFTRESET_6338_ADSLMIPSPLL_MASK)
+
#define SOFTRESET_6348_SPI_MASK (1 << 0)
#define SOFTRESET_6348_ENET_MASK (1 << 2)
#define SOFTRESET_6348_USBH_MASK (1 << 3)
#define SDRAM_CFG_BANK_SHIFT 13
#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
+#define SDRAM_MEM_REG 0xc
+
#define SDRAM_PRIO_REG 0x2C
#define SDRAM_PRIO_MIPS_SHIFT 29
#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
#define DMIPSPLLCFG_N2_SHIFT 29
#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
-#endif /* BCM63XX_REGS_H_ */
+/*************************************************************************
+ * _REG relative to RSET_SPI
+ *************************************************************************/
+
+/* BCM 6338 SPI core */
+#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
+#define SPI_BCM_6338_SPI_INT_STATUS 0x02
+#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
+#define SPI_BCM_6338_SPI_INT_MASK 0x04
+#define SPI_BCM_6338_SPI_ST 0x05
+#define SPI_BCM_6338_SPI_CLK_CFG 0x06
+#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
+#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
+#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
+#define SPI_BCM_6338_SPI_MSG_CTL 0x40
+#define SPI_BCM_6338_SPI_MSG_DATA 0x41
+#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
+#define SPI_BCM_6338_SPI_RX_DATA 0x80
+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
+
+/* BCM 6348 SPI core */
+#define SPI_BCM_6348_SPI_MASK_INT_ST 0x00
+#define SPI_BCM_6348_SPI_INT_STATUS 0x01
+#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
+#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
+#define SPI_BCM_6348_SPI_CLK_CFG 0x05
+#define SPI_BCM_6348_SPI_ST 0x06
+#define SPI_BCM_6348_SPI_INT_MASK 0x07
+#define SPI_BCM_6348_SPI_RX_TAIL 0x08
+#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
+#define SPI_BCM_6348_SPI_MSG_DATA 0x40
+#define SPI_BCM_6348_SPI_MSG_CTL 0x42
+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
+#define SPI_BCM_6348_SPI_RX_DATA 0x80
+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
+
+/* BCM 6358 SPI core */
+#define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */
+
+#define SPI_BCM_6358_SPI_MSG_DATA 0x02
+#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
+
+#define SPI_BCM_6358_SPI_RX_DATA 0x400
+#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
+
+#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
+
+#define SPI_BCM_6358_SPI_INT_STATUS 0x702
+#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
+
+#define SPI_BCM_6358_SPI_INT_MASK 0x704
+
+#define SPI_BCM_6358_SPI_STATUS 0x705
+
+#define SPI_BCM_6358_SPI_CLK_CFG 0x706
+
+#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
+#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
+#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
+
+/* Shared SPI definitions */
+
+/* Message configuration */
+#define SPI_FD_RW 0x00
+#define SPI_HD_W 0x01
+#define SPI_HD_R 0x02
+#define SPI_BYTE_CNT_SHIFT 0
+#define SPI_MSG_TYPE_SHIFT 14
+
+/* Command */
+#define SPI_CMD_NOOP 0x01
+#define SPI_CMD_SOFT_RESET 0x02
+#define SPI_CMD_HARD_RESET 0x04
+#define SPI_CMD_START_IMMEDIATE 0x08
+#define SPI_CMD_COMMAND_SHIFT 0
+#define SPI_CMD_COMMAND_MASK 0x000f
+#define SPI_CMD_DEVICE_ID_SHIFT 4
+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
+#define SPI_CMD_ONE_BYTE_SHIFT 11
+#define SPI_CMD_ONE_WIRE_SHIFT 12
+#define SPI_DEV_ID_0 0
+#define SPI_DEV_ID_1 1
+#define SPI_DEV_ID_2 2
+#define SPI_DEV_ID_3 3
+
+/* Interrupt mask */
+#define SPI_INTR_CMD_DONE 0x01
+#define SPI_INTR_RX_OVERFLOW 0x02
+#define SPI_INTR_TX_UNDERFLOW 0x04
+#define SPI_INTR_TX_OVERFLOW 0x08
+#define SPI_INTR_RX_UNDERFLOW 0x10
+#define SPI_INTR_CLEAR_ALL 0x1f
+
+/* Status */
+#define SPI_RX_EMPTY 0x02
+#define SPI_CMD_BUSY 0x04
+#define SPI_SERIAL_BUSY 0x08
+
+/* Clock configuration */
+#define SPI_CLK_20MHZ 0x00
+#define SPI_CLK_0_391MHZ 0x01
+#define SPI_CLK_0_781MHZ 0x02 /* default */
+#define SPI_CLK_1_563MHZ 0x03
+#define SPI_CLK_3_125MHZ 0x04
+#define SPI_CLK_6_250MHZ 0x05
+#define SPI_CLK_12_50MHZ 0x06
+#define SPI_CLK_25MHZ 0x07
+#define SPI_CLK_MASK 0x07
+#define SPI_SSOFFTIME_MASK 0x38
+#define SPI_SSOFFTIME_SHIFT 3
+#define SPI_BYTE_SWAP 0x80
+
+#endif /* BCM63XX_REGS_H_ */
projects / openwrt.git / blobdiff