ramips: implement clock API for RT305X

[openwrt.git] / target / linux / ramips / files / arch / mips / ralink / rt305x / setup.c

diff --git a/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c b/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c
index 19f340b..6913006 100644 (file)
--- a/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c
+++ b/target/linux/ramips/files/arch/mips/ralink/rt305x/setup.c
@@ -1,7 +1,7 @@
 /*
  * Ralink RT305x SoC specific setup
  *
- * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  *
  * Parts of this file are based on Ralink's 2.6.21 BSP
  *
@@ -13,6 +13,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/mips_machine.h>
 #include <asm/reboot.h>
@@ -21,6 +23,7 @@
 #include <asm/mach-ralink/common.h>
 #include <asm/mach-ralink/rt305x.h>
 #include <asm/mach-ralink/rt305x_regs.h>
+#include "common.h"
 
 static void rt305x_restart(char *command)
 {
@@ -44,27 +47,43 @@ unsigned int __cpuinit get_c0_compare_irq(void)
 
 void __init ramips_soc_setup(void)
 {
+       struct clk *clk;
+
        rt305x_sysc_base = ioremap_nocache(RT305X_SYSC_BASE, PAGE_SIZE);
        rt305x_memc_base = ioremap_nocache(RT305X_MEMC_BASE, PAGE_SIZE);
 
        rt305x_detect_sys_type();
-       rt305x_detect_sys_freq();
+       rt305x_clocks_init();
+
+       clk = clk_get(NULL, "cpu");
+       if (IS_ERR(clk))
+               panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
 
        printk(KERN_INFO "%s running at %lu.%02lu MHz\n", ramips_sys_type,
-               rt305x_cpu_freq / 1000000,
-               (rt305x_cpu_freq % 1000000) * 100 / 1000000);
+               clk_get_rate(clk) / 1000000,
+               (clk_get_rate(clk) % 1000000) * 100 / 1000000);
 
        _machine_restart = rt305x_restart;
        _machine_halt = rt305x_halt;
        pm_power_off = rt305x_halt;
 
-       ramips_early_serial_setup(0, RT305X_UART0_BASE, rt305x_sys_freq,
+       clk = clk_get(NULL, "uart");
+       if (IS_ERR(clk))
+               panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
+
+       ramips_early_serial_setup(0, RT305X_UART0_BASE, clk_get_rate(clk),
                                  RT305X_INTC_IRQ_UART0);
-       ramips_early_serial_setup(1, RT305X_UART1_BASE, rt305x_sys_freq,
+       ramips_early_serial_setup(1, RT305X_UART1_BASE, clk_get_rate(clk),
                                  RT305X_INTC_IRQ_UART1);
 }
 
 void __init plat_time_init(void)
 {
-       mips_hpt_frequency = rt305x_cpu_freq / 2;
+       struct clk *clk;
+
+       clk = clk_get(NULL, "cpu");
+       if (IS_ERR(clk))
+               panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
+
+       mips_hpt_frequency = clk_get_rate(clk) / 2;
 }