+--- a/Documentation/serial/driver
++++ b/Documentation/serial/driver
+@@ -186,6 +186,17 @@
+ Locking: port_sem taken.
+ Interrupts: caller dependent.
+
++ flush_buffer(port)
++ Flush any write buffers, reset any DMA state and stop any
++ ongoing DMA transfers.
++
++ This will be called whenever the port->info->xmit circular
++ buffer is cleared.
++
++ Locking: port->lock taken.
++ Interrupts: locally disabled.
++ This call must not sleep
++
+ set_termios(port,termios,oldtermios)
+ Change the port parameters, including word length, parity, stop
+ bits. Update read_status_mask and ignore_status_mask to indicate
+--- a/arch/avr32/Kconfig
++++ b/arch/avr32/Kconfig
+@@ -47,6 +47,9 @@
+ config GENERIC_TIME
+ def_bool y
+
++config GENERIC_CLOCKEVENTS
++ def_bool y
++
+ config RWSEM_XCHGADD_ALGORITHM
+ def_bool n
+
+@@ -70,6 +73,8 @@
+
+ menu "System Type and features"
+
++source "kernel/time/Kconfig"
++
+ config SUBARCH_AVR32B
+ bool
+ config MMU
+@@ -83,6 +88,7 @@
+ select MMU
+ select PERFORMANCE_COUNTERS
+ select HAVE_GPIO_LIB
++ select GENERIC_ALLOCATOR
+
+ #
+ # CPU types
+@@ -117,6 +123,9 @@
+ if BOARD_ATSTK1000
+ source "arch/avr32/boards/atstk1000/Kconfig"
+ endif
++if BOARD_ATNGW100
++source "arch/avr32/boards/atngw100/Kconfig"
++endif
+
+ choice
+ prompt "Boot loader type"
+@@ -142,6 +151,9 @@
+
+ source "kernel/Kconfig.preempt"
+
++config QUICKLIST
++ def_bool y
++
+ config HAVE_ARCH_BOOTMEM_NODE
+ def_bool n
+
+@@ -180,6 +192,10 @@
+ be dumped to the console when a Non-Maskable Interrupt
+ happens.
+
++config DW_DMAC
++ tristate "Synopsys DesignWare DMA Controller support"
++ default y if CPU_AT32AP7000
++
+ # FPU emulation goes here
+
+ source "kernel/Kconfig.hz"
+@@ -196,6 +212,11 @@
+
+ menu "Power management options"
+
++config ARCH_SUSPEND_POSSIBLE
++ def_bool y
++
++source "kernel/power/Kconfig"
++
+ menu "CPU Frequency scaling"
+
+ source "drivers/cpufreq/Kconfig"
+--- a/arch/avr32/Makefile
++++ b/arch/avr32/Makefile
+@@ -32,6 +32,7 @@
+ core-y += arch/avr32/kernel/
+ core-y += arch/avr32/mm/
+ drivers-$(CONFIG_OPROFILE) += arch/avr32/oprofile/
++drivers-y += arch/avr32/drivers/
+ libs-y += arch/avr32/lib/
+
+ archincdir-$(CONFIG_PLATFORM_AT32AP) := arch-at32ap
--- /dev/null
+++ b/arch/avr32/boards/atngw100/Kconfig
@@ -0,0 +1,12 @@
+ want to rule out the i2c bus driver.
--- a/arch/avr32/boards/atngw100/setup.c
+++ b/arch/avr32/boards/atngw100/setup.c
-@@ -20,7 +20,7 @@
- #include <asm/io.h>
- #include <asm/setup.h>
-
--#include <asm/arch/at32ap7000.h>
-+#include <asm/arch/at32ap700x.h>
- #include <asm/arch/board.h>
+@@ -25,6 +25,13 @@
#include <asm/arch/init.h>
#include <asm/arch/portmux.h>
-@@ -37,11 +37,16 @@
+
++/* Oscillator frequencies. These are board-specific */
++unsigned long at32_board_osc_rates[3] = {
++ [0] = 32768, /* 32.768 kHz on RTC osc */
++ [1] = 20000000, /* 20 MHz on osc0 */
++ [2] = 12000000, /* 12 MHz on osc1 */
++};
++
+ /* Initialized by bootloader-specific startup code. */
+ struct tag *bootloader_tags __initdata;
+
+@@ -37,11 +44,16 @@
static struct spi_board_info spi0_board_info[] __initdata = {
{
.modalias = "mtd_dataflash",
/*
* The next two functions should go away as the boot loader is
* supposed to initialize the macb address registers with a valid
-@@ -124,6 +129,7 @@
+@@ -124,6 +136,7 @@
}
};
static struct i2c_gpio_platform_data i2c_gpio_data = {
.sda_pin = GPIO_PIN_PA(6),
.scl_pin = GPIO_PIN_PA(7),
-@@ -139,6 +145,7 @@
+@@ -139,6 +152,7 @@
.platform_data = &i2c_gpio_data,
},
};
static int __init atngw100_init(void)
{
-@@ -157,6 +164,7 @@
+@@ -157,6 +171,7 @@
set_hw_addr(at32_add_device_eth(1, ð_data[1]));
at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
at32_add_device_usba(0, NULL);
for (i = 0; i < ARRAY_SIZE(ngw_leds); i++) {
-@@ -165,11 +173,15 @@
+@@ -165,11 +180,15 @@
}
platform_device_register(&ngw_gpio_leds);
return 0;
}
---- a/arch/avr32/boards/atstk1000/atstk1000.h
-+++ b/arch/avr32/boards/atstk1000/atstk1000.h
-@@ -12,4 +12,6 @@
+--- a/arch/avr32/boards/atstk1000/Kconfig
++++ b/arch/avr32/boards/atstk1000/Kconfig
+@@ -18,6 +18,10 @@
+ bool "ATSTK1004"
+ select CPU_AT32AP7002
+
++config BOARD_ATSTK1006
++ bool "ATSTK1006"
++ select CPU_AT32AP7000
++
+ endchoice
+
- extern struct atmel_lcdfb_info atstk1000_lcdc_data;
+@@ -102,4 +106,60 @@
+ depends on !BOARD_ATSTK100X_SW1_CUSTOM && !BOARD_ATSTK100X_SW3_CUSTOM
+ default y
-+void atstk1000_setup_j2_leds(void);
++config BOARD_ATSTK100X_ENABLE_AC97
++ bool "Use AC97C instead of ABDAC"
++ help
++ Select this if you want to use the built-in AC97 controller
++ instead of the built-in Audio Bitstream DAC. These share
++ the same I/O pins on the AP7000, so both can't be enabled
++ at the same time.
++
++ Note that the STK1000 kit doesn't ship with an AC97 codec on
++ board, so say N unless you've got an expansion board with an
++ AC97 codec on it that you want to use.
++
++config BOARD_ATSTK1000_CF_HACKS
++ bool "ATSTK1000 CompactFlash hacks"
++ depends on !BOARD_ATSTK100X_SW4_CUSTOM
++ help
++ Select this if you have re-routed the CompactFlash RESET and
++ CD signals to GPIOs on your STK1000. This is necessary for
++ reset and card detection to work properly, although some CF
++ cards may be able to cope without reset.
++
++config BOARD_ATSTK1000_CF_RESET_PIN
++ hex "CompactFlash RESET pin"
++ default 0x30
++ depends on BOARD_ATSTK1000_CF_HACKS
++ help
++ Select which GPIO pin to use for the CompactFlash RESET
++ signal. This is specified as a hexadecimal number and should
++ be defined as 0x20 * gpio_port + pin.
++
++ The default is 0x30, which is pin 16 on PIOB, aka GPIO14.
++
++config BOARD_ATSTK1000_CF_DETECT_PIN
++ hex "CompactFlash DETECT pin"
++ default 0x3e
++ depends on BOARD_ATSTK1000_CF_HACKS
++ help
++ Select which GPIO pin to use for the CompactFlash CD
++ signal. This is specified as a hexadecimal number and should
++ be defined as 0x20 * gpio_port + pin.
++
++ The default is 0x3e, which is pin 30 on PIOB, aka GPIO15.
++
++config BOARD_ATSTK100X_ENABLE_PSIF
++ bool "Enable PSIF peripheral (PS/2 support)"
++ default n
++ help
++ Select this if you want to use the PSIF peripheral to hook up PS/2
++ devices to your STK1000. This will require a hardware modification to
++ work correctly, since PS/2 devices require 5 volt power and signals,
++ while the STK1000 only provides 3.3 volt.
+
- #endif /* __ARCH_AVR32_BOARDS_ATSTK1000_ATSTK1000_H */
++ Say N if you have not modified the hardware to boost the voltage, say
++ Y if you have level convertion hardware or a PS/2 device capable of
++ operating on 3.3 volt.
++
+ endif # stk 1000
+--- a/arch/avr32/boards/atstk1000/Makefile
++++ b/arch/avr32/boards/atstk1000/Makefile
+@@ -2,3 +2,4 @@
+ obj-$(CONFIG_BOARD_ATSTK1002) += atstk1002.o
+ obj-$(CONFIG_BOARD_ATSTK1003) += atstk1003.o
+ obj-$(CONFIG_BOARD_ATSTK1004) += atstk1004.o
++obj-$(CONFIG_BOARD_ATSTK1006) += atstk1002.o
--- a/arch/avr32/boards/atstk1000/atstk1002.c
+++ b/arch/avr32/boards/atstk1000/atstk1002.c
-@@ -11,7 +11,6 @@
- #include <linux/etherdevice.h>
- #include <linux/init.h>
- #include <linux/kernel.h>
--#include <linux/leds.h>
- #include <linux/platform_device.h>
- #include <linux/string.h>
- #include <linux/types.h>
-@@ -22,7 +21,7 @@
-
- #include <asm/io.h>
- #include <asm/setup.h>
--#include <asm/arch/at32ap7000.h>
-+#include <asm/arch/at32ap700x.h>
- #include <asm/arch/board.h>
- #include <asm/arch/init.h>
- #include <asm/arch/portmux.h>
-@@ -49,18 +48,16 @@
- },
- };
+@@ -1,7 +1,7 @@
+ /*
+- * ATSTK1002 daughterboard-specific init code
++ * ATSTK1002/ATSTK1006 daughterboard-specific init code
+ *
+- * Copyright (C) 2005-2006 Atmel Corporation
++ * Copyright (C) 2005-2007 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -28,6 +28,80 @@
--#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
--#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
-+#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
- static struct at73c213_board_info at73c213_data = {
- .ssc_id = 0,
- .shortname = "AVR32 STK1000 external DAC",
- };
- #endif
--#endif
+ #include "atstk1000.h"
--#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
-+#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
- static struct spi_board_info spi0_board_info[] __initdata = {
--#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
-+#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
- {
- /* AT73C213 */
- .modalias = "at73c213",
-@@ -80,12 +77,25 @@
- };
- #endif
++/* Oscillator frequencies. These are board specific */
++unsigned long at32_board_osc_rates[3] = {
++ [0] = 32768, /* 32.768 kHz on RTC osc */
++ [1] = 20000000, /* 20 MHz on osc0 */
++ [2] = 12000000, /* 12 MHz on osc1 */
++};
++
++/*
++ * The ATSTK1006 daughterboard is very similar to the ATSTK1002. Both
++ * have the AT32AP7000 chip on board; the difference is that the
++ * STK1006 has 128 MB SDRAM (the STK1002 uses the 8 MB SDRAM chip on
++ * the STK1000 motherboard) and 256 MB NAND flash (the STK1002 has
++ * none.)
++ *
++ * The RAM difference is handled by the boot loader, so the only
++ * difference we end up handling here is the NAND flash.
++ */
++#ifdef CONFIG_BOARD_ATSTK1006
++#include <linux/mtd/partitions.h>
++#include <asm/arch/smc.h>
++
++static struct smc_timing nand_timing __initdata = {
++ .ncs_read_setup = 0,
++ .nrd_setup = 10,
++ .ncs_write_setup = 0,
++ .nwe_setup = 10,
++
++ .ncs_read_pulse = 30,
++ .nrd_pulse = 15,
++ .ncs_write_pulse = 30,
++ .nwe_pulse = 15,
++
++ .read_cycle = 30,
++ .write_cycle = 30,
++
++ .ncs_read_recover = 0,
++ .nrd_recover = 15,
++ .ncs_write_recover = 0,
++ /* WE# high -> RE# low min 60 ns */
++ .nwe_recover = 50,
++};
++
++static struct smc_config nand_config __initdata = {
++ .bus_width = 1,
++ .nrd_controlled = 1,
++ .nwe_controlled = 1,
++ .nwait_mode = 0,
++ .byte_write = 0,
++ .tdf_cycles = 2,
++ .tdf_mode = 0,
++};
++
++static struct mtd_partition nand_partitions[] = {
++ {
++ .name = "main",
++ .offset = 0x00000000,
++ .size = MTDPART_SIZ_FULL,
++ },
++};
++
++static struct mtd_partition *nand_part_info(int size, int *num_partitions)
++{
++ *num_partitions = ARRAY_SIZE(nand_partitions);
++ return nand_partitions;
++}
++
++static struct atmel_nand_data atstk1006_nand_data __initdata = {
++ .cle = 21,
++ .ale = 22,
++ .rdy_pin = GPIO_PIN_PB(30),
++ .enable_pin = GPIO_PIN_PB(29),
++ .partition_info = nand_part_info,
++};
++#endif
--#ifdef CONFIG_BOARD_ATSTK1002_SPI1
-+#ifdef CONFIG_BOARD_ATSTK100X_SPI1
- static struct spi_board_info spi1_board_info[] __initdata = { {
- /* patch in custom entries here */
+ struct eth_addr {
+ u8 addr[6];
+@@ -83,6 +157,19 @@
} };
#endif
/*
* The next two functions should go away as the boot loader is
* supposed to initialize the macb address registers with a valid
-@@ -141,68 +151,8 @@
- clk_put(pclk);
- }
-
--#ifdef CONFIG_BOARD_ATSTK1002_J2_LED
--
--static struct gpio_led stk_j2_led[] = {
--#ifdef CONFIG_BOARD_ATSTK1002_J2_LED8
--#define LEDSTRING "J2 jumpered to LED8"
-- { .name = "led0:amber", .gpio = GPIO_PIN_PB( 8), },
-- { .name = "led1:amber", .gpio = GPIO_PIN_PB( 9), },
-- { .name = "led2:amber", .gpio = GPIO_PIN_PB(10), },
-- { .name = "led3:amber", .gpio = GPIO_PIN_PB(13), },
-- { .name = "led4:amber", .gpio = GPIO_PIN_PB(14), },
-- { .name = "led5:amber", .gpio = GPIO_PIN_PB(15), },
-- { .name = "led6:amber", .gpio = GPIO_PIN_PB(16), },
-- { .name = "led7:amber", .gpio = GPIO_PIN_PB(30),
-- .default_trigger = "heartbeat", },
--#else /* RGB */
--#define LEDSTRING "J2 jumpered to RGB LEDs"
-- { .name = "r1:red", .gpio = GPIO_PIN_PB( 8), },
-- { .name = "g1:green", .gpio = GPIO_PIN_PB(10), },
-- { .name = "b1:blue", .gpio = GPIO_PIN_PB(14), },
--
-- { .name = "r2:red", .gpio = GPIO_PIN_PB( 9),
-- .default_trigger = "heartbeat", },
-- { .name = "g2:green", .gpio = GPIO_PIN_PB(13), },
-- { .name = "b2:blue", .gpio = GPIO_PIN_PB(15),
-- .default_trigger = "heartbeat", },
-- /* PB16, PB30 unused */
--#endif
--};
--
--static struct gpio_led_platform_data stk_j2_led_data = {
-- .num_leds = ARRAY_SIZE(stk_j2_led),
-- .leds = stk_j2_led,
--};
--
--static struct platform_device stk_j2_led_dev = {
-- .name = "leds-gpio",
-- .id = 2, /* gpio block J2 */
-- .dev = {
-- .platform_data = &stk_j2_led_data,
-- },
--};
--
--static void setup_j2_leds(void)
--{
-- unsigned i;
--
-- for (i = 0; i < ARRAY_SIZE(stk_j2_led); i++)
-- at32_select_gpio(stk_j2_led[i].gpio, AT32_GPIOF_OUTPUT);
--
-- printk("STK1002: " LEDSTRING "\n");
-- platform_device_register(&stk_j2_led_dev);
--}
--
--#else
--static void setup_j2_leds(void)
--{
--}
--#endif
--
--#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
--#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
--static void __init at73c213_set_clk(struct at73c213_board_info *info)
-+#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
-+static void __init atstk1002_setup_extdac(void)
- {
- struct clk *gclk;
- struct clk *pll;
-@@ -220,7 +170,7 @@
- }
-
- at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
-- info->dac_clk = gclk;
-+ at73c213_data.dac_clk = gclk;
-
- err_set_clk:
- clk_put(pll);
-@@ -229,12 +179,16 @@
- err_gclk:
- return;
- }
--#endif
--#endif
-+#else
-+static void __init atstk1002_setup_extdac(void)
-+{
-+
-+}
-+#endif /* CONFIG_BOARD_ATSTK1000_EXTDAC */
-
- void __init setup_board(void)
- {
--#ifdef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
-+#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
- at32_map_usart(0, 1); /* USART 0/B: /dev/ttyS1, IRDA */
- #else
- at32_map_usart(1, 0); /* USART 1/A: /dev/ttyS0, DB9 */
-@@ -271,7 +225,7 @@
+@@ -212,6 +299,12 @@
at32_add_system_devices();
--#ifdef CONFIG_BOARD_ATSTK1002_SW2_CUSTOM
-+#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
++#ifdef CONFIG_BOARD_ATSTK1006
++ smc_set_timing(&nand_config, &nand_timing);
++ smc_set_configuration(3, &nand_config);
++ at32_add_device_nand(0, &atstk1006_nand_data);
++#endif
++
+ #ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
at32_add_device_usart(1);
#else
- at32_add_device_usart(0);
-@@ -281,12 +235,16 @@
- #ifndef CONFIG_BOARD_ATSTK1002_SW6_CUSTOM
- set_hw_addr(at32_add_device_eth(0, ð_data[0]));
- #endif
--#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
-+#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
- at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
- #endif
--#ifdef CONFIG_BOARD_ATSTK1002_SPI1
-+#ifdef CONFIG_BOARD_ATSTK100X_SPI1
+@@ -228,16 +321,30 @@
+ #ifdef CONFIG_BOARD_ATSTK100X_SPI1
at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
#endif
+ at32_add_device_twi(0, NULL, 0);
#ifdef CONFIG_BOARD_ATSTK1002_SW5_CUSTOM
set_hw_addr(at32_add_device_eth(1, ð_data[1]));
#else
-@@ -294,18 +252,23 @@
- fbmem_start, fbmem_size);
+ at32_add_device_lcdc(0, &atstk1000_lcdc_data,
+- fbmem_start, fbmem_size);
++ fbmem_start, fbmem_size, 0);
#endif
at32_add_device_usba(0, NULL);
--#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
-- at32_add_device_ssc(0, ATMEL_SSC_TX);
+#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
-+ at32_add_device_ac97c(0);
++ at32_add_device_ac97c(0, NULL);
+#else
+ at32_add_device_abdac(0);
- #endif
--
-- setup_j2_leds();
--
--#ifndef CONFIG_BOARD_ATSTK1002_SW3_CUSTOM
--#ifndef CONFIG_BOARD_ATSTK1002_SW1_CUSTOM
-- at73c213_set_clk(&at73c213_data);
-+#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
-+ at32_add_device_ssc(0, ATMEL_SSC_TX);
++#endif
+ #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
+ at32_add_device_ssc(0, ATMEL_SSC_TX);
#endif
+ at32_add_device_cf(0, 2, &cf0_data);
+#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
+ at32_add_device_psif(0);
+ at32_add_device_psif(1);
- #endif
++#endif
-+ atstk1000_setup_j2_leds();
-+ atstk1002_setup_extdac();
-+
- return 0;
- }
- postcore_initcall(atstk1002_init);
---- /dev/null
+ atstk1000_setup_j2_leds();
+ atstk1002_setup_extdac();
+--- a/arch/avr32/boards/atstk1000/atstk1003.c
+++ b/arch/avr32/boards/atstk1000/atstk1003.c
-@@ -0,0 +1,185 @@
-+/*
-+ * ATSTK1003 daughterboard-specific init code
-+ *
-+ * Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/string.h>
-+#include <linux/types.h>
-+
-+#include <linux/spi/at73c213.h>
-+#include <linux/spi/spi.h>
-+
-+#include <asm/setup.h>
-+
-+#include <asm/arch/at32ap700x.h>
-+#include <asm/arch/board.h>
-+#include <asm/arch/init.h>
-+#include <asm/arch/portmux.h>
-+
-+#include "atstk1000.h"
-+
-+#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
-+static struct at73c213_board_info at73c213_data = {
-+ .ssc_id = 0,
-+ .shortname = "AVR32 STK1000 external DAC",
-+};
-+#endif
-+
-+#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
-+static struct spi_board_info spi0_board_info[] __initdata = {
-+#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
-+ {
-+ /* AT73C213 */
-+ .modalias = "at73c213",
-+ .max_speed_hz = 200000,
-+ .chip_select = 0,
-+ .mode = SPI_MODE_1,
-+ .platform_data = &at73c213_data,
-+ },
-+#endif
-+ /*
-+ * We can control the LTV350QV LCD panel, but it isn't much
-+ * point since we don't have an LCD controller...
-+ */
-+};
-+#endif
-+
-+#ifdef CONFIG_BOARD_ATSTK100X_SPI1
-+static struct spi_board_info spi1_board_info[] __initdata = { {
-+ /* patch in custom entries here */
-+} };
-+#endif
+@@ -27,6 +27,13 @@
+
+ #include "atstk1000.h"
+
++/* Oscillator frequencies. These are board specific */
++unsigned long at32_board_osc_rates[3] = {
++ [0] = 32768, /* 32.768 kHz on RTC osc */
++ [1] = 20000000, /* 20 MHz on osc0 */
++ [2] = 12000000, /* 12 MHz on osc1 */
++};
+
+ #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
+ static struct at73c213_board_info at73c213_data = {
+ .ssc_id = 0,
+@@ -59,6 +66,19 @@
+ } };
+ #endif
+
+static struct cf_platform_data __initdata cf0_data = {
+#ifdef CONFIG_BOARD_ATSTK1000_CF_HACKS
+ .detect_pin = CONFIG_BOARD_ATSTK1000_CF_DETECT_PIN,
+ .cs = 4,
+};
+
-+#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
-+static void __init atstk1003_setup_extdac(void)
-+{
-+ struct clk *gclk;
-+ struct clk *pll;
-+
-+ gclk = clk_get(NULL, "gclk0");
-+ if (IS_ERR(gclk))
-+ goto err_gclk;
-+ pll = clk_get(NULL, "pll0");
-+ if (IS_ERR(pll))
-+ goto err_pll;
-+
-+ if (clk_set_parent(gclk, pll)) {
-+ pr_debug("STK1000: failed to set pll0 as parent for DAC clock\n");
-+ goto err_set_clk;
-+ }
-+
-+ at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
-+ at73c213_data.dac_clk = gclk;
-+
-+err_set_clk:
-+ clk_put(pll);
-+err_pll:
-+ clk_put(gclk);
-+err_gclk:
-+ return;
-+}
-+#else
-+static void __init atstk1003_setup_extdac(void)
-+{
-+
-+}
-+#endif /* CONFIG_BOARD_ATSTK1000_EXTDAC */
-+
-+void __init setup_board(void)
-+{
-+#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
-+ at32_map_usart(0, 1); /* USART 0/B: /dev/ttyS1, IRDA */
-+#else
-+ at32_map_usart(1, 0); /* USART 1/A: /dev/ttyS0, DB9 */
-+#endif
-+ /* USART 2/unused: expansion connector */
-+ at32_map_usart(3, 2); /* USART 3/C: /dev/ttyS2, DB9 */
-+
-+ at32_setup_serial_console(0);
-+}
-+
-+static int __init atstk1003_init(void)
-+{
-+ /*
-+ * ATSTK1000 uses 32-bit SDRAM interface. Reserve the
-+ * SDRAM-specific pins so that nobody messes with them.
-+ */
-+ at32_reserve_pin(GPIO_PIN_PE(0)); /* DATA[16] */
-+ at32_reserve_pin(GPIO_PIN_PE(1)); /* DATA[17] */
-+ at32_reserve_pin(GPIO_PIN_PE(2)); /* DATA[18] */
-+ at32_reserve_pin(GPIO_PIN_PE(3)); /* DATA[19] */
-+ at32_reserve_pin(GPIO_PIN_PE(4)); /* DATA[20] */
-+ at32_reserve_pin(GPIO_PIN_PE(5)); /* DATA[21] */
-+ at32_reserve_pin(GPIO_PIN_PE(6)); /* DATA[22] */
-+ at32_reserve_pin(GPIO_PIN_PE(7)); /* DATA[23] */
-+ at32_reserve_pin(GPIO_PIN_PE(8)); /* DATA[24] */
-+ at32_reserve_pin(GPIO_PIN_PE(9)); /* DATA[25] */
-+ at32_reserve_pin(GPIO_PIN_PE(10)); /* DATA[26] */
-+ at32_reserve_pin(GPIO_PIN_PE(11)); /* DATA[27] */
-+ at32_reserve_pin(GPIO_PIN_PE(12)); /* DATA[28] */
-+ at32_reserve_pin(GPIO_PIN_PE(13)); /* DATA[29] */
-+ at32_reserve_pin(GPIO_PIN_PE(14)); /* DATA[30] */
-+ at32_reserve_pin(GPIO_PIN_PE(15)); /* DATA[31] */
-+ at32_reserve_pin(GPIO_PIN_PE(26)); /* SDCS */
-+
-+ at32_add_system_devices();
-+
-+#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
-+ at32_add_device_usart(1);
-+#else
-+ at32_add_device_usart(0);
-+#endif
-+ at32_add_device_usart(2);
-+
-+#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
-+ at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
-+#endif
-+#ifdef CONFIG_BOARD_ATSTK100X_SPI1
-+ at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
-+#endif
-+#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
+ #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
+ static void __init atstk1003_setup_extdac(void)
+ {
+@@ -147,12 +167,22 @@
+ at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
+ #endif
+ #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
+- at32_add_device_mci(0);
+ at32_add_device_mci(0, NULL);
-+#endif
-+ at32_add_device_usba(0, NULL);
+ #endif
+ at32_add_device_usba(0, NULL);
+#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
-+ at32_add_device_ac97c(0);
++ at32_add_device_ac97c(0, NULL);
+#else
+ at32_add_device_abdac(0);
+#endif
-+#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
-+ at32_add_device_ssc(0, ATMEL_SSC_TX);
-+#endif
+ #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
+ at32_add_device_ssc(0, ATMEL_SSC_TX);
+ #endif
+ at32_add_device_cf(0, 2, &cf0_data);
+#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
+ at32_add_device_psif(0);
+ at32_add_device_psif(1);
+#endif
-+
-+ atstk1000_setup_j2_leds();
-+ atstk1003_setup_extdac();
-+
-+ return 0;
-+}
-+postcore_initcall(atstk1003_init);
---- /dev/null
+
+ atstk1000_setup_j2_leds();
+ atstk1003_setup_extdac();
+--- a/arch/avr32/boards/atstk1000/atstk1004.c
+++ b/arch/avr32/boards/atstk1000/atstk1004.c
-@@ -0,0 +1,156 @@
-+/*
-+ * ATSTK1003 daughterboard-specific init code
-+ *
-+ * Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/string.h>
-+#include <linux/types.h>
-+
-+#include <linux/spi/at73c213.h>
-+#include <linux/spi/spi.h>
-+
-+#include <video/atmel_lcdc.h>
-+
-+#include <asm/setup.h>
-+
-+#include <asm/arch/at32ap700x.h>
-+#include <asm/arch/board.h>
-+#include <asm/arch/init.h>
-+#include <asm/arch/portmux.h>
-+
-+#include "atstk1000.h"
-+
-+#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
-+static struct at73c213_board_info at73c213_data = {
-+ .ssc_id = 0,
-+ .shortname = "AVR32 STK1000 external DAC",
-+};
-+#endif
-+
-+#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
-+static struct spi_board_info spi0_board_info[] __initdata = {
-+#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
-+ {
-+ /* AT73C213 */
-+ .modalias = "at73c213",
-+ .max_speed_hz = 200000,
-+ .chip_select = 0,
-+ .mode = SPI_MODE_1,
-+ .platform_data = &at73c213_data,
-+ },
-+#endif
-+ {
-+ /* QVGA display */
-+ .modalias = "ltv350qv",
-+ .max_speed_hz = 16000000,
-+ .chip_select = 1,
-+ .mode = SPI_MODE_3,
-+ },
+@@ -29,6 +29,13 @@
+
+ #include "atstk1000.h"
+
++/* Oscillator frequencies. These are board specific */
++unsigned long at32_board_osc_rates[3] = {
++ [0] = 32768, /* 32.768 kHz on RTC osc */
++ [1] = 20000000, /* 20 MHz on osc0 */
++ [2] = 12000000, /* 12 MHz on osc1 */
+};
-+#endif
-+
-+#ifdef CONFIG_BOARD_ATSTK100X_SPI1
-+static struct spi_board_info spi1_board_info[] __initdata = { {
-+ /* patch in custom entries here */
-+} };
-+#endif
-+
-+#ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
-+static void __init atstk1004_setup_extdac(void)
-+{
-+ struct clk *gclk;
-+ struct clk *pll;
-+
-+ gclk = clk_get(NULL, "gclk0");
-+ if (IS_ERR(gclk))
-+ goto err_gclk;
-+ pll = clk_get(NULL, "pll0");
-+ if (IS_ERR(pll))
-+ goto err_pll;
-+
-+ if (clk_set_parent(gclk, pll)) {
-+ pr_debug("STK1000: failed to set pll0 as parent for DAC clock\n");
-+ goto err_set_clk;
-+ }
-+
-+ at32_select_periph(GPIO_PIN_PA(30), GPIO_PERIPH_A, 0);
-+ at73c213_data.dac_clk = gclk;
-+
-+err_set_clk:
-+ clk_put(pll);
-+err_pll:
-+ clk_put(gclk);
-+err_gclk:
-+ return;
-+}
-+#else
-+static void __init atstk1004_setup_extdac(void)
-+{
-+
-+}
-+#endif /* CONFIG_BOARD_ATSTK1000_EXTDAC */
-+
-+void __init setup_board(void)
-+{
-+#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
-+ at32_map_usart(0, 1); /* USART 0/B: /dev/ttyS1, IRDA */
-+#else
-+ at32_map_usart(1, 0); /* USART 1/A: /dev/ttyS0, DB9 */
-+#endif
-+ /* USART 2/unused: expansion connector */
-+ at32_map_usart(3, 2); /* USART 3/C: /dev/ttyS2, DB9 */
-+
-+ at32_setup_serial_console(0);
-+}
-+
-+static int __init atstk1004_init(void)
-+{
-+ at32_add_system_devices();
-+
-+#ifdef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
-+ at32_add_device_usart(1);
-+#else
-+ at32_add_device_usart(0);
-+#endif
-+ at32_add_device_usart(2);
+
-+#ifndef CONFIG_BOARD_ATSTK100X_SW1_CUSTOM
-+ at32_add_device_spi(0, spi0_board_info, ARRAY_SIZE(spi0_board_info));
-+#endif
-+#ifdef CONFIG_BOARD_ATSTK100X_SPI1
-+ at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
-+#endif
-+#ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
+ #ifdef CONFIG_BOARD_ATSTK1000_EXTDAC
+ static struct at73c213_board_info at73c213_data = {
+ .ssc_id = 0,
+@@ -130,14 +137,23 @@
+ at32_add_device_spi(1, spi1_board_info, ARRAY_SIZE(spi1_board_info));
+ #endif
+ #ifndef CONFIG_BOARD_ATSTK100X_SW2_CUSTOM
+- at32_add_device_mci(0);
+ at32_add_device_mci(0, NULL);
-+#endif
-+ at32_add_device_lcdc(0, &atstk1000_lcdc_data,
-+ fbmem_start, fbmem_size);
-+ at32_add_device_usba(0, NULL);
+ #endif
+ at32_add_device_lcdc(0, &atstk1000_lcdc_data,
+- fbmem_start, fbmem_size);
++ fbmem_start, fbmem_size, 0);
+ at32_add_device_usba(0, NULL);
+#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_AC97
-+ at32_add_device_ac97c(0);
++ at32_add_device_ac97c(0, NULL);
+#else
+ at32_add_device_abdac(0);
+#endif
-+#ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
-+ at32_add_device_ssc(0, ATMEL_SSC_TX);
-+#endif
+ #ifndef CONFIG_BOARD_ATSTK100X_SW3_CUSTOM
+ at32_add_device_ssc(0, ATMEL_SSC_TX);
+ #endif
+#ifdef CONFIG_BOARD_ATSTK100X_ENABLE_PSIF
+ at32_add_device_psif(0);
+ at32_add_device_psif(1);
+#endif
-+
-+ atstk1000_setup_j2_leds();
-+ atstk1004_setup_extdac();
-+
-+ return 0;
-+}
-+postcore_initcall(atstk1004_init);
---- a/arch/avr32/boards/atstk1000/Kconfig
-+++ b/arch/avr32/boards/atstk1000/Kconfig
-@@ -1,34 +1,53 @@
- # STK1000 customization
-
--if BOARD_ATSTK1002
-+if BOARD_ATSTK1000
-
--config BOARD_ATSTK1002_CUSTOM
-- bool "Non-default STK-1002 jumper settings"
-+choice
-+ prompt "ATSTK1000 CPU daughterboard type"
-+ default BOARD_ATSTK1002
-+
-+config BOARD_ATSTK1002
-+ bool "ATSTK1002"
-+ select CPU_AT32AP7000
-+
-+config BOARD_ATSTK1003
-+ bool "ATSTK1003"
-+ select CPU_AT32AP7001
-+
-+config BOARD_ATSTK1004
-+ bool "ATSTK1004"
-+ select CPU_AT32AP7002
-+
-+endchoice
-+
-+
-+config BOARD_ATSTK100X_CUSTOM
-+ bool "Non-default STK1002/STK1003/STK1004 jumper settings"
- help
- You will normally leave the jumpers on the CPU card at their
- default settings. If you need to use certain peripherals,
- you will need to change some of those jumpers.
-
--if BOARD_ATSTK1002_CUSTOM
-+if BOARD_ATSTK100X_CUSTOM
-
--config BOARD_ATSTK1002_SW1_CUSTOM
-+config BOARD_ATSTK100X_SW1_CUSTOM
- bool "SW1: use SSC1 (not SPI0)"
- help
- This also prevents using the external DAC as an audio interface,
- and means you can't initialize the on-board QVGA display.
--config BOARD_ATSTK1002_SW2_CUSTOM
-+config BOARD_ATSTK100X_SW2_CUSTOM
- bool "SW2: use IRDA or TIMER0 (not UART-A, MMC/SD, and PS2-A)"
- help
- If you change this you'll want an updated boot loader putting
- the console on UART-C not UART-A.
+ atstk1000_setup_j2_leds();
+ atstk1004_setup_extdac();
+--- a/arch/avr32/configs/atngw100_defconfig
++++ b/arch/avr32/configs/atngw100_defconfig
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.24-rc7
+-# Wed Jan 9 23:20:41 2008
++# Linux kernel version: 2.6.25.4
++# Wed Jun 11 15:23:36 2008
+ #
+ CONFIG_AVR32=y
+ CONFIG_GENERIC_GPIO=y
+@@ -13,10 +13,10 @@
+ CONFIG_GENERIC_IRQ_PROBE=y
+ CONFIG_RWSEM_GENERIC_SPINLOCK=y
+ CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_CLOCKEVENTS=y
+ # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+ # CONFIG_ARCH_HAS_ILOG2_U32 is not set
+ # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+-CONFIG_ARCH_SUPPORTS_OPROFILE=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
+ CONFIG_GENERIC_BUG=y
+@@ -37,17 +37,15 @@
+ CONFIG_BSD_PROCESS_ACCT=y
+ CONFIG_BSD_PROCESS_ACCT_V3=y
+ # CONFIG_TASKSTATS is not set
+-# CONFIG_USER_NS is not set
+-# CONFIG_PID_NS is not set
+ # CONFIG_AUDIT is not set
+ # CONFIG_IKCONFIG is not set
+ CONFIG_LOG_BUF_SHIFT=14
+ # CONFIG_CGROUPS is not set
+-CONFIG_FAIR_GROUP_SCHED=y
+-CONFIG_FAIR_USER_SCHED=y
+-# CONFIG_FAIR_CGROUP_SCHED is not set
++# CONFIG_GROUP_SCHED is not set
+ CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
+ # CONFIG_RELAY is not set
++# CONFIG_NAMESPACES is not set
+ CONFIG_BLK_DEV_INITRD=y
+ CONFIG_INITRAMFS_SOURCE=""
+ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+@@ -61,11 +59,13 @@
+ CONFIG_PRINTK=y
+ CONFIG_BUG=y
+ CONFIG_ELF_CORE=y
++# CONFIG_COMPAT_BRK is not set
+ # CONFIG_BASE_FULL is not set
+ CONFIG_FUTEX=y
+ CONFIG_ANON_INODES=y
+ CONFIG_EPOLL=y
+ CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
+ CONFIG_EVENTFD=y
+ CONFIG_SHMEM=y
+ CONFIG_VM_EVENT_COUNTERS=y
+@@ -73,6 +73,14 @@
+ # CONFIG_SLAB is not set
+ CONFIG_SLUB=y
+ # CONFIG_SLOB is not set
++CONFIG_PROFILING=y
++# CONFIG_MARKERS is not set
++CONFIG_OPROFILE=m
++CONFIG_HAVE_OPROFILE=y
++CONFIG_KPROBES=y
++CONFIG_HAVE_KPROBES=y
++# CONFIG_HAVE_KRETPROBES is not set
++CONFIG_PROC_PAGE_MONITOR=y
+ CONFIG_SLABINFO=y
+ CONFIG_RT_MUTEXES=y
+ # CONFIG_TINY_SHMEM is not set
+@@ -101,10 +109,15 @@
+ CONFIG_DEFAULT_CFQ=y
+ # CONFIG_DEFAULT_NOOP is not set
+ CONFIG_DEFAULT_IOSCHED="cfq"
++CONFIG_CLASSIC_RCU=y
--config BOARD_ATSTK1002_SW3_CUSTOM
-+config BOARD_ATSTK100X_SW3_CUSTOM
- bool "SW3: use TIMER1 (not SSC0 and GCLK)"
- help
- This also prevents using the external DAC as an audio interface.
+ #
+ # System Type and features
+ #
++CONFIG_TICK_ONESHOT=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+ CONFIG_SUBARCH_AVR32B=y
+ CONFIG_MMU=y
+ CONFIG_PERFORMANCE_COUNTERS=y
+@@ -113,6 +126,7 @@
+ CONFIG_CPU_AT32AP7000=y
+ # CONFIG_BOARD_ATSTK1000 is not set
+ CONFIG_BOARD_ATNGW100=y
++CONFIG_BOARD_ATNGW100_I2C_GPIO=y
+ CONFIG_LOADER_U_BOOT=y
--config BOARD_ATSTK1002_SW4_CUSTOM
-+config BOARD_ATSTK100X_SW4_CUSTOM
- bool "SW4: use ISI/Camera (not GPIOs, SPI1, and PS2-B)"
- help
- To use the camera interface you'll need a custom card (on the
-@@ -36,27 +55,29 @@
+ #
+@@ -121,6 +135,7 @@
+ # CONFIG_AP700X_32_BIT_SMC is not set
+ CONFIG_AP700X_16_BIT_SMC=y
+ # CONFIG_AP700X_8_BIT_SMC is not set
++CONFIG_GPIO_DEV=y
+ CONFIG_LOAD_ADDRESS=0x10000000
+ CONFIG_ENTRY_ADDRESS=0x90000000
+ CONFIG_PHYS_OFFSET=0x10000000
+@@ -146,16 +161,26 @@
+ CONFIG_ZONE_DMA_FLAG=0
+ CONFIG_VIRT_TO_BUS=y
+ # CONFIG_OWNERSHIP_TRACE is not set
++CONFIG_NMI_DEBUGGING=y
++CONFIG_DW_DMAC=y
+ # CONFIG_HZ_100 is not set
+ CONFIG_HZ_250=y
+ # CONFIG_HZ_300 is not set
+ # CONFIG_HZ_1000 is not set
+ CONFIG_HZ=250
++# CONFIG_SCHED_HRTICK is not set
+ CONFIG_CMDLINE=""
- config BOARD_ATSTK1002_SW5_CUSTOM
- bool "SW5: use MACB1 (not LCDC)"
-+ depends on BOARD_ATSTK1002
+ #
+ # Power management options
+ #
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
- config BOARD_ATSTK1002_SW6_CUSTOM
- bool "SW6: more GPIOs (not MACB0)"
-+ depends on BOARD_ATSTK1002
+ #
+ # CPU Frequency scaling
+@@ -164,9 +189,9 @@
+ CONFIG_CPU_FREQ_TABLE=y
+ # CONFIG_CPU_FREQ_DEBUG is not set
+ # CONFIG_CPU_FREQ_STAT is not set
+-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+ # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+ # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+ # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+@@ -202,6 +227,7 @@
+ CONFIG_XFRM_USER=y
+ # CONFIG_XFRM_SUB_POLICY is not set
+ # CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
+ CONFIG_NET_KEY=y
+ # CONFIG_NET_KEY_MIGRATE is not set
+ CONFIG_INET=y
+@@ -260,82 +286,33 @@
+ # CONFIG_NETWORK_SECMARK is not set
+ CONFIG_NETFILTER=y
+ # CONFIG_NETFILTER_DEBUG is not set
+-CONFIG_BRIDGE_NETFILTER=y
++# CONFIG_NETFILTER_ADVANCED is not set
- endif # custom
+ #
+ # Core Netfilter Configuration
+ #
+-# CONFIG_NETFILTER_NETLINK is not set
+-CONFIG_NF_CONNTRACK_ENABLED=m
++CONFIG_NETFILTER_NETLINK=m
++CONFIG_NETFILTER_NETLINK_LOG=m
+ CONFIG_NF_CONNTRACK=m
+-CONFIG_NF_CT_ACCT=y
+-CONFIG_NF_CONNTRACK_MARK=y
+-# CONFIG_NF_CONNTRACK_EVENTS is not set
+-CONFIG_NF_CT_PROTO_GRE=m
+-# CONFIG_NF_CT_PROTO_SCTP is not set
+-# CONFIG_NF_CT_PROTO_UDPLITE is not set
+-CONFIG_NF_CONNTRACK_AMANDA=m
+ CONFIG_NF_CONNTRACK_FTP=m
+-CONFIG_NF_CONNTRACK_H323=m
+ CONFIG_NF_CONNTRACK_IRC=m
+-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+-CONFIG_NF_CONNTRACK_PPTP=m
+-CONFIG_NF_CONNTRACK_SANE=m
+ CONFIG_NF_CONNTRACK_SIP=m
+-CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
+ CONFIG_NETFILTER_XTABLES=y
+-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+-# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+-# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+ CONFIG_NETFILTER_XT_TARGET_MARK=m
+-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+ CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+-# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
+-# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+ CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+-# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
+-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+-# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+-# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+-CONFIG_NETFILTER_XT_MATCH_ESP=m
+-CONFIG_NETFILTER_XT_MATCH_HELPER=m
+-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+-CONFIG_NETFILTER_XT_MATCH_MAC=m
+ CONFIG_NETFILTER_XT_MATCH_MARK=m
+ CONFIG_NETFILTER_XT_MATCH_POLICY=m
+-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+-# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+-CONFIG_NETFILTER_XT_MATCH_REALM=m
+-# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+ CONFIG_NETFILTER_XT_MATCH_STATE=m
+-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+-CONFIG_NETFILTER_XT_MATCH_STRING=m
+-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+-# CONFIG_NETFILTER_XT_MATCH_TIME is not set
+-# CONFIG_NETFILTER_XT_MATCH_U32 is not set
+-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
--config BOARD_ATSTK1002_SPI1
-+config BOARD_ATSTK100X_SPI1
- bool "Configure SPI1 controller"
-- depends on !BOARD_ATSTK1002_SW4_CUSTOM
-+ depends on !BOARD_ATSTK100X_SW4_CUSTOM
- help
- All the signals for the second SPI controller are available on
- GPIO lines and accessed through the J1 jumper block. Say "y"
- here to configure that SPI controller.
+ #
+ # IP: Netfilter Configuration
+ #
+ CONFIG_NF_CONNTRACK_IPV4=m
+ CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+-# CONFIG_IP_NF_QUEUE is not set
+ CONFIG_IP_NF_IPTABLES=m
+-CONFIG_IP_NF_MATCH_IPRANGE=m
+-CONFIG_IP_NF_MATCH_TOS=m
+-CONFIG_IP_NF_MATCH_RECENT=m
+-CONFIG_IP_NF_MATCH_ECN=m
+-CONFIG_IP_NF_MATCH_AH=m
+-CONFIG_IP_NF_MATCH_TTL=m
+-CONFIG_IP_NF_MATCH_OWNER=m
+-CONFIG_IP_NF_MATCH_ADDRTYPE=m
+ CONFIG_IP_NF_FILTER=m
+ CONFIG_IP_NF_TARGET_REJECT=m
+ CONFIG_IP_NF_TARGET_LOG=m
+@@ -343,54 +320,25 @@
+ CONFIG_NF_NAT=m
+ CONFIG_NF_NAT_NEEDED=y
+ CONFIG_IP_NF_TARGET_MASQUERADE=m
+-CONFIG_IP_NF_TARGET_REDIRECT=m
+-CONFIG_IP_NF_TARGET_NETMAP=m
+-CONFIG_IP_NF_TARGET_SAME=m
+-CONFIG_NF_NAT_SNMP_BASIC=m
+-CONFIG_NF_NAT_PROTO_GRE=m
+ CONFIG_NF_NAT_FTP=m
+ CONFIG_NF_NAT_IRC=m
+-CONFIG_NF_NAT_TFTP=m
+-CONFIG_NF_NAT_AMANDA=m
+-CONFIG_NF_NAT_PPTP=m
+-CONFIG_NF_NAT_H323=m
++# CONFIG_NF_NAT_TFTP is not set
++# CONFIG_NF_NAT_AMANDA is not set
++# CONFIG_NF_NAT_PPTP is not set
++# CONFIG_NF_NAT_H323 is not set
+ CONFIG_NF_NAT_SIP=m
+ CONFIG_IP_NF_MANGLE=m
+-CONFIG_IP_NF_TARGET_TOS=m
+-CONFIG_IP_NF_TARGET_ECN=m
+-CONFIG_IP_NF_TARGET_TTL=m
+-CONFIG_IP_NF_TARGET_CLUSTERIP=m
+-CONFIG_IP_NF_RAW=m
+-CONFIG_IP_NF_ARPTABLES=m
+-CONFIG_IP_NF_ARPFILTER=m
+-CONFIG_IP_NF_ARP_MANGLE=m
--config BOARD_ATSTK1002_J2_LED
-+config BOARD_ATSTK1000_J2_LED
- bool
-- default BOARD_ATSTK1002_J2_LED8 || BOARD_ATSTK1002_J2_RGB
-+ default BOARD_ATSTK1000_J2_LED8 || BOARD_ATSTK1000_J2_RGB
+ #
+-# IPv6: Netfilter Configuration (EXPERIMENTAL)
++# IPv6: Netfilter Configuration
+ #
+ CONFIG_NF_CONNTRACK_IPV6=m
+-CONFIG_IP6_NF_QUEUE=m
+ CONFIG_IP6_NF_IPTABLES=m
+-CONFIG_IP6_NF_MATCH_RT=m
+-CONFIG_IP6_NF_MATCH_OPTS=m
+-CONFIG_IP6_NF_MATCH_FRAG=m
+-CONFIG_IP6_NF_MATCH_HL=m
+-CONFIG_IP6_NF_MATCH_OWNER=m
+ CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+-CONFIG_IP6_NF_MATCH_AH=m
+-CONFIG_IP6_NF_MATCH_MH=m
+-CONFIG_IP6_NF_MATCH_EUI64=m
+ CONFIG_IP6_NF_FILTER=m
+ CONFIG_IP6_NF_TARGET_LOG=m
+ CONFIG_IP6_NF_TARGET_REJECT=m
+ CONFIG_IP6_NF_MANGLE=m
+-CONFIG_IP6_NF_TARGET_HL=m
+-CONFIG_IP6_NF_RAW=m
+-
+-#
+-# Bridge: Netfilter Configuration
+-#
+-# CONFIG_BRIDGE_NF_EBTABLES is not set
+ # CONFIG_IP_DCCP is not set
+ # CONFIG_IP_SCTP is not set
+ # CONFIG_TIPC is not set
+@@ -407,7 +355,6 @@
+ # CONFIG_ECONET is not set
+ # CONFIG_WAN_ROUTER is not set
+ # CONFIG_NET_SCHED is not set
+-CONFIG_NET_CLS_ROUTE=y
- choice
- prompt "LEDs connected to J2:"
-- depends on LEDS_GPIO && !BOARD_ATSTK1002_SW4_CUSTOM
-+ depends on LEDS_GPIO && !BOARD_ATSTK100X_SW4_CUSTOM
- optional
- help
- Select this if you have jumpered the J2 jumper block to the
-@@ -64,16 +85,77 @@
- IDC cable. A default "heartbeat" trigger is provided, but
- you can of course override this.
-
--config BOARD_ATSTK1002_J2_LED8
-+config BOARD_ATSTK1000_J2_LED8
- bool "LED0..LED7"
- help
- Select this if J2 is jumpered to LED0..LED7 amber leds.
-
--config BOARD_ATSTK1002_J2_RGB
-+config BOARD_ATSTK1000_J2_RGB
- bool "RGB leds"
- help
- Select this if J2 is jumpered to the RGB leds.
-
- endchoice
+ #
+ # Network testing
+@@ -415,6 +362,7 @@
+ # CONFIG_NET_PKTGEN is not set
+ # CONFIG_NET_TCPPROBE is not set
+ # CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
+ # CONFIG_IRDA is not set
+ # CONFIG_BT is not set
+ # CONFIG_AF_RXRPC is not set
+@@ -531,11 +479,18 @@
+ CONFIG_BLK_DEV_RAM=m
+ CONFIG_BLK_DEV_RAM_COUNT=16
+ CONFIG_BLK_DEV_RAM_SIZE=4096
+-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_BLK_DEV_XIP is not set
+ # CONFIG_CDROM_PKTCDVD is not set
+ # CONFIG_ATA_OVER_ETH is not set
+-# CONFIG_MISC_DEVICES is not set
+-# CONFIG_IDE is not set
++CONFIG_MISC_DEVICES=y
++# CONFIG_ATMEL_PWM is not set
++CONFIG_ATMEL_TCLIB=y
++CONFIG_ATMEL_TCB_CLKSRC=y
++CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
++# CONFIG_EEPROM_93CX6 is not set
++# CONFIG_ATMEL_SSC is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HAVE_IDE is not set
--endif # stk 1002
-+config BOARD_ATSTK1000_EXTDAC
-+ bool
-+ depends on !BOARD_ATSTK100X_SW1_CUSTOM && !BOARD_ATSTK100X_SW3_CUSTOM
-+ default y
-+
-+config BOARD_ATSTK100X_ENABLE_AC97
-+ bool "Use AC97C instead of ABDAC"
-+ help
-+ Select this if you want to use the built-in AC97 controller
-+ instead of the built-in Audio Bitstream DAC. These share
-+ the same I/O pins on the AP7000, so both can't be enabled
-+ at the same time.
-+
-+ Note that the STK1000 kit doesn't ship with an AC97 codec on
-+ board, so say N unless you've got an expansion board with an
-+ AC97 codec on it that you want to use.
-+
-+config BOARD_ATSTK1000_CF_HACKS
-+ bool "ATSTK1000 CompactFlash hacks"
-+ depends on !BOARD_ATSTK100X_SW4_CUSTOM
-+ help
-+ Select this if you have re-routed the CompactFlash RESET and
-+ CD signals to GPIOs on your STK1000. This is necessary for
-+ reset and card detection to work properly, although some CF
-+ cards may be able to cope without reset.
-+
-+config BOARD_ATSTK1000_CF_RESET_PIN
-+ hex "CompactFlash RESET pin"
-+ default 0x30
-+ depends on BOARD_ATSTK1000_CF_HACKS
-+ help
-+ Select which GPIO pin to use for the CompactFlash RESET
-+ signal. This is specified as a hexadecimal number and should
-+ be defined as 0x20 * gpio_port + pin.
-+
-+ The default is 0x30, which is pin 16 on PIOB, aka GPIO14.
-+
-+config BOARD_ATSTK1000_CF_DETECT_PIN
-+ hex "CompactFlash DETECT pin"
-+ default 0x3e
-+ depends on BOARD_ATSTK1000_CF_HACKS
-+ help
-+ Select which GPIO pin to use for the CompactFlash CD
-+ signal. This is specified as a hexadecimal number and should
-+ be defined as 0x20 * gpio_port + pin.
-+
-+ The default is 0x3e, which is pin 30 on PIOB, aka GPIO15.
+ #
+ # SCSI device support
+@@ -568,11 +523,13 @@
+ # CONFIG_SMSC_PHY is not set
+ # CONFIG_BROADCOM_PHY is not set
+ # CONFIG_ICPLUS_PHY is not set
++# CONFIG_REALTEK_PHY is not set
+ # CONFIG_FIXED_PHY is not set
+ # CONFIG_MDIO_BITBANG is not set
+ CONFIG_NET_ETHERNET=y
+ # CONFIG_MII is not set
+ CONFIG_MACB=y
++# CONFIG_ENC28J60 is not set
+ # CONFIG_IBM_NEW_EMAC_ZMII is not set
+ # CONFIG_IBM_NEW_EMAC_RGMII is not set
+ # CONFIG_IBM_NEW_EMAC_TAH is not set
+@@ -599,7 +556,6 @@
+ # CONFIG_PPPOL2TP is not set
+ # CONFIG_SLIP is not set
+ CONFIG_SLHC=m
+-# CONFIG_SHAPER is not set
+ # CONFIG_NETCONSOLE is not set
+ # CONFIG_NETPOLL is not set
+ # CONFIG_NET_POLL_CONTROLLER is not set
+@@ -633,6 +589,7 @@
+ #
+ CONFIG_SERIAL_ATMEL=y
+ CONFIG_SERIAL_ATMEL_CONSOLE=y
++CONFIG_SERIAL_ATMEL_PDC=y
+ # CONFIG_SERIAL_ATMEL_TTYAT is not set
+ CONFIG_SERIAL_CORE=y
+ CONFIG_SERIAL_CORE_CONSOLE=y
+@@ -640,8 +597,6 @@
+ # CONFIG_LEGACY_PTYS is not set
+ # CONFIG_IPMI_HANDLER is not set
+ # CONFIG_HW_RANDOM is not set
+-# CONFIG_RTC is not set
+-# CONFIG_GEN_RTC is not set
+ # CONFIG_R3964 is not set
+ # CONFIG_RAW_DRIVER is not set
+ # CONFIG_TCG_TPM is not set
+@@ -659,6 +614,7 @@
+ #
+ # I2C Hardware Bus support
+ #
++CONFIG_I2C_ATMELTWI=m
+ CONFIG_I2C_GPIO=m
+ # CONFIG_I2C_OCORES is not set
+ # CONFIG_I2C_PARPORT_LIGHT is not set
+@@ -669,13 +625,12 @@
+ #
+ # Miscellaneous I2C Chip support
+ #
+-# CONFIG_SENSORS_DS1337 is not set
+-# CONFIG_SENSORS_DS1374 is not set
+ # CONFIG_DS1682 is not set
+ # CONFIG_SENSORS_EEPROM is not set
+ # CONFIG_SENSORS_PCF8574 is not set
+-# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_PCF8575 is not set
+ # CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_TPS65010 is not set
+ # CONFIG_SENSORS_MAX6875 is not set
+ # CONFIG_SENSORS_TSL2550 is not set
+ # CONFIG_I2C_DEBUG_CORE is not set
+@@ -702,9 +657,27 @@
+ # CONFIG_SPI_AT25 is not set
+ CONFIG_SPI_SPIDEV=m
+ # CONFIG_SPI_TLE62X0 is not set
++CONFIG_HAVE_GPIO_LIB=y
+
-+config BOARD_ATSTK100X_ENABLE_PSIF
-+ bool "Enable PSIF peripheral (PS/2 support)"
-+ default n
-+ help
-+ Select this if you want to use the PSIF peripheral to hook up PS/2
-+ devices to your STK1000. This will require a hardware modification to
-+ work correctly, since PS/2 devices require 5 volt power and signals,
-+ while the STK1000 only provides 3.3 volt.
++#
++# GPIO Support
++#
++# CONFIG_DEBUG_GPIO is not set
+
-+ Say N if you have not modified the hardware to boost the voltage, say
-+ Y if you have level convertion hardware or a PS/2 device capable of
-+ operating on 3.3 volt.
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
+
-+endif # stk 1000
---- a/arch/avr32/boards/atstk1000/Makefile
-+++ b/arch/avr32/boards/atstk1000/Makefile
-@@ -1,2 +1,4 @@
- obj-y += setup.o flash.o
- obj-$(CONFIG_BOARD_ATSTK1002) += atstk1002.o
-+obj-$(CONFIG_BOARD_ATSTK1003) += atstk1003.o
-+obj-$(CONFIG_BOARD_ATSTK1004) += atstk1004.o
---- a/arch/avr32/boards/atstk1000/setup.c
-+++ b/arch/avr32/boards/atstk1000/setup.c
-@@ -10,13 +10,17 @@
- #include <linux/bootmem.h>
- #include <linux/fb.h>
- #include <linux/init.h>
-+#include <linux/platform_device.h>
- #include <linux/types.h>
- #include <linux/linkage.h>
++#
++# SPI GPIO expanders:
++#
++# CONFIG_GPIO_MCP23S08 is not set
+ # CONFIG_W1 is not set
+ # CONFIG_POWER_SUPPLY is not set
+ # CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
+ CONFIG_WATCHDOG=y
+ # CONFIG_WATCHDOG_NOWAYOUT is not set
- #include <video/atmel_lcdc.h>
+@@ -757,10 +730,6 @@
+ #
+ # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+ #
+-
+-#
+-# USB Gadget Support
+-#
+ CONFIG_USB_GADGET=y
+ # CONFIG_USB_GADGET_DEBUG is not set
+ # CONFIG_USB_GADGET_DEBUG_FILES is not set
+@@ -787,21 +756,24 @@
+ # CONFIG_USB_FILE_STORAGE_TEST is not set
+ CONFIG_USB_G_SERIAL=m
+ # CONFIG_USB_MIDI_GADGET is not set
+-CONFIG_MMC=m
++# CONFIG_USB_G_PRINTER is not set
++CONFIG_MMC=y
+ # CONFIG_MMC_DEBUG is not set
+ # CONFIG_MMC_UNSAFE_RESUME is not set
- #include <asm/setup.h>
-+
-+#include <asm/arch/at32ap700x.h>
- #include <asm/arch/board.h>
-+#include <asm/arch/portmux.h>
+ #
+ # MMC/SD Card Drivers
+ #
+-CONFIG_MMC_BLOCK=m
++CONFIG_MMC_BLOCK=y
+ CONFIG_MMC_BLOCK_BOUNCE=y
+ # CONFIG_SDIO_UART is not set
- #include "atstk1000.h"
+ #
+ # MMC/SD Host Controller Drivers
+ #
++CONFIG_MMC_ATMELMCI=y
+ CONFIG_MMC_SPI=m
++# CONFIG_MEMSTICK is not set
+ CONFIG_NEW_LEDS=y
+ CONFIG_LEDS_CLASS=y
-@@ -61,3 +65,63 @@
- .default_monspecs = &atstk1000_default_monspecs,
- .guard_time = 2,
- };
-+
-+#ifdef CONFIG_BOARD_ATSTK1000_J2_LED
-+#include <linux/leds.h>
-+
-+static struct gpio_led stk1000_j2_led[] = {
-+#ifdef CONFIG_BOARD_ATSTK1000_J2_LED8
-+#define LEDSTRING "J2 jumpered to LED8"
-+ { .name = "led0:amber", .gpio = GPIO_PIN_PB( 8), },
-+ { .name = "led1:amber", .gpio = GPIO_PIN_PB( 9), },
-+ { .name = "led2:amber", .gpio = GPIO_PIN_PB(10), },
-+ { .name = "led3:amber", .gpio = GPIO_PIN_PB(13), },
-+ { .name = "led4:amber", .gpio = GPIO_PIN_PB(14), },
-+ { .name = "led5:amber", .gpio = GPIO_PIN_PB(15), },
-+ { .name = "led6:amber", .gpio = GPIO_PIN_PB(16), },
-+ { .name = "led7:amber", .gpio = GPIO_PIN_PB(30),
-+ .default_trigger = "heartbeat", },
-+#else /* RGB */
-+#define LEDSTRING "J2 jumpered to RGB LEDs"
-+ { .name = "r1:red", .gpio = GPIO_PIN_PB( 8), },
-+ { .name = "g1:green", .gpio = GPIO_PIN_PB(10), },
-+ { .name = "b1:blue", .gpio = GPIO_PIN_PB(14), },
-+
-+ { .name = "r2:red", .gpio = GPIO_PIN_PB( 9),
-+ .default_trigger = "heartbeat", },
-+ { .name = "g2:green", .gpio = GPIO_PIN_PB(13), },
-+ { .name = "b2:blue", .gpio = GPIO_PIN_PB(15),
-+ .default_trigger = "heartbeat", },
-+ /* PB16, PB30 unused */
-+#endif
-+};
-+
-+static struct gpio_led_platform_data stk1000_j2_led_data = {
-+ .num_leds = ARRAY_SIZE(stk1000_j2_led),
-+ .leds = stk1000_j2_led,
-+};
-+
-+static struct platform_device stk1000_j2_led_dev = {
-+ .name = "leds-gpio",
-+ .id = 2, /* gpio block J2 */
-+ .dev = {
-+ .platform_data = &stk1000_j2_led_data,
-+ },
-+};
-+
-+void __init atstk1000_setup_j2_leds(void)
-+{
-+ unsigned i;
-+
-+ for (i = 0; i < ARRAY_SIZE(stk1000_j2_led); i++)
-+ at32_select_gpio(stk1000_j2_led[i].gpio, AT32_GPIOF_OUTPUT);
-+
-+ printk("STK1000: " LEDSTRING "\n");
-+ platform_device_register(&stk1000_j2_led_dev);
-+}
-+#else /* CONFIG_BOARD_ATSTK1000_J2_LED */
-+void __init atstk1000_setup_j2_leds(void)
-+{
-+
-+}
-+#endif /* CONFIG_BOARD_ATSTK1000_J2_LED */
---- a/arch/avr32/configs/atngw100_defconfig
-+++ b/arch/avr32/configs/atngw100_defconfig
-@@ -1,46 +1,52 @@
+@@ -844,19 +816,22 @@
+ # CONFIG_RTC_DRV_PCF8563 is not set
+ # CONFIG_RTC_DRV_PCF8583 is not set
+ # CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_S35390A is not set
+
+ #
+ # SPI RTC drivers
+ #
+-# CONFIG_RTC_DRV_RS5C348 is not set
+ # CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
+
+ #
+ # Platform RTC drivers
+ #
++# CONFIG_RTC_DRV_DS1511 is not set
+ # CONFIG_RTC_DRV_DS1553 is not set
+-# CONFIG_RTC_DRV_STK17TA8 is not set
+ # CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
+ # CONFIG_RTC_DRV_M48T86 is not set
+ # CONFIG_RTC_DRV_M48T59 is not set
+ # CONFIG_RTC_DRV_V3020 is not set
+@@ -874,25 +849,23 @@
+ #
+ # File systems
+ #
+-CONFIG_EXT2_FS=m
++CONFIG_EXT2_FS=y
+ # CONFIG_EXT2_FS_XATTR is not set
+ # CONFIG_EXT2_FS_XIP is not set
+-CONFIG_EXT3_FS=m
++CONFIG_EXT3_FS=y
+ # CONFIG_EXT3_FS_XATTR is not set
+ # CONFIG_EXT4DEV_FS is not set
+-CONFIG_JBD=m
++CONFIG_JBD=y
+ # CONFIG_REISERFS_FS is not set
+ # CONFIG_JFS_FS is not set
+ # CONFIG_FS_POSIX_ACL is not set
+ # CONFIG_XFS_FS is not set
+ # CONFIG_GFS2_FS is not set
+ # CONFIG_OCFS2_FS is not set
+-# CONFIG_MINIX_FS is not set
+-# CONFIG_ROMFS_FS is not set
++# CONFIG_DNOTIFY is not set
+ CONFIG_INOTIFY=y
+ CONFIG_INOTIFY_USER=y
+ # CONFIG_QUOTA is not set
+-# CONFIG_DNOTIFY is not set
+ # CONFIG_AUTOFS_FS is not set
+ # CONFIG_AUTOFS4_FS is not set
+ CONFIG_FUSE_FS=m
+@@ -923,7 +896,7 @@
+ CONFIG_TMPFS=y
+ # CONFIG_TMPFS_POSIX_ACL is not set
+ # CONFIG_HUGETLB_PAGE is not set
+-CONFIG_CONFIGFS_FS=m
++CONFIG_CONFIGFS_FS=y
+
+ #
+ # Miscellaneous filesystems
+@@ -948,8 +921,10 @@
+ # CONFIG_JFFS2_RUBIN is not set
+ # CONFIG_CRAMFS is not set
+ # CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
+ # CONFIG_HPFS_FS is not set
+ # CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
+ # CONFIG_SYSV_FS is not set
+ # CONFIG_UFS_FS is not set
+ CONFIG_NETWORK_FILESYSTEMS=y
+@@ -1030,11 +1005,6 @@
+ # CONFIG_NLS_KOI8_U is not set
+ CONFIG_NLS_UTF8=m
+ # CONFIG_DLM is not set
+-CONFIG_INSTRUMENTATION=y
+-CONFIG_PROFILING=y
+-CONFIG_OPROFILE=m
+-CONFIG_KPROBES=y
+-# CONFIG_MARKERS is not set
+
+ #
+ # Kernel hacking
+@@ -1053,6 +1023,7 @@
+ # CONFIG_SCHEDSTATS is not set
+ # CONFIG_TIMER_STATS is not set
+ # CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
+ # CONFIG_DEBUG_RT_MUTEXES is not set
+ # CONFIG_RT_MUTEX_TESTER is not set
+ # CONFIG_DEBUG_SPINLOCK is not set
+@@ -1069,9 +1040,10 @@
+ # CONFIG_DEBUG_LIST is not set
+ # CONFIG_DEBUG_SG is not set
+ CONFIG_FRAME_POINTER=y
+-# CONFIG_FORCED_INLINING is not set
+ # CONFIG_BOOT_PRINTK_DELAY is not set
+ # CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_KPROBES_SANITY_TEST is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
+ # CONFIG_LKDTM is not set
+ # CONFIG_FAULT_INJECTION is not set
+ # CONFIG_SAMPLES is not set
+@@ -1084,7 +1056,9 @@
+ # CONFIG_SECURITY_FILE_CAPABILITIES is not set
+ CONFIG_CRYPTO=y
+ CONFIG_CRYPTO_ALGAPI=y
++CONFIG_CRYPTO_AEAD=y
+ CONFIG_CRYPTO_BLKCIPHER=y
++# CONFIG_CRYPTO_SEQIV is not set
+ CONFIG_CRYPTO_HASH=y
+ CONFIG_CRYPTO_MANAGER=y
+ CONFIG_CRYPTO_HMAC=y
+@@ -1103,6 +1077,9 @@
+ CONFIG_CRYPTO_PCBC=m
+ # CONFIG_CRYPTO_LRW is not set
+ # CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CCM is not set
+ # CONFIG_CRYPTO_CRYPTD is not set
+ CONFIG_CRYPTO_DES=y
+ # CONFIG_CRYPTO_FCRYPT is not set
+@@ -1117,12 +1094,14 @@
+ # CONFIG_CRYPTO_KHAZAD is not set
+ # CONFIG_CRYPTO_ANUBIS is not set
+ # CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SALSA20 is not set
+ CONFIG_CRYPTO_DEFLATE=y
+ # CONFIG_CRYPTO_MICHAEL_MIC is not set
+ # CONFIG_CRYPTO_CRC32C is not set
+ # CONFIG_CRYPTO_CAMELLIA is not set
+ # CONFIG_CRYPTO_TEST is not set
+-# CONFIG_CRYPTO_AUTHENC is not set
++CONFIG_CRYPTO_AUTHENC=y
++# CONFIG_CRYPTO_LZO is not set
+ CONFIG_CRYPTO_HW=y
+
+ #
+@@ -1137,10 +1116,7 @@
+ # CONFIG_LIBCRC32C is not set
+ CONFIG_ZLIB_INFLATE=y
+ CONFIG_ZLIB_DEFLATE=y
+-CONFIG_TEXTSEARCH=y
+-CONFIG_TEXTSEARCH_KMP=m
+-CONFIG_TEXTSEARCH_BM=m
+-CONFIG_TEXTSEARCH_FSM=m
++CONFIG_GENERIC_ALLOCATOR=y
+ CONFIG_PLIST=y
+ CONFIG_HAS_IOMEM=y
+ CONFIG_HAS_IOPORT=y
+--- a/arch/avr32/configs/atstk1002_defconfig
++++ b/arch/avr32/configs/atstk1002_defconfig
+@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
--# Linux kernel version: 2.6.22-rc5
--# Sat Jun 23 15:40:05 2007
-+# Linux kernel version: 2.6.24
-+# Thu Mar 6 12:49:54 2008
+-# Linux kernel version: 2.6.24-rc7
+-# Wed Jan 9 23:07:43 2008
++# Linux kernel version: 2.6.25.4
++# Wed Jun 11 15:29:18 2008
#
CONFIG_AVR32=y
CONFIG_GENERIC_GPIO=y
- CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
- CONFIG_HARDIRQS_SW_RESEND=y
+@@ -13,10 +13,10 @@
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+ # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+-CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_BUG=y
- CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
- #
--# Code maturity level options
-+# General setup
- #
- CONFIG_EXPERIMENTAL=y
- CONFIG_BROKEN_ON_SMP=y
- CONFIG_INIT_ENV_ARG_LIMIT=32
--
--#
--# General setup
--#
- CONFIG_LOCALVERSION=""
- # CONFIG_LOCALVERSION_AUTO is not set
- CONFIG_SWAP=y
- CONFIG_SYSVIPC=y
--# CONFIG_IPC_NS is not set
- CONFIG_SYSVIPC_SYSCTL=y
+@@ -36,15 +36,15 @@
CONFIG_POSIX_MQUEUE=y
- CONFIG_BSD_PROCESS_ACCT=y
- CONFIG_BSD_PROCESS_ACCT_V3=y
+ # CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
--# CONFIG_UTS_NS is not set
-+# CONFIG_USER_NS is not set
-+# CONFIG_PID_NS is not set
+-# CONFIG_USER_NS is not set
+-# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+CONFIG_FAIR_GROUP_SCHED=y
-+CONFIG_FAIR_USER_SCHED=y
-+# CONFIG_FAIR_CGROUP_SCHED is not set
+ # CONFIG_CGROUPS is not set
+-# CONFIG_FAIR_GROUP_SCHED is not set
++# CONFIG_GROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
- # CONFIG_RELAY is not set
++CONFIG_SYSFS_DEPRECATED_V2=y
+ CONFIG_RELAY=y
++# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
-@@ -61,35 +67,28 @@
+ CONFIG_INITRAMFS_SOURCE=""
+ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+@@ -58,11 +58,13 @@
+ CONFIG_PRINTK=y
+ CONFIG_BUG=y
+ CONFIG_ELF_CORE=y
++# CONFIG_COMPAT_BRK is not set
+ # CONFIG_BASE_FULL is not set
+ CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
--CONFIG_TIMERFD=y
++CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
--# CONFIG_SLUB_DEBUG is not set
-+CONFIG_SLUB_DEBUG=y
+@@ -70,6 +72,14 @@
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
-+CONFIG_SLABINFO=y
++CONFIG_PROFILING=y
++# CONFIG_MARKERS is not set
++CONFIG_OPROFILE=m
++CONFIG_HAVE_OPROFILE=y
++CONFIG_KPROBES=y
++CONFIG_HAVE_KPROBES=y
++# CONFIG_HAVE_KRETPROBES is not set
++CONFIG_PROC_PAGE_MONITOR=y
+ CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
- CONFIG_BASE_SMALL=1
--
--#
--# Loadable module support
--#
- CONFIG_MODULES=y
- CONFIG_MODULE_UNLOAD=y
- CONFIG_MODULE_FORCE_UNLOAD=y
- # CONFIG_MODVERSIONS is not set
- # CONFIG_MODULE_SRCVERSION_ALL is not set
- CONFIG_KMOD=y
--
--#
--# Block layer
--#
- CONFIG_BLOCK=y
- # CONFIG_LBD is not set
- # CONFIG_BLK_DEV_IO_TRACE is not set
- # CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
+@@ -98,10 +108,15 @@
+ CONFIG_DEFAULT_CFQ=y
+ # CONFIG_DEFAULT_NOOP is not set
+ CONFIG_DEFAULT_IOSCHED="cfq"
++CONFIG_CLASSIC_RCU=y
- #
- # IO Schedulers
-@@ -107,21 +106,28 @@
#
# System Type and features
#
CONFIG_SUBARCH_AVR32B=y
CONFIG_MMU=y
CONFIG_PERFORMANCE_COUNTERS=y
- CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7000=y
- # CONFIG_BOARD_ATSTK1000 is not set
- CONFIG_BOARD_ATNGW100=y
-+CONFIG_BOARD_ATNGW100_I2C_GPIO=y
+@@ -113,12 +128,16 @@
+ CONFIG_BOARD_ATSTK1002=y
+ # CONFIG_BOARD_ATSTK1003 is not set
+ # CONFIG_BOARD_ATSTK1004 is not set
++# CONFIG_BOARD_ATSTK1006 is not set
+ # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
+ # CONFIG_BOARD_ATSTK100X_SPI1 is not set
+ # CONFIG_BOARD_ATSTK1000_J2_LED is not set
+ # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
+ # CONFIG_BOARD_ATSTK1000_J2_RGB is not set
+ CONFIG_BOARD_ATSTK1000_EXTDAC=y
++# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
++# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
++# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
CONFIG_LOADER_U_BOOT=y
#
- # Atmel AVR32 AP options
- #
--# CONFIG_AP7000_32_BIT_SMC is not set
--CONFIG_AP7000_16_BIT_SMC=y
--# CONFIG_AP7000_8_BIT_SMC is not set
-+# CONFIG_AP700X_32_BIT_SMC is not set
-+CONFIG_AP700X_16_BIT_SMC=y
-+# CONFIG_AP700X_8_BIT_SMC is not set
+@@ -127,6 +146,7 @@
+ # CONFIG_AP700X_32_BIT_SMC is not set
+ CONFIG_AP700X_16_BIT_SMC=y
+ # CONFIG_AP700X_8_BIT_SMC is not set
+CONFIG_GPIO_DEV=y
CONFIG_LOAD_ADDRESS=0x10000000
CONFIG_ENTRY_ADDRESS=0x90000000
CONFIG_PHYS_OFFSET=0x10000000
-@@ -141,10 +147,14 @@
- CONFIG_FLATMEM=y
- CONFIG_FLAT_NODE_MEM_MAP=y
- # CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
- CONFIG_SPLIT_PTLOCK_CPUS=4
- # CONFIG_RESOURCES_64BIT is not set
+@@ -152,16 +172,26 @@
CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_VIRT_TO_BUS=y
+ CONFIG_VIRT_TO_BUS=y
# CONFIG_OWNERSHIP_TRACE is not set
-+# CONFIG_NMI_DEBUGGING is not set
++CONFIG_NMI_DEBUGGING=y
+CONFIG_DW_DMAC=y
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
-@@ -153,13 +163,31 @@
+ # CONFIG_HZ_1000 is not set
+ CONFIG_HZ=250
++# CONFIG_SCHED_HRTICK is not set
CONFIG_CMDLINE=""
#
--# Bus options
-+# Power management options
- #
--# CONFIG_ARCH_SUPPORTS_MSI is not set
-
- #
--# PCCARD (PCMCIA/CardBus) support
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
- #
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
- # CONFIG_PCCARD is not set
-
- #
-@@ -213,6 +241,7 @@
- CONFIG_INET_XFRM_MODE_TRANSPORT=y
- CONFIG_INET_XFRM_MODE_TUNNEL=y
- CONFIG_INET_XFRM_MODE_BEET=y
-+# CONFIG_INET_LRO is not set
- CONFIG_INET_DIAG=y
- CONFIG_INET_TCP_DIAG=y
- # CONFIG_TCP_CONG_ADVANCED is not set
-@@ -240,6 +269,7 @@
- # CONFIG_NETWORK_SECMARK is not set
- CONFIG_NETFILTER=y
- # CONFIG_NETFILTER_DEBUG is not set
-+CONFIG_BRIDGE_NETFILTER=y
-
- #
- # Core Netfilter Configuration
-@@ -252,6 +282,7 @@
- # CONFIG_NF_CONNTRACK_EVENTS is not set
- CONFIG_NF_CT_PROTO_GRE=m
- # CONFIG_NF_CT_PROTO_SCTP is not set
-+# CONFIG_NF_CT_PROTO_UDPLITE is not set
- CONFIG_NF_CONNTRACK_AMANDA=m
- CONFIG_NF_CONNTRACK_FTP=m
- CONFIG_NF_CONNTRACK_H323=m
-@@ -269,9 +300,11 @@
- CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
- CONFIG_NETFILTER_XT_TARGET_NFLOG=m
- # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
-+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
- CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
- CONFIG_NETFILTER_XT_MATCH_COMMENT=m
- CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-+# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
- CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
- CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
- # CONFIG_NETFILTER_XT_MATCH_DCCP is not set
-@@ -284,6 +317,7 @@
- CONFIG_NETFILTER_XT_MATCH_MARK=m
- CONFIG_NETFILTER_XT_MATCH_POLICY=m
- CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
- CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
- CONFIG_NETFILTER_XT_MATCH_QUOTA=m
- CONFIG_NETFILTER_XT_MATCH_REALM=m
-@@ -292,6 +326,8 @@
- CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
- CONFIG_NETFILTER_XT_MATCH_STRING=m
- CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-+# CONFIG_NETFILTER_XT_MATCH_TIME is not set
-+# CONFIG_NETFILTER_XT_MATCH_U32 is not set
- CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-
+ # Power management options
#
-@@ -359,13 +395,19 @@
- CONFIG_IP6_NF_MANGLE=m
- CONFIG_IP6_NF_TARGET_HL=m
- CONFIG_IP6_NF_RAW=m
-+
-+#
-+# Bridge: Netfilter Configuration
-+#
-+# CONFIG_BRIDGE_NF_EBTABLES is not set
- # CONFIG_IP_DCCP is not set
- # CONFIG_IP_SCTP is not set
- # CONFIG_TIPC is not set
- # CONFIG_ATM is not set
--# CONFIG_BRIDGE is not set
-+CONFIG_BRIDGE=m
- CONFIG_VLAN_8021Q=m
- # CONFIG_DECNET is not set
-+CONFIG_LLC=m
- # CONFIG_LLC2 is not set
- # CONFIG_IPX is not set
- # CONFIG_ATALK is not set
-@@ -373,10 +415,6 @@
- # CONFIG_LAPB is not set
- # CONFIG_ECONET is not set
- # CONFIG_WAN_ROUTER is not set
--
--#
--# QoS and/or fair queueing
--#
- # CONFIG_NET_SCHED is not set
- CONFIG_NET_CLS_ROUTE=y
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
-@@ -384,6 +422,7 @@
- # Network testing
#
+ # CPU Frequency scaling
+@@ -170,9 +200,9 @@
+ CONFIG_CPU_FREQ_TABLE=y
+ # CONFIG_CPU_FREQ_DEBUG is not set
+ # CONFIG_CPU_FREQ_STAT is not set
+-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+ # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+ # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+ # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+@@ -208,6 +238,7 @@
+ CONFIG_XFRM_USER=m
+ # CONFIG_XFRM_SUB_POLICY is not set
+ # CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
+ CONFIG_NET_KEY=m
+ # CONFIG_NET_KEY_MIGRATE is not set
+ CONFIG_INET=y
+@@ -279,6 +310,7 @@
# CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
+ # CONFIG_NET_TCPPROBE is not set
# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
-@@ -397,6 +436,7 @@
- # CONFIG_MAC80211 is not set
- # CONFIG_IEEE80211 is not set
- # CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-
- #
- # Device Drivers
-@@ -405,16 +445,13 @@
- #
- # Generic Driver Options
- #
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
- CONFIG_STANDALONE=y
- # CONFIG_PREVENT_FIRMWARE_BUILD is not set
- # CONFIG_FW_LOADER is not set
- # CONFIG_DEBUG_DRIVER is not set
- # CONFIG_DEBUG_DEVRES is not set
- # CONFIG_SYS_HYPERVISOR is not set
--
--#
--# Connector - unified userspace <-> kernelspace linker
--#
- # CONFIG_CONNECTOR is not set
- CONFIG_MTD=y
- # CONFIG_MTD_DEBUG is not set
-@@ -434,6 +471,7 @@
- # CONFIG_INFTL is not set
- # CONFIG_RFD_FTL is not set
- # CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-
- #
- # RAM/ROM/Flash chip drivers
-@@ -493,20 +531,8 @@
- # UBI - Unsorted block images
- #
- # CONFIG_MTD_UBI is not set
--
--#
--# Parallel port support
--#
- # CONFIG_PARPORT is not set
--
--#
--# Plug and Play support
--#
--# CONFIG_PNPACPI is not set
--
--#
--# Block devices
--#
-+CONFIG_BLK_DEV=y
- # CONFIG_BLK_DEV_COW_COMMON is not set
- CONFIG_BLK_DEV_LOOP=m
- # CONFIG_BLK_DEV_CRYPTOLOOP is not set
-@@ -517,11 +543,13 @@
- CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+ # CONFIG_AF_RXRPC is not set
+@@ -395,13 +427,18 @@
+ CONFIG_BLK_DEV_RAM=m
+ CONFIG_BLK_DEV_RAM_COUNT=16
+ CONFIG_BLK_DEV_RAM_SIZE=4096
+-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
--
--#
--# Misc devices
--#
--# CONFIG_BLINK is not set
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_ATMEL_PWM is not set
+ CONFIG_MISC_DEVICES=y
++CONFIG_ATMEL_PWM=m
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+# CONFIG_ATMEL_SSC is not set
- # CONFIG_IDE is not set
+ # CONFIG_EEPROM_93CX6 is not set
+ CONFIG_ATMEL_SSC=m
+-# CONFIG_IDE is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HAVE_IDE is not set
#
-@@ -529,30 +557,42 @@
- #
- # CONFIG_RAID_ATTRS is not set
- # CONFIG_SCSI is not set
-+# CONFIG_SCSI_DMA is not set
- # CONFIG_SCSI_NETLINK is not set
- # CONFIG_ATA is not set
--
--#
--# Multi-device support (RAID and LVM)
--#
+ # SCSI device support
+@@ -444,6 +481,7 @@
+ # CONFIG_SCSI_LOWLEVEL is not set
+ CONFIG_ATA=m
+ # CONFIG_ATA_NONSTANDARD is not set
++# CONFIG_SATA_MV is not set
+ CONFIG_PATA_AT32=m
+ # CONFIG_PATA_PLATFORM is not set
# CONFIG_MD is not set
--
--#
--# Network device support
--#
- CONFIG_NETDEVICES=y
-+# CONFIG_NETDEVICES_MULTIQUEUE is not set
- # CONFIG_DUMMY is not set
- # CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
- # CONFIG_EQUALIZER is not set
- CONFIG_TUN=m
--# CONFIG_PHYLIB is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-
- #
--# Ethernet (10 or 100Mbit)
-+# MII PHY device drivers
- #
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
+@@ -469,11 +507,13 @@
+ # CONFIG_SMSC_PHY is not set
+ # CONFIG_BROADCOM_PHY is not set
+ # CONFIG_ICPLUS_PHY is not set
++# CONFIG_REALTEK_PHY is not set
+ # CONFIG_FIXED_PHY is not set
+ # CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
--CONFIG_MII=y
-+# CONFIG_MII is not set
+ # CONFIG_MII is not set
CONFIG_MACB=y
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
- # CONFIG_NETDEV_1000 is not set
- # CONFIG_NETDEV_10000 is not set
-
-@@ -571,21 +611,14 @@
- CONFIG_PPP_BSDCOMP=m
- CONFIG_PPP_MPPE=m
- CONFIG_PPPOE=m
-+# CONFIG_PPPOL2TP is not set
++# CONFIG_ENC28J60 is not set
+ # CONFIG_IBM_NEW_EMAC_ZMII is not set
+ # CONFIG_IBM_NEW_EMAC_RGMII is not set
+ # CONFIG_IBM_NEW_EMAC_TAH is not set
+@@ -500,7 +540,6 @@
+ # CONFIG_PPPOL2TP is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
- # CONFIG_SHAPER is not set
+-# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
--
--#
--# ISDN subsystem
--#
- # CONFIG_ISDN is not set
--
--#
--# Telephony Support
--#
- # CONFIG_PHONE is not set
-
- #
-@@ -615,28 +648,57 @@
+@@ -568,6 +607,7 @@
#
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
# CONFIG_SERIAL_ATMEL_TTYAT is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
- CONFIG_UNIX98_PTYS=y
+@@ -575,8 +615,6 @@
# CONFIG_LEGACY_PTYS is not set
--
--#
--# IPMI
--#
# CONFIG_IPMI_HANDLER is not set
--# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
- # CONFIG_RTC is not set
- # CONFIG_GEN_RTC is not set
+-# CONFIG_RTC is not set
+-# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
--
--#
--# TPM devices
--#
# CONFIG_TCG_TPM is not set
--# CONFIG_I2C is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
+@@ -594,6 +632,7 @@
+ #
+ # I2C Hardware Bus support
+ #
++CONFIG_I2C_ATMELTWI=m
+ CONFIG_I2C_GPIO=m
+ # CONFIG_I2C_OCORES is not set
+ # CONFIG_I2C_PARPORT_LIGHT is not set
+@@ -604,13 +643,12 @@
+ #
+ # Miscellaneous I2C Chip support
+ #
+-# CONFIG_SENSORS_DS1337 is not set
+-# CONFIG_SENSORS_DS1374 is not set
+ # CONFIG_DS1682 is not set
+ # CONFIG_SENSORS_EEPROM is not set
+ # CONFIG_SENSORS_PCF8574 is not set
+-# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_PCF8575 is not set
+ # CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_TPS65010 is not set
+ # CONFIG_SENSORS_MAX6875 is not set
+ # CONFIG_SENSORS_TSL2550 is not set
+ # CONFIG_I2C_DEBUG_CORE is not set
+@@ -637,9 +675,27 @@
+ # CONFIG_SPI_AT25 is not set
+ CONFIG_SPI_SPIDEV=m
+ # CONFIG_SPI_TLE62X0 is not set
++CONFIG_HAVE_GPIO_LIB=y
+
+#
-+# I2C Algorithms
++# GPIO Support
+#
-+CONFIG_I2C_ALGOBIT=m
-+# CONFIG_I2C_ALGOPCF is not set
-+# CONFIG_I2C_ALGOPCA is not set
++# CONFIG_DEBUG_GPIO is not set
+
+#
-+# I2C Hardware Bus support
++# I2C GPIO expanders:
+#
-+CONFIG_I2C_ATMELTWI=m
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_SIMTEC is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+# CONFIG_I2C_STUB is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
+
+#
-+# Miscellaneous I2C Chip support
++# SPI GPIO expanders:
+#
-+# CONFIG_SENSORS_DS1337 is not set
-+# CONFIG_SENSORS_DS1374 is not set
-+# CONFIG_DS1682 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
++# CONFIG_GPIO_MCP23S08 is not set
+ # CONFIG_W1 is not set
+ # CONFIG_POWER_SUPPLY is not set
+ # CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
+ CONFIG_WATCHDOG=y
+ # CONFIG_WATCHDOG_NOWAYOUT is not set
+@@ -732,12 +788,18 @@
#
- # SPI support
-@@ -655,13 +717,25 @@
- # SPI Protocol Masters
+ # Generic devices
#
- # CONFIG_SPI_AT25 is not set
--# CONFIG_SPI_SPIDEV is not set
-+CONFIG_SPI_SPIDEV=m
-+# CONFIG_SPI_TLE62X0 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
++CONFIG_SND_AC97_CODEC=m
+ # CONFIG_SND_DUMMY is not set
+ # CONFIG_SND_MTPAV is not set
+ # CONFIG_SND_SERIAL_U16550 is not set
+ # CONFIG_SND_MPU401 is not set
#
--# Dallas's 1-wire bus
-+# Watchdog Device Drivers
- #
--# CONFIG_W1 is not set
--# CONFIG_HWMON is not set
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32AP700X_WDT=y
++# AVR32 devices
++#
++CONFIG_SND_ATMEL_AC97=m
+
+#
-+# Sonics Silicon Backplane
+ # SPI devices
+ #
+ CONFIG_SND_AT73C213=m
+@@ -753,9 +815,14 @@
+ #
+
+ #
++# ALSA SoC audio for Freescale SOCs
+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
++
++#
+ # Open Sound System
+ #
+ # CONFIG_SOUND_PRIME is not set
++CONFIG_AC97_BUS=m
+ # CONFIG_HID_SUPPORT is not set
+ CONFIG_USB_SUPPORT=y
+ # CONFIG_USB_ARCH_HAS_HCD is not set
+@@ -765,10 +832,6 @@
+ #
+ # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+ #
+-
+-#
+-# USB Gadget Support
+-#
+ CONFIG_USB_GADGET=y
+ # CONFIG_USB_GADGET_DEBUG is not set
+ # CONFIG_USB_GADGET_DEBUG_FILES is not set
+@@ -796,27 +859,31 @@
+ # CONFIG_USB_FILE_STORAGE_TEST is not set
+ CONFIG_USB_G_SERIAL=m
+ # CONFIG_USB_MIDI_GADGET is not set
+-CONFIG_MMC=m
++# CONFIG_USB_G_PRINTER is not set
++CONFIG_MMC=y
+ # CONFIG_MMC_DEBUG is not set
+ # CONFIG_MMC_UNSAFE_RESUME is not set
#
- # Multifunction device drivers
-@@ -678,23 +752,21 @@
+ # MMC/SD Card Drivers
+ #
+-CONFIG_MMC_BLOCK=m
++CONFIG_MMC_BLOCK=y
+ CONFIG_MMC_BLOCK_BOUNCE=y
+ # CONFIG_SDIO_UART is not set
+
#
- # Graphics support
+ # MMC/SD Host Controller Drivers
#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+# CONFIG_FB is not set
- # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
++CONFIG_MMC_ATMELMCI=y
+ CONFIG_MMC_SPI=m
++# CONFIG_MEMSTICK is not set
+ CONFIG_NEW_LEDS=y
+ CONFIG_LEDS_CLASS=m
#
- # Display device support
+ # LED drivers
#
- # CONFIG_DISPLAY_SUPPORT is not set
--# CONFIG_VGASTATE is not set
--# CONFIG_FB is not set
++CONFIG_LEDS_ATMEL_PWM=m
+ CONFIG_LEDS_GPIO=m
#
- # Sound
+@@ -853,19 +920,22 @@
+ # CONFIG_RTC_DRV_PCF8563 is not set
+ # CONFIG_RTC_DRV_PCF8583 is not set
+ # CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_S35390A is not set
+
#
- # CONFIG_SOUND is not set
--
--#
--# USB support
--#
-+CONFIG_USB_SUPPORT=y
- # CONFIG_USB_ARCH_HAS_HCD is not set
- # CONFIG_USB_ARCH_HAS_OHCI is not set
- # CONFIG_USB_ARCH_HAS_EHCI is not set
-@@ -706,12 +778,48 @@
+ # SPI RTC drivers
#
- # USB Gadget Support
+-# CONFIG_RTC_DRV_RS5C348 is not set
+ # CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
+
#
--# CONFIG_USB_GADGET is not set
--# CONFIG_MMC is not set
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA2XX is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
-+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+# CONFIG_MMC_BLOCK_BOUNCE is not set
-+# CONFIG_SDIO_UART is not set
-
- #
--# LED devices
-+# MMC/SD Host Controller Drivers
- #
-+CONFIG_MMC_ATMELMCI=y
-+CONFIG_MMC_SPI=m
- CONFIG_NEW_LEDS=y
- CONFIG_LEDS_CLASS=y
-
-@@ -726,53 +834,71 @@
- CONFIG_LEDS_TRIGGERS=y
- CONFIG_LEDS_TRIGGER_TIMER=y
- CONFIG_LEDS_TRIGGER_HEARTBEAT=y
--
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
-
- #
--# LED drivers
--#
--
--#
--# LED Triggers
--#
--
--#
--# InfiniBand support
-+# RTC interfaces
- #
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
-
- #
--# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-+# I2C RTC drivers
- #
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
-
+ # Platform RTC drivers
#
--# Real Time Clock
-+# SPI RTC drivers
- #
--# CONFIG_RTC_CLASS is not set
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
-
- #
--# DMA Engine support
-+# Platform RTC drivers
- #
--# CONFIG_DMA_ENGINE is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
+ # CONFIG_RTC_DRV_DS1553 is not set
+-# CONFIG_RTC_DRV_STK17TA8 is not set
+ # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-
- #
--# DMA Clients
-+# on-CPU RTC drivers
- #
-+CONFIG_RTC_DRV_AT32AP700X=y
-
- #
--# DMA Devices
-+# Userspace I/O
- #
-+# CONFIG_UIO is not set
-
+ # CONFIG_RTC_DRV_M48T86 is not set
+ # CONFIG_RTC_DRV_M48T59 is not set
+ # CONFIG_RTC_DRV_V3020 is not set
+@@ -883,13 +953,13 @@
#
# File systems
#
--CONFIG_EXT2_FS=y
-+CONFIG_EXT2_FS=m
+-CONFIG_EXT2_FS=m
++CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
--CONFIG_EXT3_FS=y
-+CONFIG_EXT3_FS=m
+-CONFIG_EXT3_FS=m
++CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
# CONFIG_EXT4DEV_FS is not set
--CONFIG_JBD=y
--# CONFIG_JBD_DEBUG is not set
-+CONFIG_JBD=m
+-CONFIG_JBD=m
++CONFIG_JBD=y
+ # CONFIG_JBD_DEBUG is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
- # CONFIG_FS_POSIX_ACL is not set
-@@ -781,7 +907,8 @@
+@@ -897,12 +967,10 @@
+ # CONFIG_XFS_FS is not set
+ # CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
- # CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
--# CONFIG_INOTIFY is not set
-+CONFIG_INOTIFY=y
-+CONFIG_INOTIFY_USER=y
+-CONFIG_MINIX_FS=m
+-# CONFIG_ROMFS_FS is not set
++# CONFIG_DNOTIFY is not set
+ CONFIG_INOTIFY=y
+ CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
- # CONFIG_DNOTIFY is not set
+-# CONFIG_DNOTIFY is not set
# CONFIG_AUTOFS_FS is not set
-@@ -814,7 +941,6 @@
+ # CONFIG_AUTOFS4_FS is not set
+ CONFIG_FUSE_FS=m
+@@ -933,7 +1001,7 @@
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
--CONFIG_RAMFS=y
- CONFIG_CONFIGFS_FS=y
+-# CONFIG_CONFIGFS_FS is not set
++CONFIG_CONFIGFS_FS=y
#
-@@ -830,10 +956,12 @@
- CONFIG_JFFS2_FS=y
- CONFIG_JFFS2_FS_DEBUG=0
- CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
- # CONFIG_JFFS2_SUMMARY is not set
- # CONFIG_JFFS2_FS_XATTR is not set
- # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
- CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
- CONFIG_JFFS2_RTIME=y
+ # Miscellaneous filesystems
+@@ -957,8 +1025,10 @@
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_CRAMFS is not set
-@@ -842,19 +970,21 @@
+ # CONFIG_VXFS_FS is not set
++CONFIG_MINIX_FS=m
+ # CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
--
--#
--# Network File Systems
--#
-+CONFIG_NETWORK_FILESYSTEMS=y
- CONFIG_NFS_FS=y
- CONFIG_NFS_V3=y
- # CONFIG_NFS_V3_ACL is not set
- # CONFIG_NFS_V4 is not set
- # CONFIG_NFS_DIRECTIO is not set
--# CONFIG_NFSD is not set
-+CONFIG_NFSD=m
-+CONFIG_NFSD_V3=y
-+# CONFIG_NFSD_V3_ACL is not set
-+# CONFIG_NFSD_V4 is not set
-+CONFIG_NFSD_TCP=y
- CONFIG_ROOT_NFS=y
- CONFIG_LOCKD=y
- CONFIG_LOCKD_V4=y
-+CONFIG_EXPORTFS=m
- CONFIG_NFS_COMMON=y
- CONFIG_SUNRPC=y
- # CONFIG_SUNRPC_BIND34 is not set
-@@ -871,23 +1001,18 @@
- # CONFIG_NCP_FS is not set
- # CONFIG_CODA_FS is not set
- # CONFIG_AFS_FS is not set
--# CONFIG_9P_FS is not set
-
- #
- # Partition Types
- #
- # CONFIG_PARTITION_ADVANCED is not set
- CONFIG_MSDOS_PARTITION=y
--
--#
--# Native Language Support
--#
--CONFIG_NLS=y
-+CONFIG_NLS=m
- CONFIG_NLS_DEFAULT="iso8859-1"
--# CONFIG_NLS_CODEPAGE_437 is not set
-+CONFIG_NLS_CODEPAGE_437=m
- # CONFIG_NLS_CODEPAGE_737 is not set
- # CONFIG_NLS_CODEPAGE_775 is not set
--CONFIG_NLS_CODEPAGE_850=y
-+CONFIG_NLS_CODEPAGE_850=m
- # CONFIG_NLS_CODEPAGE_852 is not set
- # CONFIG_NLS_CODEPAGE_855 is not set
- # CONFIG_NLS_CODEPAGE_857 is not set
-@@ -908,7 +1033,7 @@
- # CONFIG_NLS_CODEPAGE_1250 is not set
- # CONFIG_NLS_CODEPAGE_1251 is not set
- # CONFIG_NLS_ASCII is not set
--CONFIG_NLS_ISO8859_1=y
-+CONFIG_NLS_ISO8859_1=m
- # CONFIG_NLS_ISO8859_2 is not set
- # CONFIG_NLS_ISO8859_3 is not set
- # CONFIG_NLS_ISO8859_4 is not set
-@@ -921,18 +1046,19 @@
- # CONFIG_NLS_ISO8859_15 is not set
- # CONFIG_NLS_KOI8_R is not set
+ CONFIG_NETWORK_FILESYSTEMS=y
+@@ -1028,11 +1098,6 @@
# CONFIG_NLS_KOI8_U is not set
--CONFIG_NLS_UTF8=y
--
--#
--# Distributed Lock Manager
--#
-+CONFIG_NLS_UTF8=m
+ CONFIG_NLS_UTF8=m
# CONFIG_DLM is not set
-+CONFIG_INSTRUMENTATION=y
-+CONFIG_PROFILING=y
-+CONFIG_OPROFILE=m
-+CONFIG_KPROBES=y
-+# CONFIG_MARKERS is not set
+-CONFIG_INSTRUMENTATION=y
+-CONFIG_PROFILING=y
+-CONFIG_OPROFILE=m
+-CONFIG_KPROBES=y
+-# CONFIG_MARKERS is not set
#
# Kernel hacking
- #
--CONFIG_TRACE_IRQFLAGS_SUPPORT=y
- # CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
- CONFIG_ENABLE_MUST_CHECK=y
- CONFIG_MAGIC_SYSRQ=y
- # CONFIG_UNUSED_SYMBOLS is not set
-@@ -941,12 +1067,17 @@
- CONFIG_DEBUG_KERNEL=y
- # CONFIG_DEBUG_SHIRQ is not set
- CONFIG_DETECT_SOFTLOCKUP=y
-+CONFIG_SCHED_DEBUG=y
+@@ -1051,6 +1116,7 @@
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
+ # CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
- # CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
- # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
- # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
- # CONFIG_DEBUG_KOBJECT is not set
-@@ -954,21 +1085,21 @@
- # CONFIG_DEBUG_INFO is not set
- # CONFIG_DEBUG_VM is not set
+@@ -1067,9 +1133,10 @@
# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
+ # CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
- # CONFIG_FORCED_INLINING is not set
-+# CONFIG_BOOT_PRINTK_DELAY is not set
+-CONFIG_FORCED_INLINING=y
+ # CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_LKDTM is not set
++# CONFIG_KPROBES_SANITY_TEST is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
+ # CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
--# CONFIG_KPROBES is not set
-+# CONFIG_SAMPLES is not set
-
- #
- # Security options
- #
- # CONFIG_KEYS is not set
- # CONFIG_SECURITY is not set
--
--#
--# Cryptographic options
--#
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+ # CONFIG_SAMPLES is not set
+@@ -1082,7 +1149,9 @@
+ # CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y
- CONFIG_CRYPTO_ALGAPI=y
- CONFIG_CRYPTO_BLKCIPHER=y
-@@ -989,6 +1120,7 @@
- CONFIG_CRYPTO_CBC=y
- CONFIG_CRYPTO_PCBC=m
+ CONFIG_CRYPTO_ALGAPI=m
++CONFIG_CRYPTO_AEAD=m
+ CONFIG_CRYPTO_BLKCIPHER=m
++# CONFIG_CRYPTO_SEQIV is not set
+ CONFIG_CRYPTO_HASH=m
+ CONFIG_CRYPTO_MANAGER=m
+ CONFIG_CRYPTO_HMAC=m
+@@ -1101,6 +1170,9 @@
+ # CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_XTS is not set
+ # CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_CRYPTD is not set
- CONFIG_CRYPTO_DES=y
+ CONFIG_CRYPTO_DES=m
# CONFIG_CRYPTO_FCRYPT is not set
-@@ -1002,15 +1134,14 @@
- CONFIG_CRYPTO_ARC4=m
+@@ -1115,12 +1187,14 @@
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_SEED is not set
- CONFIG_CRYPTO_DEFLATE=y
+ # CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SALSA20 is not set
+ CONFIG_CRYPTO_DEFLATE=m
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
--
--#
--# Hardware crypto devices
--#
-+# CONFIG_CRYPTO_AUTHENC is not set
-+CONFIG_CRYPTO_HW=y
+-# CONFIG_CRYPTO_AUTHENC is not set
++CONFIG_CRYPTO_AUTHENC=m
++# CONFIG_CRYPTO_LZO is not set
+ # CONFIG_CRYPTO_HW is not set
#
- # Library routines
-@@ -1018,8 +1149,9 @@
- CONFIG_BITREVERSE=y
- CONFIG_CRC_CCITT=m
- # CONFIG_CRC16 is not set
--# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC_ITU_T=m
- CONFIG_CRC32=y
-+CONFIG_CRC7=m
+@@ -1135,6 +1209,7 @@
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
---- a/arch/avr32/configs/atstk1002_defconfig
-+++ b/arch/avr32/configs/atstk1002_defconfig
-@@ -1,48 +1,49 @@
++CONFIG_GENERIC_ALLOCATOR=y
+ CONFIG_PLIST=y
+ CONFIG_HAS_IOMEM=y
+ CONFIG_HAS_IOPORT=y
+--- a/arch/avr32/configs/atstk1003_defconfig
++++ b/arch/avr32/configs/atstk1003_defconfig
+@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
--# Linux kernel version: 2.6.22-rc5
--# Sat Jun 23 15:32:08 2007
-+# Linux kernel version: 2.6.24
-+# Thu Mar 6 12:49:17 2008
+-# Linux kernel version: 2.6.24-rc7
+-# Wed Jan 9 22:54:34 2008
++# Linux kernel version: 2.6.25.4
++# Wed Jun 11 15:33:36 2008
#
CONFIG_AVR32=y
CONFIG_GENERIC_GPIO=y
- CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
- CONFIG_HARDIRQS_SW_RESEND=y
+@@ -13,10 +13,10 @@
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+ # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+-CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_BUG=y
- CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
- #
--# Code maturity level options
-+# General setup
- #
- CONFIG_EXPERIMENTAL=y
- CONFIG_BROKEN_ON_SMP=y
- CONFIG_INIT_ENV_ARG_LIMIT=32
--
--#
--# General setup
--#
- CONFIG_LOCALVERSION=""
- # CONFIG_LOCALVERSION_AUTO is not set
- CONFIG_SWAP=y
- CONFIG_SYSVIPC=y
--# CONFIG_IPC_NS is not set
- CONFIG_SYSVIPC_SYSCTL=y
- CONFIG_POSIX_MQUEUE=y
--CONFIG_BSD_PROCESS_ACCT=y
--CONFIG_BSD_PROCESS_ACCT_V3=y
--CONFIG_TASKSTATS=y
--CONFIG_TASK_DELAY_ACCT=y
--# CONFIG_TASK_XACCT is not set
--# CONFIG_UTS_NS is not set
--CONFIG_AUDIT=y
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_USER_NS is not set
-+# CONFIG_PID_NS is not set
-+# CONFIG_AUDIT is not set
+@@ -39,17 +39,15 @@
+ CONFIG_TASKSTATS=y
+ CONFIG_TASK_DELAY_ACCT=y
+ # CONFIG_TASK_XACCT is not set
+-# CONFIG_USER_NS is not set
+-# CONFIG_PID_NS is not set
+ CONFIG_AUDIT=y
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_FAIR_GROUP_SCHED is not set
+ # CONFIG_CGROUPS is not set
+-CONFIG_FAIR_GROUP_SCHED=y
+-CONFIG_FAIR_USER_SCHED=y
+-# CONFIG_FAIR_CGROUP_SCHED is not set
++# CONFIG_GROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_RELAY=y
++# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
-@@ -63,35 +64,28 @@
+ CONFIG_INITRAMFS_SOURCE=""
+ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+@@ -63,11 +61,13 @@
+ CONFIG_PRINTK=y
+ CONFIG_BUG=y
+ CONFIG_ELF_CORE=y
++# CONFIG_COMPAT_BRK is not set
+ # CONFIG_BASE_FULL is not set
+ CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
--CONFIG_TIMERFD=y
++CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
--# CONFIG_SLUB_DEBUG is not set
-+CONFIG_SLUB_DEBUG=y
+@@ -75,6 +75,14 @@
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
-+CONFIG_SLABINFO=y
++CONFIG_PROFILING=y
++# CONFIG_MARKERS is not set
++CONFIG_OPROFILE=m
++CONFIG_HAVE_OPROFILE=y
++CONFIG_KPROBES=y
++CONFIG_HAVE_KPROBES=y
++# CONFIG_HAVE_KRETPROBES is not set
++CONFIG_PROC_PAGE_MONITOR=y
+ CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
- CONFIG_BASE_SMALL=1
--
--#
--# Loadable module support
--#
- CONFIG_MODULES=y
- CONFIG_MODULE_UNLOAD=y
- # CONFIG_MODULE_FORCE_UNLOAD is not set
- # CONFIG_MODVERSIONS is not set
- # CONFIG_MODULE_SRCVERSION_ALL is not set
- # CONFIG_KMOD is not set
--
--#
--# Block layer
--#
- CONFIG_BLOCK=y
- # CONFIG_LBD is not set
- # CONFIG_BLK_DEV_IO_TRACE is not set
- # CONFIG_LSF is not set
-+# CONFIG_BLK_DEV_BSG is not set
-
- #
- # IO Schedulers
-@@ -99,32 +93,49 @@
- CONFIG_IOSCHED_NOOP=y
- # CONFIG_IOSCHED_AS is not set
- # CONFIG_IOSCHED_DEADLINE is not set
--# CONFIG_IOSCHED_CFQ is not set
-+CONFIG_IOSCHED_CFQ=y
- # CONFIG_DEFAULT_AS is not set
- # CONFIG_DEFAULT_DEADLINE is not set
--# CONFIG_DEFAULT_CFQ is not set
--CONFIG_DEFAULT_NOOP=y
--CONFIG_DEFAULT_IOSCHED="noop"
-+CONFIG_DEFAULT_CFQ=y
-+# CONFIG_DEFAULT_NOOP is not set
-+CONFIG_DEFAULT_IOSCHED="cfq"
+@@ -103,10 +111,15 @@
+ CONFIG_DEFAULT_CFQ=y
+ # CONFIG_DEFAULT_NOOP is not set
+ CONFIG_DEFAULT_IOSCHED="cfq"
++CONFIG_CLASSIC_RCU=y
#
# System Type and features
CONFIG_SUBARCH_AVR32B=y
CONFIG_MMU=y
CONFIG_PERFORMANCE_COUNTERS=y
- CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP700X=y
- CONFIG_CPU_AT32AP7000=y
--CONFIG_BOARD_ATSTK1002=y
- CONFIG_BOARD_ATSTK1000=y
- # CONFIG_BOARD_ATNGW100 is not set
-+CONFIG_BOARD_ATSTK1002=y
-+# CONFIG_BOARD_ATSTK1003 is not set
-+# CONFIG_BOARD_ATSTK1004 is not set
-+# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
-+# CONFIG_BOARD_ATSTK100X_SPI1 is not set
-+# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+# CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
-+# CONFIG_BOARD_ATSTK1000_J2_RGB is not set
-+CONFIG_BOARD_ATSTK1000_EXTDAC=y
+@@ -118,12 +131,16 @@
+ # CONFIG_BOARD_ATSTK1002 is not set
+ CONFIG_BOARD_ATSTK1003=y
+ # CONFIG_BOARD_ATSTK1004 is not set
++# CONFIG_BOARD_ATSTK1006 is not set
+ # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
+ # CONFIG_BOARD_ATSTK100X_SPI1 is not set
+ # CONFIG_BOARD_ATSTK1000_J2_LED is not set
+ # CONFIG_BOARD_ATSTK1000_J2_LED8 is not set
+ # CONFIG_BOARD_ATSTK1000_J2_RGB is not set
+ CONFIG_BOARD_ATSTK1000_EXTDAC=y
+# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
+# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
+# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
CONFIG_LOADER_U_BOOT=y
#
- # Atmel AVR32 AP options
- #
--# CONFIG_AP7000_32_BIT_SMC is not set
--CONFIG_AP7000_16_BIT_SMC=y
--# CONFIG_AP7000_8_BIT_SMC is not set
-+# CONFIG_AP700X_32_BIT_SMC is not set
-+CONFIG_AP700X_16_BIT_SMC=y
-+# CONFIG_AP700X_8_BIT_SMC is not set
+@@ -132,6 +149,7 @@
+ # CONFIG_AP700X_32_BIT_SMC is not set
+ CONFIG_AP700X_16_BIT_SMC=y
+ # CONFIG_AP700X_8_BIT_SMC is not set
+CONFIG_GPIO_DEV=y
CONFIG_LOAD_ADDRESS=0x10000000
CONFIG_ENTRY_ADDRESS=0x90000000
CONFIG_PHYS_OFFSET=0x10000000
-@@ -144,10 +155,14 @@
- CONFIG_FLATMEM=y
- CONFIG_FLAT_NODE_MEM_MAP=y
- # CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
- CONFIG_SPLIT_PTLOCK_CPUS=4
- # CONFIG_RESOURCES_64BIT is not set
+@@ -157,16 +175,26 @@
CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_VIRT_TO_BUS=y
+ CONFIG_VIRT_TO_BUS=y
# CONFIG_OWNERSHIP_TRACE is not set
+CONFIG_NMI_DEBUGGING=y
+CONFIG_DW_DMAC=y
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
-@@ -156,13 +171,31 @@
+ # CONFIG_HZ_1000 is not set
+ CONFIG_HZ=250
++# CONFIG_SCHED_HRTICK is not set
CONFIG_CMDLINE=""
#
--# Bus options
-+# Power management options
- #
--# CONFIG_ARCH_SUPPORTS_MSI is not set
-
- #
--# PCCARD (PCMCIA/CardBus) support
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
-+
-+#
-+# Bus options
+ # Power management options
#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
- # CONFIG_PCCARD is not set
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
#
-@@ -182,7 +215,12 @@
- CONFIG_PACKET=y
- CONFIG_PACKET_MMAP=y
- CONFIG_UNIX=y
--# CONFIG_NET_KEY is not set
-+CONFIG_XFRM=y
-+CONFIG_XFRM_USER=m
-+# CONFIG_XFRM_SUB_POLICY is not set
-+# CONFIG_XFRM_MIGRATE is not set
-+CONFIG_NET_KEY=m
-+# CONFIG_NET_KEY_MIGRATE is not set
- CONFIG_INET=y
- # CONFIG_IP_MULTICAST is not set
- # CONFIG_IP_ADVANCED_ROUTER is not set
-@@ -191,36 +229,52 @@
- CONFIG_IP_PNP_DHCP=y
- # CONFIG_IP_PNP_BOOTP is not set
- # CONFIG_IP_PNP_RARP is not set
--# CONFIG_NET_IPIP is not set
--# CONFIG_NET_IPGRE is not set
-+CONFIG_NET_IPIP=m
-+CONFIG_NET_IPGRE=m
- # CONFIG_ARPD is not set
- # CONFIG_SYN_COOKIES is not set
--# CONFIG_INET_AH is not set
--# CONFIG_INET_ESP is not set
-+CONFIG_INET_AH=m
-+CONFIG_INET_ESP=m
- # CONFIG_INET_IPCOMP is not set
- # CONFIG_INET_XFRM_TUNNEL is not set
--# CONFIG_INET_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
--# CONFIG_INET_XFRM_MODE_TUNNEL is not set
--# CONFIG_INET_XFRM_MODE_BEET is not set
-+CONFIG_INET_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET_XFRM_MODE_TUNNEL=m
-+CONFIG_INET_XFRM_MODE_BEET=m
-+# CONFIG_INET_LRO is not set
- CONFIG_INET_DIAG=y
- CONFIG_INET_TCP_DIAG=y
- # CONFIG_TCP_CONG_ADVANCED is not set
- CONFIG_TCP_CONG_CUBIC=y
- CONFIG_DEFAULT_TCP_CONG="cubic"
- # CONFIG_TCP_MD5SIG is not set
--# CONFIG_IPV6 is not set
--# CONFIG_INET6_XFRM_TUNNEL is not set
--# CONFIG_INET6_TUNNEL is not set
-+CONFIG_IPV6=m
-+# CONFIG_IPV6_PRIVACY is not set
-+# CONFIG_IPV6_ROUTER_PREF is not set
-+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-+CONFIG_INET6_AH=m
-+CONFIG_INET6_ESP=m
-+CONFIG_INET6_IPCOMP=m
-+# CONFIG_IPV6_MIP6 is not set
-+CONFIG_INET6_XFRM_TUNNEL=m
-+CONFIG_INET6_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-+CONFIG_INET6_XFRM_MODE_TUNNEL=m
-+CONFIG_INET6_XFRM_MODE_BEET=m
-+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-+CONFIG_IPV6_SIT=m
-+CONFIG_IPV6_TUNNEL=m
-+# CONFIG_IPV6_MULTIPLE_TABLES is not set
- # CONFIG_NETWORK_SECMARK is not set
- # CONFIG_NETFILTER is not set
- # CONFIG_IP_DCCP is not set
- # CONFIG_IP_SCTP is not set
- # CONFIG_TIPC is not set
- # CONFIG_ATM is not set
--# CONFIG_BRIDGE is not set
-+CONFIG_BRIDGE=m
- # CONFIG_VLAN_8021Q is not set
- # CONFIG_DECNET is not set
-+CONFIG_LLC=m
- # CONFIG_LLC2 is not set
- # CONFIG_IPX is not set
- # CONFIG_ATALK is not set
-@@ -228,16 +282,13 @@
- # CONFIG_LAPB is not set
- # CONFIG_ECONET is not set
- # CONFIG_WAN_ROUTER is not set
--
--#
--# QoS and/or fair queueing
--#
- # CONFIG_NET_SCHED is not set
-
- #
- # Network testing
- #
+ # CPU Frequency scaling
+@@ -175,9 +203,9 @@
+ CONFIG_CPU_FREQ_TABLE=y
+ # CONFIG_CPU_FREQ_DEBUG is not set
+ # CONFIG_CPU_FREQ_STAT is not set
+-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+ # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+ # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+ # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+@@ -260,6 +288,7 @@
# CONFIG_NET_PKTGEN is not set
-+# CONFIG_NET_TCPPROBE is not set
+ # CONFIG_NET_TCPPROBE is not set
# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
-@@ -251,6 +302,7 @@
- # CONFIG_MAC80211 is not set
- # CONFIG_IEEE80211 is not set
- # CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
-
- #
- # Device Drivers
-@@ -259,16 +311,13 @@
- #
- # Generic Driver Options
- #
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
- CONFIG_STANDALONE=y
- # CONFIG_PREVENT_FIRMWARE_BUILD is not set
- # CONFIG_FW_LOADER is not set
- # CONFIG_DEBUG_DRIVER is not set
- # CONFIG_DEBUG_DEVRES is not set
- # CONFIG_SYS_HYPERVISOR is not set
--
--#
--# Connector - unified userspace <-> kernelspace linker
--#
- # CONFIG_CONNECTOR is not set
- CONFIG_MTD=y
- # CONFIG_MTD_DEBUG is not set
-@@ -288,6 +337,7 @@
- # CONFIG_INFTL is not set
- # CONFIG_RFD_FTL is not set
- # CONFIG_SSFDC is not set
-+# CONFIG_MTD_OOPS is not set
-
- #
- # RAM/ROM/Flash chip drivers
-@@ -327,6 +377,8 @@
- #
- # Self-contained MTD device drivers
- #
-+CONFIG_MTD_DATAFLASH=m
-+CONFIG_MTD_M25P80=m
- # CONFIG_MTD_SLRAM is not set
- # CONFIG_MTD_PHRAM is not set
- # CONFIG_MTD_MTDRAM is not set
-@@ -345,20 +397,8 @@
- # UBI - Unsorted block images
- #
- # CONFIG_MTD_UBI is not set
--
--#
--# Parallel port support
--#
- # CONFIG_PARPORT is not set
--
--#
--# Plug and Play support
--#
--# CONFIG_PNPACPI is not set
--
--#
--# Block devices
--#
-+CONFIG_BLK_DEV=y
- # CONFIG_BLK_DEV_COW_COMMON is not set
- CONFIG_BLK_DEV_LOOP=m
- # CONFIG_BLK_DEV_CRYPTOLOOP is not set
-@@ -369,42 +409,91 @@
- CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+ # CONFIG_AF_RXRPC is not set
+@@ -376,13 +405,18 @@
+ CONFIG_BLK_DEV_RAM=m
+ CONFIG_BLK_DEV_RAM_COUNT=16
+ CONFIG_BLK_DEV_RAM_SIZE=4096
+-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
--
--#
--# Misc devices
--#
--# CONFIG_BLINK is not set
-+CONFIG_MISC_DEVICES=y
+ CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_PWM=m
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+CONFIG_ATMEL_SSC=m
- # CONFIG_IDE is not set
+ # CONFIG_EEPROM_93CX6 is not set
+ CONFIG_ATMEL_SSC=m
+-# CONFIG_IDE is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HAVE_IDE is not set
#
# SCSI device support
- #
- # CONFIG_RAID_ATTRS is not set
--# CONFIG_SCSI is not set
-+CONFIG_SCSI=m
-+CONFIG_SCSI_DMA=y
-+# CONFIG_SCSI_TGT is not set
- # CONFIG_SCSI_NETLINK is not set
--# CONFIG_ATA is not set
-+# CONFIG_SCSI_PROC_FS is not set
-
- #
--# Multi-device support (RAID and LVM)
-+# SCSI support type (disk, tape, CD-ROM)
- #
--# CONFIG_MD is not set
-+CONFIG_BLK_DEV_SD=m
-+# CONFIG_CHR_DEV_ST is not set
-+# CONFIG_CHR_DEV_OSST is not set
-+CONFIG_BLK_DEV_SR=m
-+# CONFIG_BLK_DEV_SR_VENDOR is not set
-+# CONFIG_CHR_DEV_SG is not set
-+# CONFIG_CHR_DEV_SCH is not set
-+
-+#
-+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-+#
-+# CONFIG_SCSI_MULTI_LUN is not set
-+# CONFIG_SCSI_CONSTANTS is not set
-+# CONFIG_SCSI_LOGGING is not set
-+# CONFIG_SCSI_SCAN_ASYNC is not set
-+CONFIG_SCSI_WAIT_SCAN=m
-
- #
--# Network device support
-+# SCSI Transports
- #
-+# CONFIG_SCSI_SPI_ATTRS is not set
-+# CONFIG_SCSI_FC_ATTRS is not set
-+# CONFIG_SCSI_ISCSI_ATTRS is not set
-+# CONFIG_SCSI_SAS_LIBSAS is not set
-+# CONFIG_SCSI_SRP_ATTRS is not set
-+# CONFIG_SCSI_LOWLEVEL is not set
-+CONFIG_ATA=m
-+# CONFIG_ATA_NONSTANDARD is not set
-+CONFIG_PATA_AT32=m
-+# CONFIG_PATA_PLATFORM is not set
-+# CONFIG_MD is not set
- CONFIG_NETDEVICES=y
--CONFIG_DUMMY=y
-+# CONFIG_NETDEVICES_MULTIQUEUE is not set
-+# CONFIG_DUMMY is not set
- # CONFIG_BONDING is not set
-+# CONFIG_MACVLAN is not set
- # CONFIG_EQUALIZER is not set
- CONFIG_TUN=m
--# CONFIG_PHYLIB is not set
-+# CONFIG_VETH is not set
-+CONFIG_PHYLIB=y
-
- #
--# Ethernet (10 or 100Mbit)
-+# MII PHY device drivers
- #
-+# CONFIG_MARVELL_PHY is not set
-+# CONFIG_DAVICOM_PHY is not set
-+# CONFIG_QSEMI_PHY is not set
-+# CONFIG_LXT_PHY is not set
-+# CONFIG_CICADA_PHY is not set
-+# CONFIG_VITESSE_PHY is not set
-+# CONFIG_SMSC_PHY is not set
-+# CONFIG_BROADCOM_PHY is not set
-+# CONFIG_ICPLUS_PHY is not set
-+# CONFIG_FIXED_PHY is not set
-+# CONFIG_MDIO_BITBANG is not set
- CONFIG_NET_ETHERNET=y
--CONFIG_MII=y
-+# CONFIG_MII is not set
- CONFIG_MACB=y
-+# CONFIG_IBM_NEW_EMAC_ZMII is not set
-+# CONFIG_IBM_NEW_EMAC_RGMII is not set
-+# CONFIG_IBM_NEW_EMAC_TAH is not set
-+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-+# CONFIG_B44 is not set
- # CONFIG_NETDEV_1000 is not set
- # CONFIG_NETDEV_10000 is not set
-
-@@ -423,27 +512,54 @@
- CONFIG_PPP_BSDCOMP=m
- # CONFIG_PPP_MPPE is not set
- # CONFIG_PPPOE is not set
-+# CONFIG_PPPOL2TP is not set
+@@ -427,6 +461,7 @@
+ # CONFIG_SCSI_DEBUG is not set
+ CONFIG_ATA=m
+ # CONFIG_ATA_NONSTANDARD is not set
++# CONFIG_SATA_MV is not set
+ CONFIG_PATA_AT32=m
+ # CONFIG_PATA_PLATFORM is not set
+ # CONFIG_MD is not set
+@@ -460,7 +495,6 @@
+ # CONFIG_PPPOL2TP is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m
- # CONFIG_SHAPER is not set
+-# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
--
--#
--# ISDN subsystem
--#
- # CONFIG_ISDN is not set
--
--#
--# Telephony Support
--#
- # CONFIG_PHONE is not set
-
- #
- # Input device support
- #
--# CONFIG_INPUT is not set
-+CONFIG_INPUT=m
-+# CONFIG_INPUT_FF_MEMLESS is not set
-+CONFIG_INPUT_POLLDEV=m
-+
-+#
-+# Userland interfaces
-+#
-+CONFIG_INPUT_MOUSEDEV=m
-+CONFIG_INPUT_MOUSEDEV_PSAUX=y
-+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-+# CONFIG_INPUT_JOYDEV is not set
-+CONFIG_INPUT_EVDEV=m
-+# CONFIG_INPUT_EVBUG is not set
-+
-+#
-+# Input Device Drivers
-+#
-+CONFIG_INPUT_KEYBOARD=y
-+# CONFIG_KEYBOARD_ATKBD is not set
-+# CONFIG_KEYBOARD_SUNKBD is not set
-+# CONFIG_KEYBOARD_LKKBD is not set
-+# CONFIG_KEYBOARD_XTKBD is not set
-+# CONFIG_KEYBOARD_NEWTON is not set
-+# CONFIG_KEYBOARD_STOWAWAY is not set
-+CONFIG_KEYBOARD_GPIO=m
-+CONFIG_INPUT_MOUSE=y
-+# CONFIG_MOUSE_PS2 is not set
-+# CONFIG_MOUSE_SERIAL is not set
-+# CONFIG_MOUSE_VSXXXAA is not set
-+CONFIG_MOUSE_GPIO=m
-+# CONFIG_INPUT_JOYSTICK is not set
-+# CONFIG_INPUT_TABLET is not set
-+# CONFIG_INPUT_TOUCHSCREEN is not set
-+# CONFIG_INPUT_MISC is not set
-
- #
- # Hardware I/O ports
-@@ -467,40 +583,94 @@
+@@ -528,6 +562,7 @@
#
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
# CONFIG_SERIAL_ATMEL_TTYAT is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
- CONFIG_UNIX98_PTYS=y
+@@ -535,8 +570,6 @@
# CONFIG_LEGACY_PTYS is not set
--
--#
--# IPMI
--#
# CONFIG_IPMI_HANDLER is not set
--# CONFIG_WATCHDOG is not set
# CONFIG_HW_RANDOM is not set
- # CONFIG_RTC is not set
- # CONFIG_GEN_RTC is not set
+-# CONFIG_RTC is not set
+-# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
-+# CONFIG_TCG_TPM is not set
-+CONFIG_I2C=m
-+CONFIG_I2C_BOARDINFO=y
-+CONFIG_I2C_CHARDEV=m
+ # CONFIG_TCG_TPM is not set
+@@ -554,6 +587,7 @@
+ #
+ # I2C Hardware Bus support
+ #
++CONFIG_I2C_ATMELTWI=m
+ CONFIG_I2C_GPIO=m
+ # CONFIG_I2C_OCORES is not set
+ # CONFIG_I2C_PARPORT_LIGHT is not set
+@@ -564,13 +598,12 @@
+ #
+ # Miscellaneous I2C Chip support
+ #
+-# CONFIG_SENSORS_DS1337 is not set
+-# CONFIG_SENSORS_DS1374 is not set
+ # CONFIG_DS1682 is not set
+ # CONFIG_SENSORS_EEPROM is not set
+ # CONFIG_SENSORS_PCF8574 is not set
+-# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_PCF8575 is not set
+ # CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_TPS65010 is not set
+ # CONFIG_SENSORS_MAX6875 is not set
+ # CONFIG_SENSORS_TSL2550 is not set
+ # CONFIG_I2C_DEBUG_CORE is not set
+@@ -597,9 +630,27 @@
+ # CONFIG_SPI_AT25 is not set
+ CONFIG_SPI_SPIDEV=m
+ # CONFIG_SPI_TLE62X0 is not set
++CONFIG_HAVE_GPIO_LIB=y
+
+#
-+# I2C Algorithms
++# GPIO Support
+#
-+CONFIG_I2C_ALGOBIT=m
-+# CONFIG_I2C_ALGOPCF is not set
-+# CONFIG_I2C_ALGOPCA is not set
++# CONFIG_DEBUG_GPIO is not set
+
+#
-+# I2C Hardware Bus support
++# I2C GPIO expanders:
+#
-+CONFIG_I2C_ATMELTWI=m
-+CONFIG_I2C_GPIO=m
-+# CONFIG_I2C_OCORES is not set
-+# CONFIG_I2C_PARPORT_LIGHT is not set
-+# CONFIG_I2C_SIMTEC is not set
-+# CONFIG_I2C_TAOS_EVM is not set
-+# CONFIG_I2C_STUB is not set
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
+
+#
-+# Miscellaneous I2C Chip support
++# SPI GPIO expanders:
+#
-+# CONFIG_SENSORS_DS1337 is not set
-+# CONFIG_SENSORS_DS1374 is not set
-+# CONFIG_DS1682 is not set
-+# CONFIG_SENSORS_EEPROM is not set
-+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
-+# CONFIG_SENSORS_PCF8591 is not set
-+# CONFIG_SENSORS_MAX6875 is not set
-+# CONFIG_SENSORS_TSL2550 is not set
-+# CONFIG_I2C_DEBUG_CORE is not set
-+# CONFIG_I2C_DEBUG_ALGO is not set
-+# CONFIG_I2C_DEBUG_BUS is not set
-+# CONFIG_I2C_DEBUG_CHIP is not set
++# CONFIG_GPIO_MCP23S08 is not set
+ # CONFIG_W1 is not set
+ # CONFIG_POWER_SUPPLY is not set
+ # CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
+ CONFIG_WATCHDOG=y
+ # CONFIG_WATCHDOG_NOWAYOUT is not set
+@@ -665,12 +716,18 @@
#
--# TPM devices
-+# SPI support
+ # Generic devices
#
--# CONFIG_TCG_TPM is not set
--# CONFIG_I2C is not set
-+CONFIG_SPI=y
-+# CONFIG_SPI_DEBUG is not set
-+CONFIG_SPI_MASTER=y
++CONFIG_SND_AC97_CODEC=m
+ # CONFIG_SND_DUMMY is not set
+ # CONFIG_SND_MTPAV is not set
+ # CONFIG_SND_SERIAL_U16550 is not set
+ # CONFIG_SND_MPU401 is not set
#
--# SPI support
-+# SPI Master Controller Drivers
++# AVR32 devices
++#
++CONFIG_SND_ATMEL_AC97=m
++
++#
+ # SPI devices
+ #
+ CONFIG_SND_AT73C213=m
+@@ -686,9 +743,14 @@
#
--# CONFIG_SPI is not set
--# CONFIG_SPI_MASTER is not set
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
#
--# Dallas's 1-wire bus
-+# SPI Protocol Masters
++# ALSA SoC audio for Freescale SOCs
++#
++
++#
+ # Open Sound System
#
-+# CONFIG_SPI_AT25 is not set
-+CONFIG_SPI_SPIDEV=m
-+# CONFIG_SPI_TLE62X0 is not set
- # CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
- # CONFIG_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
-+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32AP700X_WDT=y
-+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
-
- #
- # Multifunction device drivers
-@@ -517,23 +687,104 @@
- #
- # Graphics support
- #
--# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+CONFIG_FB_DEFERRED_IO=y
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
-+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_VIRTUAL is not set
-+CONFIG_BACKLIGHT_LCD_SUPPORT=y
-+CONFIG_LCD_CLASS_DEVICE=y
-+CONFIG_LCD_LTV350QV=y
-+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
-
- #
- # Display device support
- #
- # CONFIG_DISPLAY_SUPPORT is not set
--# CONFIG_VGASTATE is not set
--# CONFIG_FB is not set
-+# CONFIG_LOGO is not set
-
- #
- # Sound
- #
--# CONFIG_SOUND is not set
-+CONFIG_SOUND=m
-+
-+#
-+# Advanced Linux Sound Architecture
-+#
-+CONFIG_SND=m
-+CONFIG_SND_TIMER=m
-+CONFIG_SND_PCM=m
-+# CONFIG_SND_SEQUENCER is not set
-+CONFIG_SND_OSSEMUL=y
-+CONFIG_SND_MIXER_OSS=m
-+CONFIG_SND_PCM_OSS=m
-+CONFIG_SND_PCM_OSS_PLUGINS=y
-+# CONFIG_SND_DYNAMIC_MINORS is not set
-+# CONFIG_SND_SUPPORT_OLD_API is not set
-+# CONFIG_SND_VERBOSE_PROCFS is not set
-+# CONFIG_SND_VERBOSE_PRINTK is not set
-+# CONFIG_SND_DEBUG is not set
-+
-+#
-+# Generic devices
-+#
-+CONFIG_SND_AC97_CODEC=m
-+# CONFIG_SND_DUMMY is not set
-+# CONFIG_SND_MTPAV is not set
-+# CONFIG_SND_SERIAL_U16550 is not set
-+# CONFIG_SND_MPU401 is not set
-+
-+#
-+# AVR32 devices
-+#
-+CONFIG_SND_ATMEL_AC97=m
-
- #
--# USB support
-+# SPI devices
- #
-+CONFIG_SND_AT73C213=m
-+CONFIG_SND_AT73C213_TARGET_BITRATE=48000
-+
-+#
-+# System on Chip audio support
-+#
-+# CONFIG_SND_SOC is not set
-+
-+#
-+# SoC Audio support for SuperH
-+#
-+
-+#
-+# Open Sound System
-+#
-+CONFIG_SOUND_PRIME=m
-+# CONFIG_SOUND_MSNDCLAS is not set
-+# CONFIG_SOUND_MSNDPIN is not set
-+CONFIG_SOUND_AT32_ABDAC=m
+ # CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
-+# CONFIG_HID_SUPPORT is not set
-+CONFIG_USB_SUPPORT=y
+ # CONFIG_HID_SUPPORT is not set
+ CONFIG_USB_SUPPORT=y
# CONFIG_USB_ARCH_HAS_HCD is not set
- # CONFIG_USB_ARCH_HAS_OHCI is not set
- # CONFIG_USB_ARCH_HAS_EHCI is not set
-@@ -545,63 +796,137 @@
+@@ -698,10 +760,6 @@
#
- # USB Gadget Support
+ # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
--# CONFIG_USB_GADGET is not set
--# CONFIG_MMC is not set
-
-#
--# LED devices
+-# USB Gadget Support
-#
--# CONFIG_NEW_LEDS is not set
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG is not set
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+# CONFIG_USB_GADGET_DEBUG_FS is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA2XX is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+CONFIG_USB_ZERO=m
-+CONFIG_USB_ETH=m
-+CONFIG_USB_ETH_RNDIS=y
-+CONFIG_USB_GADGETFS=m
-+CONFIG_USB_FILE_STORAGE=m
-+# CONFIG_USB_FILE_STORAGE_TEST is not set
-+CONFIG_USB_G_SERIAL=m
-+# CONFIG_USB_MIDI_GADGET is not set
+ CONFIG_USB_GADGET=y
+ # CONFIG_USB_GADGET_DEBUG is not set
+ # CONFIG_USB_GADGET_DEBUG_FILES is not set
+@@ -729,27 +787,31 @@
+ # CONFIG_USB_FILE_STORAGE_TEST is not set
+ CONFIG_USB_G_SERIAL=m
+ # CONFIG_USB_MIDI_GADGET is not set
+-CONFIG_MMC=m
++# CONFIG_USB_G_PRINTER is not set
+CONFIG_MMC=y
-+# CONFIG_MMC_DEBUG is not set
-+# CONFIG_MMC_UNSAFE_RESUME is not set
-+
-+#
-+# MMC/SD Card Drivers
-+#
-+CONFIG_MMC_BLOCK=y
-+# CONFIG_MMC_BLOCK_BOUNCE is not set
-+# CONFIG_SDIO_UART is not set
-+
-+#
-+# MMC/SD Host Controller Drivers
-+#
-+CONFIG_MMC_ATMELMCI=y
-+CONFIG_MMC_SPI=m
-+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=m
+ # CONFIG_MMC_DEBUG is not set
+ # CONFIG_MMC_UNSAFE_RESUME is not set
#
- # LED drivers
+ # MMC/SD Card Drivers
#
-+CONFIG_LEDS_ATMEL_PWM=m
-+CONFIG_LEDS_GPIO=m
+-CONFIG_MMC_BLOCK=m
++CONFIG_MMC_BLOCK=y
+ # CONFIG_MMC_BLOCK_BOUNCE is not set
+ # CONFIG_SDIO_UART is not set
#
- # LED Triggers
+ # MMC/SD Host Controller Drivers
#
-+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=m
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
++CONFIG_MMC_ATMELMCI=y
+ CONFIG_MMC_SPI=m
++# CONFIG_MEMSTICK is not set
+ CONFIG_NEW_LEDS=y
+ CONFIG_LEDS_CLASS=y
#
--# InfiniBand support
-+# RTC interfaces
+ # LED drivers
#
-+CONFIG_RTC_INTF_SYSFS=y
-+CONFIG_RTC_INTF_PROC=y
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
++CONFIG_LEDS_ATMEL_PWM=m
+ CONFIG_LEDS_GPIO=y
#
--# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-+# I2C RTC drivers
- #
-+# CONFIG_RTC_DRV_DS1307 is not set
-+# CONFIG_RTC_DRV_DS1374 is not set
-+# CONFIG_RTC_DRV_DS1672 is not set
-+# CONFIG_RTC_DRV_MAX6900 is not set
-+# CONFIG_RTC_DRV_RS5C372 is not set
-+# CONFIG_RTC_DRV_ISL1208 is not set
-+# CONFIG_RTC_DRV_X1205 is not set
-+# CONFIG_RTC_DRV_PCF8563 is not set
-+# CONFIG_RTC_DRV_PCF8583 is not set
-+# CONFIG_RTC_DRV_M41T80 is not set
+@@ -786,19 +848,22 @@
+ # CONFIG_RTC_DRV_PCF8563 is not set
+ # CONFIG_RTC_DRV_PCF8583 is not set
+ # CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_S35390A is not set
#
--# Real Time Clock
-+# SPI RTC drivers
+ # SPI RTC drivers
#
--# CONFIG_RTC_CLASS is not set
+-# CONFIG_RTC_DRV_RS5C348 is not set
+ # CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
#
--# DMA Engine support
-+# Platform RTC drivers
+ # Platform RTC drivers
#
--# CONFIG_DMA_ENGINE is not set
-+# CONFIG_RTC_DRV_DS1553 is not set
++# CONFIG_RTC_DRV_DS1511 is not set
+ # CONFIG_RTC_DRV_DS1553 is not set
+-# CONFIG_RTC_DRV_STK17TA8 is not set
+ # CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
-
- #
--# DMA Clients
-+# on-CPU RTC drivers
- #
-+CONFIG_RTC_DRV_AT32AP700X=y
-
- #
--# DMA Devices
-+# Userspace I/O
- #
-+# CONFIG_UIO is not set
-
+ # CONFIG_RTC_DRV_M48T86 is not set
+ # CONFIG_RTC_DRV_M48T59 is not set
+ # CONFIG_RTC_DRV_V3020 is not set
+@@ -816,13 +881,13 @@
#
# File systems
#
+CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
--# CONFIG_EXT3_FS is not set
+-CONFIG_EXT3_FS=m
+CONFIG_EXT3_FS=y
-+# CONFIG_EXT3_FS_XATTR is not set
+ # CONFIG_EXT3_FS_XATTR is not set
# CONFIG_EXT4DEV_FS is not set
+-CONFIG_JBD=m
+CONFIG_JBD=y
-+# CONFIG_JBD_DEBUG is not set
+ # CONFIG_JBD_DEBUG is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
- # CONFIG_FS_POSIX_ACL is not set
+@@ -830,12 +895,10 @@
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
--CONFIG_MINIX_FS=m
-+# CONFIG_MINIX_FS is not set
- # CONFIG_ROMFS_FS is not set
+-# CONFIG_MINIX_FS is not set
+-# CONFIG_ROMFS_FS is not set
++# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
-@@ -609,7 +934,7 @@
- # CONFIG_DNOTIFY is not set
+ # CONFIG_QUOTA is not set
+-# CONFIG_DNOTIFY is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
--# CONFIG_FUSE_FS is not set
-+CONFIG_FUSE_FS=m
-
- #
- # CD-ROM/DVD Filesystems
-@@ -637,8 +962,7 @@
+ CONFIG_FUSE_FS=m
+@@ -866,7 +929,7 @@
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
--CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
+CONFIG_CONFIGFS_FS=y
#
# Miscellaneous filesystems
-@@ -652,11 +976,12 @@
- # CONFIG_EFS_FS is not set
- CONFIG_JFFS2_FS=y
- CONFIG_JFFS2_FS_DEBUG=0
--CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WRITEBUFFER is not set
- # CONFIG_JFFS2_SUMMARY is not set
- # CONFIG_JFFS2_FS_XATTR is not set
- # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
- CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
- CONFIG_JFFS2_RTIME=y
+@@ -891,8 +954,10 @@
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_CRAMFS is not set
-@@ -665,10 +990,7 @@
+ # CONFIG_VXFS_FS is not set
++# CONFIG_MINIX_FS is not set
+ # CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
--
--#
--# Network File Systems
--#
-+CONFIG_NETWORK_FILESYSTEMS=y
- CONFIG_NFS_FS=y
- CONFIG_NFS_V3=y
- # CONFIG_NFS_V3_ACL is not set
-@@ -688,17 +1010,12 @@
- # CONFIG_NCP_FS is not set
- # CONFIG_CODA_FS is not set
- # CONFIG_AFS_FS is not set
--# CONFIG_9P_FS is not set
-
- #
- # Partition Types
- #
- # CONFIG_PARTITION_ADVANCED is not set
- CONFIG_MSDOS_PARTITION=y
--
--#
--# Native Language Support
--#
- CONFIG_NLS=m
- CONFIG_NLS_DEFAULT="iso8859-1"
- CONFIG_NLS_CODEPAGE_437=m
-@@ -739,17 +1056,18 @@
- # CONFIG_NLS_KOI8_R is not set
+ # CONFIG_NETWORK_FILESYSTEMS is not set
+@@ -943,11 +1008,6 @@
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=m
--
--#
--# Distributed Lock Manager
--#
# CONFIG_DLM is not set
-+CONFIG_INSTRUMENTATION=y
-+CONFIG_PROFILING=y
-+CONFIG_OPROFILE=m
-+CONFIG_KPROBES=y
-+# CONFIG_MARKERS is not set
+-CONFIG_INSTRUMENTATION=y
+-CONFIG_PROFILING=y
+-CONFIG_OPROFILE=m
+-CONFIG_KPROBES=y
+-# CONFIG_MARKERS is not set
#
# Kernel hacking
- #
--CONFIG_TRACE_IRQFLAGS_SUPPORT=y
- # CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
- CONFIG_ENABLE_MUST_CHECK=y
- CONFIG_MAGIC_SYSRQ=y
- # CONFIG_UNUSED_SYMBOLS is not set
-@@ -758,12 +1076,17 @@
- CONFIG_DEBUG_KERNEL=y
- # CONFIG_DEBUG_SHIRQ is not set
- CONFIG_DETECT_SOFTLOCKUP=y
-+CONFIG_SCHED_DEBUG=y
+@@ -965,6 +1025,7 @@
+ CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
-+# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
- # CONFIG_DEBUG_MUTEXES is not set
-+# CONFIG_DEBUG_LOCK_ALLOC is not set
-+# CONFIG_PROVE_LOCKING is not set
-+# CONFIG_LOCK_STAT is not set
- # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
- # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
- # CONFIG_DEBUG_KOBJECT is not set
-@@ -771,22 +1094,63 @@
- # CONFIG_DEBUG_INFO is not set
- # CONFIG_DEBUG_VM is not set
+@@ -981,9 +1042,10 @@
# CONFIG_DEBUG_LIST is not set
-+# CONFIG_DEBUG_SG is not set
+ # CONFIG_DEBUG_SG is not set
CONFIG_FRAME_POINTER=y
- CONFIG_FORCED_INLINING=y
-+# CONFIG_BOOT_PRINTK_DELAY is not set
+-CONFIG_FORCED_INLINING=y
+ # CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
-+# CONFIG_LKDTM is not set
++# CONFIG_KPROBES_SANITY_TEST is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
+ # CONFIG_LKDTM is not set
# CONFIG_FAULT_INJECTION is not set
--# CONFIG_KPROBES is not set
-+# CONFIG_SAMPLES is not set
-
- #
- # Security options
- #
- # CONFIG_KEYS is not set
- # CONFIG_SECURITY is not set
+ # CONFIG_SAMPLES is not set
+@@ -1009,6 +1071,7 @@
+ CONFIG_AUDIT_GENERIC=y
+ CONFIG_ZLIB_INFLATE=y
+ CONFIG_ZLIB_DEFLATE=y
++CONFIG_GENERIC_ALLOCATOR=y
+ CONFIG_PLIST=y
+ CONFIG_HAS_IOMEM=y
+ CONFIG_HAS_IOPORT=y
+--- a/arch/avr32/configs/atstk1004_defconfig
++++ b/arch/avr32/configs/atstk1004_defconfig
+@@ -1,7 +1,7 @@
+ #
+ # Automatically generated make config: don't edit
+-# Linux kernel version: 2.6.24-rc7
+-# Wed Jan 9 23:04:20 2008
++# Linux kernel version: 2.6.25.4
++# Wed Jun 11 15:37:49 2008
+ #
+ CONFIG_AVR32=y
+ CONFIG_GENERIC_GPIO=y
+@@ -13,10 +13,10 @@
+ CONFIG_GENERIC_IRQ_PROBE=y
+ CONFIG_RWSEM_GENERIC_SPINLOCK=y
+ CONFIG_GENERIC_TIME=y
++CONFIG_GENERIC_CLOCKEVENTS=y
+ # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+ # CONFIG_ARCH_HAS_ILOG2_U32 is not set
+ # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+-CONFIG_ARCH_SUPPORTS_OPROFILE=y
+ CONFIG_GENERIC_HWEIGHT=y
+ CONFIG_GENERIC_CALIBRATE_DELAY=y
+ CONFIG_GENERIC_BUG=y
+@@ -34,15 +34,15 @@
+ # CONFIG_POSIX_MQUEUE is not set
+ # CONFIG_BSD_PROCESS_ACCT is not set
+ # CONFIG_TASKSTATS is not set
+-# CONFIG_USER_NS is not set
+-# CONFIG_PID_NS is not set
+ # CONFIG_AUDIT is not set
+ # CONFIG_IKCONFIG is not set
+ CONFIG_LOG_BUF_SHIFT=14
+ # CONFIG_CGROUPS is not set
+-# CONFIG_FAIR_GROUP_SCHED is not set
++# CONFIG_GROUP_SCHED is not set
+ CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
+ # CONFIG_RELAY is not set
++# CONFIG_NAMESPACES is not set
+ # CONFIG_BLK_DEV_INITRD is not set
+ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+ CONFIG_SYSCTL=y
+@@ -54,24 +54,37 @@
+ CONFIG_PRINTK=y
+ CONFIG_BUG=y
+ CONFIG_ELF_CORE=y
++# CONFIG_COMPAT_BRK is not set
+ # CONFIG_BASE_FULL is not set
+ # CONFIG_FUTEX is not set
+ # CONFIG_EPOLL is not set
+ # CONFIG_SIGNALFD is not set
++# CONFIG_TIMERFD is not set
+ # CONFIG_EVENTFD is not set
+ CONFIG_SHMEM=y
+ CONFIG_VM_EVENT_COUNTERS=y
+ # CONFIG_SLAB is not set
+ # CONFIG_SLUB is not set
+ CONFIG_SLOB=y
++# CONFIG_PROFILING is not set
++# CONFIG_MARKERS is not set
++CONFIG_HAVE_OPROFILE=y
++CONFIG_HAVE_KPROBES=y
++# CONFIG_HAVE_KRETPROBES is not set
++# CONFIG_PROC_PAGE_MONITOR is not set
+ # CONFIG_TINY_SHMEM is not set
+ CONFIG_BASE_SMALL=1
+ # CONFIG_MODULES is not set
+ # CONFIG_BLOCK is not set
++CONFIG_CLASSIC_RCU=y
+
+ #
+ # System Type and features
+ #
++# CONFIG_TICK_ONESHOT is not set
++# CONFIG_NO_HZ is not set
++# CONFIG_HIGH_RES_TIMERS is not set
++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+ CONFIG_SUBARCH_AVR32B=y
+ CONFIG_MMU=y
+ CONFIG_PERFORMANCE_COUNTERS=y
+@@ -83,10 +96,14 @@
+ # CONFIG_BOARD_ATSTK1002 is not set
+ # CONFIG_BOARD_ATSTK1003 is not set
+ CONFIG_BOARD_ATSTK1004=y
++# CONFIG_BOARD_ATSTK1006 is not set
+ # CONFIG_BOARD_ATSTK100X_CUSTOM is not set
+ # CONFIG_BOARD_ATSTK100X_SPI1 is not set
+ # CONFIG_BOARD_ATSTK1000_J2_LED is not set
+ CONFIG_BOARD_ATSTK1000_EXTDAC=y
++# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
++# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
++# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
+ CONFIG_LOADER_U_BOOT=y
+
+ #
+@@ -95,6 +112,7 @@
+ # CONFIG_AP700X_32_BIT_SMC is not set
+ CONFIG_AP700X_16_BIT_SMC=y
+ # CONFIG_AP700X_8_BIT_SMC is not set
++# CONFIG_GPIO_DEV is not set
+ CONFIG_LOAD_ADDRESS=0x10000000
+ CONFIG_ENTRY_ADDRESS=0x90000000
+ CONFIG_PHYS_OFFSET=0x10000000
+@@ -120,34 +138,26 @@
+ CONFIG_ZONE_DMA_FLAG=0
+ CONFIG_VIRT_TO_BUS=y
+ # CONFIG_OWNERSHIP_TRACE is not set
++# CONFIG_NMI_DEBUGGING is not set
++CONFIG_DW_DMAC=y
+ # CONFIG_HZ_100 is not set
+ CONFIG_HZ_250=y
+ # CONFIG_HZ_300 is not set
+ # CONFIG_HZ_1000 is not set
+ CONFIG_HZ=250
++# CONFIG_SCHED_HRTICK is not set
+ CONFIG_CMDLINE=""
+
+ #
+ # Power management options
+ #
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++# CONFIG_PM is not set
+
+ #
+ # CPU Frequency scaling
+ #
+-CONFIG_CPU_FREQ=y
+-CONFIG_CPU_FREQ_TABLE=y
+-# CONFIG_CPU_FREQ_DEBUG is not set
+-# CONFIG_CPU_FREQ_STAT is not set
+-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+-CONFIG_CPU_FREQ_GOV_USERSPACE=y
+-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+-CONFIG_CPU_FREQ_AT32AP=y
++# CONFIG_CPU_FREQ is not set
+
+ #
+ # Bus options
+@@ -222,6 +232,7 @@
+ #
+ # CONFIG_NET_PKTGEN is not set
+ # CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
+ # CONFIG_IRDA is not set
+ # CONFIG_BT is not set
+ # CONFIG_AF_RXRPC is not set
+@@ -321,6 +332,7 @@
+ # CONFIG_MTD_UBI is not set
+ # CONFIG_PARPORT is not set
+ # CONFIG_MISC_DEVICES is not set
++# CONFIG_HAVE_IDE is not set
+
+ #
+ # SCSI device support
+@@ -358,6 +370,7 @@
+ #
+ CONFIG_SERIAL_ATMEL=y
+ CONFIG_SERIAL_ATMEL_CONSOLE=y
++# CONFIG_SERIAL_ATMEL_PDC is not set
+ # CONFIG_SERIAL_ATMEL_TTYAT is not set
+ CONFIG_SERIAL_CORE=y
+ CONFIG_SERIAL_CORE_CONSOLE=y
+@@ -365,8 +378,6 @@
+ # CONFIG_LEGACY_PTYS is not set
+ # CONFIG_IPMI_HANDLER is not set
+ # CONFIG_HW_RANDOM is not set
+-# CONFIG_RTC is not set
+-# CONFIG_GEN_RTC is not set
+ # CONFIG_R3964 is not set
+ # CONFIG_TCG_TPM is not set
+ # CONFIG_I2C is not set
+@@ -389,9 +400,24 @@
+ # CONFIG_SPI_AT25 is not set
+ # CONFIG_SPI_SPIDEV is not set
+ # CONFIG_SPI_TLE62X0 is not set
++CONFIG_HAVE_GPIO_LIB=y
++
++#
++# GPIO Support
++#
++
++#
++# I2C GPIO expanders:
++#
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_GPIO_MCP23S08 is not set
+ # CONFIG_W1 is not set
+ # CONFIG_POWER_SUPPLY is not set
+ # CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
+ CONFIG_WATCHDOG=y
+ # CONFIG_WATCHDOG_NOWAYOUT is not set
+
+@@ -471,10 +497,6 @@
+ #
+ # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+ #
-
-#
--# Cryptographic options
+-# USB Gadget Support
-#
--# CONFIG_CRYPTO is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+CONFIG_CRYPTO=y
-+CONFIG_CRYPTO_ALGAPI=m
-+CONFIG_CRYPTO_BLKCIPHER=m
-+CONFIG_CRYPTO_HASH=m
-+CONFIG_CRYPTO_MANAGER=m
-+CONFIG_CRYPTO_HMAC=m
-+# CONFIG_CRYPTO_XCBC is not set
-+# CONFIG_CRYPTO_NULL is not set
-+# CONFIG_CRYPTO_MD4 is not set
-+CONFIG_CRYPTO_MD5=m
-+CONFIG_CRYPTO_SHA1=m
-+# CONFIG_CRYPTO_SHA256 is not set
-+# CONFIG_CRYPTO_SHA512 is not set
-+# CONFIG_CRYPTO_WP512 is not set
-+# CONFIG_CRYPTO_TGR192 is not set
-+# CONFIG_CRYPTO_GF128MUL is not set
-+# CONFIG_CRYPTO_ECB is not set
-+CONFIG_CRYPTO_CBC=m
-+# CONFIG_CRYPTO_PCBC is not set
-+# CONFIG_CRYPTO_LRW is not set
-+# CONFIG_CRYPTO_XTS is not set
-+# CONFIG_CRYPTO_CRYPTD is not set
-+CONFIG_CRYPTO_DES=m
-+# CONFIG_CRYPTO_FCRYPT is not set
-+# CONFIG_CRYPTO_BLOWFISH is not set
-+# CONFIG_CRYPTO_TWOFISH is not set
-+# CONFIG_CRYPTO_SERPENT is not set
-+# CONFIG_CRYPTO_AES is not set
-+# CONFIG_CRYPTO_CAST5 is not set
-+# CONFIG_CRYPTO_CAST6 is not set
-+# CONFIG_CRYPTO_TEA is not set
-+# CONFIG_CRYPTO_ARC4 is not set
-+# CONFIG_CRYPTO_KHAZAD is not set
-+# CONFIG_CRYPTO_ANUBIS is not set
-+# CONFIG_CRYPTO_SEED is not set
-+CONFIG_CRYPTO_DEFLATE=m
-+# CONFIG_CRYPTO_MICHAEL_MIC is not set
-+# CONFIG_CRYPTO_CRC32C is not set
-+# CONFIG_CRYPTO_CAMELLIA is not set
-+# CONFIG_CRYPTO_TEST is not set
-+# CONFIG_CRYPTO_AUTHENC is not set
-+# CONFIG_CRYPTO_HW is not set
+ CONFIG_USB_GADGET=y
+ # CONFIG_USB_GADGET_DEBUG_FILES is not set
+ CONFIG_USB_GADGET_SELECTED=y
+@@ -499,7 +521,9 @@
+ # CONFIG_USB_FILE_STORAGE is not set
+ # CONFIG_USB_G_SERIAL is not set
+ # CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
+ # CONFIG_MMC is not set
++# CONFIG_MEMSTICK is not set
+ # CONFIG_NEW_LEDS is not set
+ CONFIG_RTC_LIB=y
+ CONFIG_RTC_CLASS=y
+@@ -519,15 +543,17 @@
+ #
+ # SPI RTC drivers
+ #
+-# CONFIG_RTC_DRV_RS5C348 is not set
+ # CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
#
- # Library routines
-@@ -794,10 +1158,10 @@
- CONFIG_BITREVERSE=y
- CONFIG_CRC_CCITT=m
- # CONFIG_CRC16 is not set
--# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC_ITU_T=m
- CONFIG_CRC32=y
-+CONFIG_CRC7=m
+ # Platform RTC drivers
+ #
++# CONFIG_RTC_DRV_DS1511 is not set
+ # CONFIG_RTC_DRV_DS1553 is not set
+-# CONFIG_RTC_DRV_STK17TA8 is not set
+ # CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
+ # CONFIG_RTC_DRV_M48T86 is not set
+ # CONFIG_RTC_DRV_M48T59 is not set
+ # CONFIG_RTC_DRV_V3020 is not set
+@@ -545,9 +571,9 @@
+ #
+ # File systems
+ #
++# CONFIG_DNOTIFY is not set
+ # CONFIG_INOTIFY is not set
+ # CONFIG_QUOTA is not set
+-# CONFIG_DNOTIFY is not set
+ # CONFIG_AUTOFS_FS is not set
+ # CONFIG_AUTOFS4_FS is not set
+ # CONFIG_FUSE_FS is not set
+@@ -580,7 +606,6 @@
+ # CONFIG_NETWORK_FILESYSTEMS is not set
+ # CONFIG_NLS is not set
+ # CONFIG_DLM is not set
+-# CONFIG_INSTRUMENTATION is not set
+
+ #
+ # Kernel hacking
+@@ -616,6 +641,7 @@
# CONFIG_LIBCRC32C is not set
--CONFIG_AUDIT_GENERIC=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
- CONFIG_PLIST=y
++CONFIG_GENERIC_ALLOCATOR=y
+ CONFIG_HAS_IOMEM=y
+ CONFIG_HAS_IOPORT=y
+ CONFIG_HAS_DMA=y
--- /dev/null
-+++ b/arch/avr32/configs/atstk1003_defconfig
-@@ -0,0 +1,1041 @@
++++ b/arch/avr32/configs/atstk1006_defconfig
+@@ -0,0 +1,1235 @@
+#
+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.24
-+# Thu Mar 6 12:50:27 2008
++# Linux kernel version: 2.6.25.4
++# Wed Jun 11 15:40:45 2008
+#
+CONFIG_AVR32=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
-+CONFIG_BSD_PROCESS_ACCT=y
-+CONFIG_BSD_PROCESS_ACCT_V3=y
-+CONFIG_TASKSTATS=y
-+CONFIG_TASK_DELAY_ACCT=y
-+# CONFIG_TASK_XACCT is not set
-+# CONFIG_USER_NS is not set
-+# CONFIG_PID_NS is not set
-+CONFIG_AUDIT=y
++# CONFIG_BSD_PROCESS_ACCT is not set
++# CONFIG_TASKSTATS is not set
++# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
-+CONFIG_FAIR_GROUP_SCHED=y
-+CONFIG_FAIR_USER_SCHED=y
-+# CONFIG_FAIR_CGROUP_SCHED is not set
++# CONFIG_GROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
++CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
++# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
++# CONFIG_COMPAT_BRK is not set
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
++CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
-+# CONFIG_SLUB_DEBUG is not set
++CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
++CONFIG_PROFILING=y
++# CONFIG_MARKERS is not set
++CONFIG_OPROFILE=m
++CONFIG_HAVE_OPROFILE=y
++CONFIG_KPROBES=y
++CONFIG_HAVE_KPROBES=y
++# CONFIG_HAVE_KRETPROBES is not set
++CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
++CONFIG_CLASSIC_RCU=y
+
+#
+# System Type and features
+CONFIG_PERFORMANCE_COUNTERS=y
+CONFIG_PLATFORM_AT32AP=y
+CONFIG_CPU_AT32AP700X=y
-+CONFIG_CPU_AT32AP7001=y
++CONFIG_CPU_AT32AP7000=y
+CONFIG_BOARD_ATSTK1000=y
+# CONFIG_BOARD_ATNGW100 is not set
+# CONFIG_BOARD_ATSTK1002 is not set
-+CONFIG_BOARD_ATSTK1003=y
++# CONFIG_BOARD_ATSTK1003 is not set
+# CONFIG_BOARD_ATSTK1004 is not set
++CONFIG_BOARD_ATSTK1006=y
+# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
+# CONFIG_BOARD_ATSTK100X_SPI1 is not set
+# CONFIG_BOARD_ATSTK1000_J2_LED is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
++# CONFIG_SCHED_HRTICK is not set
+CONFIG_CMDLINE=""
+
+#
+# Power management options
+#
++CONFIG_ARCH_SUSPEND_POSSIBLE=y
++CONFIG_PM=y
++# CONFIG_PM_LEGACY is not set
++# CONFIG_PM_DEBUG is not set
++CONFIG_PM_SLEEP=y
++CONFIG_SUSPEND=y
++CONFIG_SUSPEND_FREEZER=y
+
+#
+# CPU Frequency scaling
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+# CONFIG_CPU_FREQ_STAT is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
-+# CONFIG_NET_KEY is not set
++CONFIG_XFRM=y
++CONFIG_XFRM_USER=m
++# CONFIG_XFRM_SUB_POLICY is not set
++# CONFIG_XFRM_MIGRATE is not set
++# CONFIG_XFRM_STATISTICS is not set
++CONFIG_NET_KEY=m
++# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
-+# CONFIG_IP_PNP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_IP_PNP_BOOTP is not set
++# CONFIG_IP_PNP_RARP is not set
++CONFIG_NET_IPIP=m
++CONFIG_NET_IPGRE=m
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
-+# CONFIG_INET_AH is not set
-+# CONFIG_INET_ESP is not set
++CONFIG_INET_AH=m
++CONFIG_INET_ESP=m
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
-+# CONFIG_INET_TUNNEL is not set
-+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-+# CONFIG_INET_XFRM_MODE_BEET is not set
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_XFRM_MODE_TRANSPORT=m
++CONFIG_INET_XFRM_MODE_TUNNEL=m
++CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
-+# CONFIG_INET_DIAG is not set
++CONFIG_INET_DIAG=y
++CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
-+# CONFIG_IPV6 is not set
-+# CONFIG_INET6_XFRM_TUNNEL is not set
-+# CONFIG_INET6_TUNNEL is not set
++CONFIG_IPV6=m
++# CONFIG_IPV6_PRIVACY is not set
++# CONFIG_IPV6_ROUTER_PREF is not set
++# CONFIG_IPV6_OPTIMISTIC_DAD is not set
++CONFIG_INET6_AH=m
++CONFIG_INET6_ESP=m
++CONFIG_INET6_IPCOMP=m
++# CONFIG_IPV6_MIP6 is not set
++CONFIG_INET6_XFRM_TUNNEL=m
++CONFIG_INET6_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
++CONFIG_IPV6_SIT=m
++CONFIG_IPV6_TUNNEL=m
++# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
-+# CONFIG_BRIDGE is not set
++CONFIG_BRIDGE=m
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
++CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
++# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
-+# CONFIG_MTD_NAND is not set
++CONFIG_MTD_NAND=y
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_SMC is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++CONFIG_MTD_NAND_IDS=y
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++CONFIG_MTD_NAND_ATMEL=y
++CONFIG_MTD_NAND_ATMEL_ECC_HW=y
++# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
++# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
++# CONFIG_MTD_NAND_NANDSIM is not set
++# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
-+# CONFIG_MTD_UBI is not set
++CONFIG_MTD_UBI=m
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_RESERVE=1
++CONFIG_MTD_UBI_GLUEBI=y
++
++#
++# UBI debugging options
++#
++# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_RAM=m
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
-+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
++# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_ATMEL_SSC=m
-+# CONFIG_IDE is not set
++# CONFIG_ENCLOSURE_SERVICES is not set
++# CONFIG_HAVE_IDE is not set
+
+#
+# SCSI device support
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
-+CONFIG_SCSI_LOWLEVEL=y
-+# CONFIG_ISCSI_TCP is not set
-+# CONFIG_SCSI_DEBUG is not set
++# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
++# CONFIG_SATA_MV is not set
+CONFIG_PATA_AT32=m
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_MD is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
-+# CONFIG_TUN is not set
++CONFIG_TUN=m
+# CONFIG_VETH is not set
-+# CONFIG_NET_ETHERNET is not set
++CONFIG_PHYLIB=y
++
++#
++# MII PHY device drivers
++#
++# CONFIG_MARVELL_PHY is not set
++# CONFIG_DAVICOM_PHY is not set
++# CONFIG_QSEMI_PHY is not set
++# CONFIG_LXT_PHY is not set
++# CONFIG_CICADA_PHY is not set
++# CONFIG_VITESSE_PHY is not set
++# CONFIG_SMSC_PHY is not set
++# CONFIG_BROADCOM_PHY is not set
++# CONFIG_ICPLUS_PHY is not set
++# CONFIG_REALTEK_PHY is not set
++# CONFIG_FIXED_PHY is not set
++# CONFIG_MDIO_BITBANG is not set
++CONFIG_NET_ETHERNET=y
++# CONFIG_MII is not set
++CONFIG_MACB=y
++# CONFIG_ENC28J60 is not set
++# CONFIG_IBM_NEW_EMAC_ZMII is not set
++# CONFIG_IBM_NEW_EMAC_RGMII is not set
++# CONFIG_IBM_NEW_EMAC_TAH is not set
++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
++# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
-+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
-+# CONFIG_INPUT_EVDEV is not set
++CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
-+# CONFIG_RTC is not set
-+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+#
+# Miscellaneous I2C Chip support
+#
-+# CONFIG_SENSORS_DS1337 is not set
-+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
-+# CONFIG_SENSORS_PCA9539 is not set
++# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCF8591 is not set
++# CONFIG_TPS65010 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_SPI_AT25 is not set
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
++CONFIG_HAVE_GPIO_LIB=y
++
++#
++# GPIO Support
++#
++# CONFIG_DEBUG_GPIO is not set
++
++#
++# I2C GPIO expanders:
++#
++# CONFIG_GPIO_PCA953X is not set
++# CONFIG_GPIO_PCF857X is not set
++
++#
++# SPI GPIO expanders:
++#
++# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
++# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+# CONFIG_FB is not set
-+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+
-+#
-+# Sound
-+#
-+CONFIG_SOUND=m
-+
-+#
-+# Advanced Linux Sound Architecture
-+#
-+CONFIG_SND=m
++CONFIG_FB=y
++# CONFIG_FIRMWARE_EDID is not set
++# CONFIG_FB_DDC is not set
++CONFIG_FB_CFB_FILLRECT=y
++CONFIG_FB_CFB_COPYAREA=y
++CONFIG_FB_CFB_IMAGEBLIT=y
++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
++# CONFIG_FB_SYS_FILLRECT is not set
++# CONFIG_FB_SYS_COPYAREA is not set
++# CONFIG_FB_SYS_IMAGEBLIT is not set
++# CONFIG_FB_SYS_FOPS is not set
++CONFIG_FB_DEFERRED_IO=y
++# CONFIG_FB_SVGALIB is not set
++# CONFIG_FB_MACMODES is not set
++# CONFIG_FB_BACKLIGHT is not set
++# CONFIG_FB_MODE_HELPERS is not set
++# CONFIG_FB_TILEBLITTING is not set
++
++#
++# Frame buffer hardware drivers
++#
++# CONFIG_FB_S1D13XXX is not set
++CONFIG_FB_ATMEL=y
++# CONFIG_FB_VIRTUAL is not set
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_LCD_LTV350QV=y
++# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
++
++#
++# Display device support
++#
++# CONFIG_DISPLAY_SUPPORT is not set
++# CONFIG_LOGO is not set
++
++#
++# Sound
++#
++CONFIG_SOUND=m
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
-+CONFIG_SND_SUPPORT_OLD_API=y
-+CONFIG_SND_VERBOSE_PROCFS=y
++# CONFIG_SND_SUPPORT_OLD_API is not set
++# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+
+#
++# ALSA SoC audio for Freescale SOCs
++#
++
++#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
-+
-+#
-+# USB Gadget Support
-+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+CONFIG_USB_GADGET_DEBUG_FS=y
++# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+CONFIG_USB_GADGET_ATMEL_USBA=y
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
-+# CONFIG_MMC_BLOCK_BOUNCE is not set
++CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+
+#
+#
+CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_SPI=m
++# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
-+CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+CONFIG_LEDS_ATMEL_PWM=m
-+CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_GPIO=m
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
-+CONFIG_LEDS_TRIGGER_TIMER=y
-+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
++# CONFIG_RTC_DRV_S35390A is not set
+
+#
+# SPI RTC drivers
+#
-+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
++# CONFIG_RTC_DRV_R9701 is not set
++# CONFIG_RTC_DRV_RS5C348 is not set
+
+#
+# Platform RTC drivers
+#
++# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
++# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# Userspace I/O
+#
-+CONFIG_UIO=m
++# CONFIG_UIO is not set
+
+#
+# File systems
+#
-+CONFIG_EXT2_FS=m
++CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
-+CONFIG_EXT3_FS=m
++CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4DEV_FS is not set
-+CONFIG_JBD=m
++CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
-+# CONFIG_MINIX_FS is not set
-+# CONFIG_ROMFS_FS is not set
++# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
-+# CONFIG_DNOTIFY is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
-+CONFIG_JFFS2_FS_WRITEBUFFER=y
-+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
++# CONFIG_JFFS2_FS_WRITEBUFFER is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
++CONFIG_MINIX_FS=m
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
++# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
-+# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3=y
++# CONFIG_NFS_V3_ACL is not set
++# CONFIG_NFS_V4 is not set
++# CONFIG_NFS_DIRECTIO is not set
++# CONFIG_NFSD is not set
++CONFIG_ROOT_NFS=y
++CONFIG_LOCKD=y
++CONFIG_LOCKD_V4=y
++CONFIG_NFS_COMMON=y
++CONFIG_SUNRPC=y
++# CONFIG_SUNRPC_BIND34 is not set
++# CONFIG_RPCSEC_GSS_KRB5 is not set
++# CONFIG_RPCSEC_GSS_SPKM3 is not set
++# CONFIG_SMB_FS is not set
++# CONFIG_CIFS is not set
++# CONFIG_NCP_FS is not set
++# CONFIG_CODA_FS is not set
++# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
-+CONFIG_INSTRUMENTATION=y
-+CONFIG_PROFILING=y
-+CONFIG_OPROFILE=m
-+CONFIG_KPROBES=y
-+# CONFIG_MARKERS is not set
+
+#
+# Kernel hacking
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+CONFIG_FRAME_POINTER=y
-+CONFIG_FORCED_INLINING=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_KPROBES_SANITY_TEST is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+# CONFIG_CRYPTO is not set
++CONFIG_CRYPTO=y
++CONFIG_CRYPTO_ALGAPI=m
++CONFIG_CRYPTO_AEAD=m
++CONFIG_CRYPTO_BLKCIPHER=m
++# CONFIG_CRYPTO_SEQIV is not set
++CONFIG_CRYPTO_HASH=m
++CONFIG_CRYPTO_MANAGER=m
++CONFIG_CRYPTO_HMAC=m
++# CONFIG_CRYPTO_XCBC is not set
++# CONFIG_CRYPTO_NULL is not set
++# CONFIG_CRYPTO_MD4 is not set
++CONFIG_CRYPTO_MD5=m
++CONFIG_CRYPTO_SHA1=m
++# CONFIG_CRYPTO_SHA256 is not set
++# CONFIG_CRYPTO_SHA512 is not set
++# CONFIG_CRYPTO_WP512 is not set
++# CONFIG_CRYPTO_TGR192 is not set
++# CONFIG_CRYPTO_GF128MUL is not set
++# CONFIG_CRYPTO_ECB is not set
++CONFIG_CRYPTO_CBC=m
++# CONFIG_CRYPTO_PCBC is not set
++# CONFIG_CRYPTO_LRW is not set
++# CONFIG_CRYPTO_XTS is not set
++# CONFIG_CRYPTO_CTR is not set
++# CONFIG_CRYPTO_GCM is not set
++# CONFIG_CRYPTO_CCM is not set
++# CONFIG_CRYPTO_CRYPTD is not set
++CONFIG_CRYPTO_DES=m
++# CONFIG_CRYPTO_FCRYPT is not set
++# CONFIG_CRYPTO_BLOWFISH is not set
++# CONFIG_CRYPTO_TWOFISH is not set
++# CONFIG_CRYPTO_SERPENT is not set
++# CONFIG_CRYPTO_AES is not set
++# CONFIG_CRYPTO_CAST5 is not set
++# CONFIG_CRYPTO_CAST6 is not set
++# CONFIG_CRYPTO_TEA is not set
++# CONFIG_CRYPTO_ARC4 is not set
++# CONFIG_CRYPTO_KHAZAD is not set
++# CONFIG_CRYPTO_ANUBIS is not set
++# CONFIG_CRYPTO_SEED is not set
++# CONFIG_CRYPTO_SALSA20 is not set
++CONFIG_CRYPTO_DEFLATE=m
++# CONFIG_CRYPTO_MICHAEL_MIC is not set
++# CONFIG_CRYPTO_CRC32C is not set
++# CONFIG_CRYPTO_CAMELLIA is not set
++# CONFIG_CRYPTO_TEST is not set
++CONFIG_CRYPTO_AUTHENC=m
++# CONFIG_CRYPTO_LZO is not set
++# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+# CONFIG_LIBCRC32C is not set
-+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
++CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
--- /dev/null
-+++ b/arch/avr32/configs/atstk1004_defconfig
-@@ -0,0 +1,639 @@
-+#
-+# Automatically generated make config: don't edit
-+# Linux kernel version: 2.6.24
-+# Thu Mar 6 12:51:05 2008
-+#
-+CONFIG_AVR32=y
-+CONFIG_GENERIC_GPIO=y
-+CONFIG_GENERIC_HARDIRQS=y
-+CONFIG_STACKTRACE_SUPPORT=y
-+CONFIG_LOCKDEP_SUPPORT=y
-+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-+CONFIG_HARDIRQS_SW_RESEND=y
-+CONFIG_GENERIC_IRQ_PROBE=y
-+CONFIG_RWSEM_GENERIC_SPINLOCK=y
-+CONFIG_GENERIC_TIME=y
-+CONFIG_GENERIC_CLOCKEVENTS=y
-+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
-+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-+CONFIG_ARCH_SUPPORTS_OPROFILE=y
-+CONFIG_GENERIC_HWEIGHT=y
-+CONFIG_GENERIC_CALIBRATE_DELAY=y
-+CONFIG_GENERIC_BUG=y
-+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
++++ b/arch/avr32/drivers/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_DW_DMAC) += dw-dmac.o
+--- /dev/null
++++ b/arch/avr32/drivers/dw-dmac.c
+@@ -0,0 +1,761 @@
++/*
++ * Driver for the Synopsys DesignWare DMA Controller
++ *
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/clk.h>
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
+
-+#
-+# General setup
-+#
-+CONFIG_EXPERIMENTAL=y
-+CONFIG_BROKEN_ON_SMP=y
-+CONFIG_INIT_ENV_ARG_LIMIT=32
-+CONFIG_LOCALVERSION=""
-+# CONFIG_LOCALVERSION_AUTO is not set
-+# CONFIG_SYSVIPC is not set
-+# CONFIG_POSIX_MQUEUE is not set
-+# CONFIG_BSD_PROCESS_ACCT is not set
-+# CONFIG_TASKSTATS is not set
-+# CONFIG_USER_NS is not set
-+# CONFIG_PID_NS is not set
-+# CONFIG_AUDIT is not set
-+# CONFIG_IKCONFIG is not set
-+CONFIG_LOG_BUF_SHIFT=14
-+# CONFIG_CGROUPS is not set
-+# CONFIG_FAIR_GROUP_SCHED is not set
-+CONFIG_SYSFS_DEPRECATED=y
-+# CONFIG_RELAY is not set
-+# CONFIG_BLK_DEV_INITRD is not set
-+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-+CONFIG_SYSCTL=y
-+CONFIG_EMBEDDED=y
-+# CONFIG_SYSCTL_SYSCALL is not set
-+CONFIG_KALLSYMS=y
-+# CONFIG_KALLSYMS_EXTRA_PASS is not set
-+CONFIG_HOTPLUG=y
-+CONFIG_PRINTK=y
-+CONFIG_BUG=y
-+CONFIG_ELF_CORE=y
-+# CONFIG_BASE_FULL is not set
-+# CONFIG_FUTEX is not set
-+# CONFIG_EPOLL is not set
-+# CONFIG_SIGNALFD is not set
-+# CONFIG_EVENTFD is not set
-+CONFIG_SHMEM=y
-+CONFIG_VM_EVENT_COUNTERS=y
-+# CONFIG_SLAB is not set
-+# CONFIG_SLUB is not set
-+CONFIG_SLOB=y
-+# CONFIG_TINY_SHMEM is not set
-+CONFIG_BASE_SMALL=1
-+# CONFIG_MODULES is not set
-+# CONFIG_BLOCK is not set
++#include <asm/dma-controller.h>
++#include <asm/io.h>
+
-+#
-+# System Type and features
-+#
-+CONFIG_TICK_ONESHOT=y
-+CONFIG_NO_HZ=y
-+CONFIG_HIGH_RES_TIMERS=y
-+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-+CONFIG_SUBARCH_AVR32B=y
-+CONFIG_MMU=y
-+CONFIG_PERFORMANCE_COUNTERS=y
-+CONFIG_PLATFORM_AT32AP=y
-+CONFIG_CPU_AT32AP700X=y
-+CONFIG_CPU_AT32AP7002=y
-+CONFIG_BOARD_ATSTK1000=y
-+# CONFIG_BOARD_ATNGW100 is not set
-+# CONFIG_BOARD_ATSTK1002 is not set
-+# CONFIG_BOARD_ATSTK1003 is not set
-+CONFIG_BOARD_ATSTK1004=y
-+# CONFIG_BOARD_ATSTK100X_CUSTOM is not set
-+# CONFIG_BOARD_ATSTK100X_SPI1 is not set
-+# CONFIG_BOARD_ATSTK1000_J2_LED is not set
-+CONFIG_BOARD_ATSTK1000_EXTDAC=y
-+# CONFIG_BOARD_ATSTK100X_ENABLE_AC97 is not set
-+# CONFIG_BOARD_ATSTK1000_CF_HACKS is not set
-+# CONFIG_BOARD_ATSTK100X_ENABLE_PSIF is not set
-+CONFIG_LOADER_U_BOOT=y
++#include "dw-dmac.h"
+
-+#
-+# Atmel AVR32 AP options
-+#
-+# CONFIG_AP700X_32_BIT_SMC is not set
-+CONFIG_AP700X_16_BIT_SMC=y
-+# CONFIG_AP700X_8_BIT_SMC is not set
-+# CONFIG_GPIO_DEV is not set
-+CONFIG_LOAD_ADDRESS=0x10000000
-+CONFIG_ENTRY_ADDRESS=0x90000000
-+CONFIG_PHYS_OFFSET=0x10000000
-+CONFIG_PREEMPT_NONE=y
-+# CONFIG_PREEMPT_VOLUNTARY is not set
-+# CONFIG_PREEMPT is not set
-+# CONFIG_HAVE_ARCH_BOOTMEM_NODE is not set
-+# CONFIG_ARCH_HAVE_MEMORY_PRESENT is not set
-+# CONFIG_NEED_NODE_MEMMAP_SIZE is not set
-+CONFIG_ARCH_FLATMEM_ENABLE=y
-+# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-+# CONFIG_ARCH_SPARSEMEM_ENABLE is not set
-+CONFIG_SELECT_MEMORY_MODEL=y
-+CONFIG_FLATMEM_MANUAL=y
-+# CONFIG_DISCONTIGMEM_MANUAL is not set
-+# CONFIG_SPARSEMEM_MANUAL is not set
-+CONFIG_FLATMEM=y
-+CONFIG_FLAT_NODE_MEM_MAP=y
-+# CONFIG_SPARSEMEM_STATIC is not set
-+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-+CONFIG_SPLIT_PTLOCK_CPUS=4
-+# CONFIG_RESOURCES_64BIT is not set
-+CONFIG_ZONE_DMA_FLAG=0
-+CONFIG_VIRT_TO_BUS=y
-+# CONFIG_OWNERSHIP_TRACE is not set
-+# CONFIG_NMI_DEBUGGING is not set
-+# CONFIG_DW_DMAC is not set
-+# CONFIG_HZ_100 is not set
-+CONFIG_HZ_250=y
-+# CONFIG_HZ_300 is not set
-+# CONFIG_HZ_1000 is not set
-+CONFIG_HZ=250
-+CONFIG_CMDLINE=""
++#define DMAC_NR_CHANNELS 3
++#define DMAC_MAX_BLOCKSIZE 4095
+
-+#
-+# Power management options
-+#
++enum {
++ CH_STATE_FREE = 0,
++ CH_STATE_ALLOCATED,
++ CH_STATE_BUSY,
++};
+
-+#
-+# CPU Frequency scaling
-+#
-+CONFIG_CPU_FREQ=y
-+CONFIG_CPU_FREQ_TABLE=y
-+# CONFIG_CPU_FREQ_DEBUG is not set
-+# CONFIG_CPU_FREQ_STAT is not set
-+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-+CONFIG_CPU_FREQ_GOV_USERSPACE=y
-+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-+CONFIG_CPU_FREQ_AT32AP=y
++struct dw_dma_lli {
++ dma_addr_t sar;
++ dma_addr_t dar;
++ dma_addr_t llp;
++ u32 ctllo;
++ u32 ctlhi;
++ u32 sstat;
++ u32 dstat;
++};
+
-+#
-+# Bus options
-+#
-+# CONFIG_ARCH_SUPPORTS_MSI is not set
-+# CONFIG_PCCARD is not set
++struct dw_dma_block {
++ struct dw_dma_lli *lli_vaddr;
++ dma_addr_t lli_dma_addr;
++};
+
-+#
-+# Executable file formats
-+#
-+CONFIG_BINFMT_ELF=y
-+# CONFIG_BINFMT_MISC is not set
++struct dw_dma_channel {
++ unsigned int state;
++ int is_cyclic;
++ struct dma_request_sg *req_sg;
++ struct dma_request_cyclic *req_cyclic;
++ unsigned int nr_blocks;
++ int direction;
++ struct dw_dma_block *block;
++};
+
-+#
-+# Networking
-+#
-+CONFIG_NET=y
++struct dw_dma_controller {
++ spinlock_t lock;
++ void * __iomem regs;
++ struct dma_pool *lli_pool;
++ struct clk *hclk;
++ struct dma_controller dma;
++ struct dw_dma_channel channel[DMAC_NR_CHANNELS];
++};
++#define to_dw_dmac(dmac) container_of(dmac, struct dw_dma_controller, dma)
+
-+#
-+# Networking options
-+#
-+CONFIG_PACKET=y
-+CONFIG_PACKET_MMAP=y
-+CONFIG_UNIX=y
-+# CONFIG_NET_KEY is not set
-+CONFIG_INET=y
-+# CONFIG_IP_MULTICAST is not set
-+# CONFIG_IP_ADVANCED_ROUTER is not set
-+CONFIG_IP_FIB_HASH=y
-+# CONFIG_IP_PNP is not set
-+# CONFIG_NET_IPIP is not set
-+# CONFIG_NET_IPGRE is not set
-+# CONFIG_ARPD is not set
-+# CONFIG_SYN_COOKIES is not set
-+# CONFIG_INET_AH is not set
-+# CONFIG_INET_ESP is not set
-+# CONFIG_INET_IPCOMP is not set
-+# CONFIG_INET_XFRM_TUNNEL is not set
-+# CONFIG_INET_TUNNEL is not set
-+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-+# CONFIG_INET_XFRM_MODE_BEET is not set
-+# CONFIG_INET_LRO is not set
-+# CONFIG_INET_DIAG is not set
-+# CONFIG_TCP_CONG_ADVANCED is not set
-+CONFIG_TCP_CONG_CUBIC=y
-+CONFIG_DEFAULT_TCP_CONG="cubic"
-+# CONFIG_TCP_MD5SIG is not set
-+# CONFIG_IPV6 is not set
-+# CONFIG_INET6_XFRM_TUNNEL is not set
-+# CONFIG_INET6_TUNNEL is not set
-+# CONFIG_NETWORK_SECMARK is not set
-+# CONFIG_NETFILTER is not set
-+# CONFIG_IP_DCCP is not set
-+# CONFIG_IP_SCTP is not set
-+# CONFIG_TIPC is not set
-+# CONFIG_ATM is not set
-+# CONFIG_BRIDGE is not set
-+# CONFIG_VLAN_8021Q is not set
-+# CONFIG_DECNET is not set
-+# CONFIG_LLC2 is not set
-+# CONFIG_IPX is not set
-+# CONFIG_ATALK is not set
-+# CONFIG_X25 is not set
-+# CONFIG_LAPB is not set
-+# CONFIG_ECONET is not set
-+# CONFIG_WAN_ROUTER is not set
-+# CONFIG_NET_SCHED is not set
++#define dmac_writel_hi(dmac, reg, value) \
++ __raw_writel((value), (dmac)->regs + DW_DMAC_##reg + 4)
++#define dmac_readl_hi(dmac, reg) \
++ __raw_readl((dmac)->regs + DW_DMAC_##reg + 4)
++#define dmac_writel_lo(dmac, reg, value) \
++ __raw_writel((value), (dmac)->regs + DW_DMAC_##reg)
++#define dmac_readl_lo(dmac, reg) \
++ __raw_readl((dmac)->regs + DW_DMAC_##reg)
++#define dmac_chan_writel_hi(dmac, chan, reg, value) \
++ __raw_writel((value), ((dmac)->regs + 0x58 * (chan) \
++ + DW_DMAC_CHAN_##reg + 4))
++#define dmac_chan_readl_hi(dmac, chan, reg) \
++ __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg + 4)
++#define dmac_chan_writel_lo(dmac, chan, reg, value) \
++ __raw_writel((value), (dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
++#define dmac_chan_readl_lo(dmac, chan, reg) \
++ __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
++#define set_channel_bit(dmac, reg, chan) \
++ dmac_writel_lo(dmac, reg, (1 << (chan)) | (1 << ((chan) + 8)))
++#define clear_channel_bit(dmac, reg, chan) \
++ dmac_writel_lo(dmac, reg, (0 << (chan)) | (1 << ((chan) + 8)))
+
-+#
-+# Network testing
-+#
-+# CONFIG_NET_PKTGEN is not set
-+# CONFIG_HAMRADIO is not set
-+# CONFIG_IRDA is not set
-+# CONFIG_BT is not set
-+# CONFIG_AF_RXRPC is not set
++static int dmac_alloc_channel(struct dma_controller *_dmac)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++ struct dw_dma_channel *chan;
++ unsigned long flags;
++ int i;
+
-+#
-+# Wireless
-+#
-+# CONFIG_CFG80211 is not set
-+# CONFIG_WIRELESS_EXT is not set
-+# CONFIG_MAC80211 is not set
-+# CONFIG_IEEE80211 is not set
-+# CONFIG_RFKILL is not set
-+# CONFIG_NET_9P is not set
++ spin_lock_irqsave(&dmac->lock, flags);
++ for (i = 0; i < DMAC_NR_CHANNELS; i++)
++ if (dmac->channel[i].state == CH_STATE_FREE)
++ break;
+
-+#
-+# Device Drivers
-+#
++ if (i < DMAC_NR_CHANNELS) {
++ chan = &dmac->channel[i];
++ chan->state = CH_STATE_ALLOCATED;
++ } else {
++ i = -EBUSY;
++ }
+
-+#
-+# Generic Driver Options
-+#
-+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-+CONFIG_STANDALONE=y
-+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-+# CONFIG_FW_LOADER is not set
-+# CONFIG_SYS_HYPERVISOR is not set
-+# CONFIG_CONNECTOR is not set
-+CONFIG_MTD=y
-+# CONFIG_MTD_DEBUG is not set
-+# CONFIG_MTD_CONCAT is not set
-+CONFIG_MTD_PARTITIONS=y
-+# CONFIG_MTD_REDBOOT_PARTS is not set
-+CONFIG_MTD_CMDLINE_PARTS=y
++ spin_unlock_irqrestore(&dmac->lock, flags);
+
-+#
-+# User Modules And Translation Layers
-+#
-+CONFIG_MTD_CHAR=y
-+# CONFIG_MTD_OOPS is not set
++ return i;
++}
+
-+#
-+# RAM/ROM/Flash chip drivers
-+#
-+CONFIG_MTD_CFI=y
-+# CONFIG_MTD_JEDECPROBE is not set
-+CONFIG_MTD_GEN_PROBE=y
-+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-+CONFIG_MTD_MAP_BANK_WIDTH_1=y
-+CONFIG_MTD_MAP_BANK_WIDTH_2=y
-+CONFIG_MTD_MAP_BANK_WIDTH_4=y
-+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-+CONFIG_MTD_CFI_I1=y
-+CONFIG_MTD_CFI_I2=y
-+# CONFIG_MTD_CFI_I4 is not set
-+# CONFIG_MTD_CFI_I8 is not set
-+# CONFIG_MTD_CFI_INTELEXT is not set
-+CONFIG_MTD_CFI_AMDSTD=y
-+# CONFIG_MTD_CFI_STAA is not set
-+CONFIG_MTD_CFI_UTIL=y
-+# CONFIG_MTD_RAM is not set
-+# CONFIG_MTD_ROM is not set
-+# CONFIG_MTD_ABSENT is not set
++static void dmac_release_channel(struct dma_controller *_dmac, int channel)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
+
-+#
-+# Mapping drivers for chip access
-+#
-+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-+CONFIG_MTD_PHYSMAP=y
-+CONFIG_MTD_PHYSMAP_START=0x8000000
-+CONFIG_MTD_PHYSMAP_LEN=0x0
-+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-+# CONFIG_MTD_PLATRAM is not set
++ BUG_ON(channel >= DMAC_NR_CHANNELS
++ || dmac->channel[channel].state != CH_STATE_ALLOCATED);
+
-+#
-+# Self-contained MTD device drivers
-+#
-+# CONFIG_MTD_DATAFLASH is not set
-+# CONFIG_MTD_M25P80 is not set
-+# CONFIG_MTD_SLRAM is not set
-+# CONFIG_MTD_PHRAM is not set
-+# CONFIG_MTD_MTDRAM is not set
++ dmac->channel[channel].state = CH_STATE_FREE;
++}
+
-+#
-+# Disk-On-Chip Device Drivers
-+#
-+# CONFIG_MTD_DOC2000 is not set
-+# CONFIG_MTD_DOC2001 is not set
-+# CONFIG_MTD_DOC2001PLUS is not set
-+# CONFIG_MTD_NAND is not set
-+# CONFIG_MTD_ONENAND is not set
++static struct dw_dma_block *allocate_blocks(struct dw_dma_controller *dmac,
++ unsigned int nr_blocks)
++{
++ struct dw_dma_block *block;
++ void *p;
++ unsigned int i;
+
-+#
-+# UBI - Unsorted block images
-+#
-+# CONFIG_MTD_UBI is not set
-+# CONFIG_PARPORT is not set
-+CONFIG_MISC_DEVICES=y
-+# CONFIG_ATMEL_PWM is not set
-+CONFIG_ATMEL_TCLIB=y
-+CONFIG_ATMEL_TCB_CLKSRC=y
-+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
-+# CONFIG_EEPROM_93CX6 is not set
-+# CONFIG_ATMEL_SSC is not set
++ block = kmalloc(nr_blocks * sizeof(*block),
++ GFP_KERNEL);
++ if (unlikely(!block))
++ return NULL;
+
-+#
-+# SCSI device support
-+#
-+# CONFIG_SCSI_DMA is not set
-+# CONFIG_SCSI_NETLINK is not set
-+# CONFIG_NETDEVICES is not set
-+# CONFIG_ISDN is not set
-+# CONFIG_PHONE is not set
++ for (i = 0; i < nr_blocks; i++) {
++ p = dma_pool_alloc(dmac->lli_pool, GFP_KERNEL,
++ &block[i].lli_dma_addr);
++ block[i].lli_vaddr = p;
++ if (unlikely(!p))
++ goto fail;
++ }
+
-+#
-+# Input device support
-+#
-+# CONFIG_INPUT is not set
++ return block;
+
-+#
-+# Hardware I/O ports
-+#
-+# CONFIG_SERIO is not set
-+# CONFIG_GAMEPORT is not set
++fail:
++ for (i = 0; i < nr_blocks; i++) {
++ if (!block[i].lli_vaddr)
++ break;
++ dma_pool_free(dmac->lli_pool, block[i].lli_vaddr,
++ block[i].lli_dma_addr);
++ }
++ kfree(block);
++ return NULL;
++}
+
-+#
-+# Character devices
-+#
-+# CONFIG_VT is not set
-+# CONFIG_SERIAL_NONSTANDARD is not set
++static void cleanup_channel(struct dw_dma_controller *dmac,
++ struct dw_dma_channel *chan)
++{
++ unsigned int i;
+
-+#
-+# Serial drivers
-+#
-+# CONFIG_SERIAL_8250 is not set
++ if (chan->nr_blocks > 1) {
++ for (i = 0; i < chan->nr_blocks; i++)
++ dma_pool_free(dmac->lli_pool, chan->block[i].lli_vaddr,
++ chan->block[i].lli_dma_addr);
++ kfree(chan->block);
++ }
+
-+#
-+# Non-8250 serial port support
-+#
-+CONFIG_SERIAL_ATMEL=y
-+CONFIG_SERIAL_ATMEL_CONSOLE=y
-+# CONFIG_SERIAL_ATMEL_PDC is not set
-+# CONFIG_SERIAL_ATMEL_TTYAT is not set
-+CONFIG_SERIAL_CORE=y
-+CONFIG_SERIAL_CORE_CONSOLE=y
-+CONFIG_UNIX98_PTYS=y
-+# CONFIG_LEGACY_PTYS is not set
-+# CONFIG_IPMI_HANDLER is not set
-+# CONFIG_HW_RANDOM is not set
-+# CONFIG_RTC is not set
-+# CONFIG_GEN_RTC is not set
-+# CONFIG_R3964 is not set
-+# CONFIG_TCG_TPM is not set
-+# CONFIG_I2C is not set
++ chan->state = CH_STATE_ALLOCATED;
++}
+
-+#
-+# SPI support
-+#
-+CONFIG_SPI=y
-+CONFIG_SPI_MASTER=y
++static int dmac_prepare_request_sg(struct dma_controller *_dmac,
++ struct dma_request_sg *req)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++ struct dw_dma_channel *chan;
++ unsigned long ctlhi, ctllo, cfghi, cfglo;
++ unsigned long block_size;
++ unsigned int nr_blocks;
++ int ret, i, direction;
++ unsigned long flags;
+
-+#
-+# SPI Master Controller Drivers
-+#
-+CONFIG_SPI_ATMEL=y
-+# CONFIG_SPI_BITBANG is not set
++ spin_lock_irqsave(&dmac->lock, flags);
+
-+#
-+# SPI Protocol Masters
-+#
-+# CONFIG_SPI_AT25 is not set
-+# CONFIG_SPI_SPIDEV is not set
-+# CONFIG_SPI_TLE62X0 is not set
-+# CONFIG_W1 is not set
-+# CONFIG_POWER_SUPPLY is not set
-+# CONFIG_HWMON is not set
-+CONFIG_WATCHDOG=y
-+# CONFIG_WATCHDOG_NOWAYOUT is not set
++ ret = -EINVAL;
++ if (req->req.channel >= DMAC_NR_CHANNELS
++ || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
++ || req->block_size > DMAC_MAX_BLOCKSIZE) {
++ spin_unlock_irqrestore(&dmac->lock, flags);
++ return -EINVAL;
++ }
+
-+#
-+# Watchdog Device Drivers
-+#
-+# CONFIG_SOFT_WATCHDOG is not set
-+CONFIG_AT32AP700X_WDT=y
++ chan = &dmac->channel[req->req.channel];
++ chan->state = CH_STATE_BUSY;
++ chan->req_sg = req;
++ chan->is_cyclic = 0;
+
-+#
-+# Sonics Silicon Backplane
-+#
-+CONFIG_SSB_POSSIBLE=y
-+# CONFIG_SSB is not set
++ /*
++ * We have marked the channel as busy, so no need to keep the
++ * lock as long as we only touch the channel-specific
++ * registers
++ */
++ spin_unlock_irqrestore(&dmac->lock, flags);
+
-+#
-+# Multifunction device drivers
-+#
-+# CONFIG_MFD_SM501 is not set
++ /*
++ * There may be limitations in the driver and/or the DMA
++ * controller that prevents us from sending a whole
++ * scatterlist item in one go. Taking this into account,
++ * calculate the number of block transfers we need to set up.
++ *
++ * FIXME: Let the peripheral driver know about the maximum
++ * block size we support. We really don't want to use a
++ * different block size than what was suggested by the
++ * peripheral.
++ *
++ * Each block will get its own Linked List Item (LLI) below.
++ */
++ block_size = req->block_size;
++ nr_blocks = req->nr_blocks;
++ pr_debug("block_size %lu, nr_blocks %u nr_sg = %u\n",
++ block_size, nr_blocks, req->nr_sg);
+
-+#
-+# Multimedia devices
-+#
-+# CONFIG_VIDEO_DEV is not set
-+# CONFIG_DVB_CORE is not set
-+# CONFIG_DAB is not set
++ BUG_ON(nr_blocks == 0);
++ chan->nr_blocks = nr_blocks;
+
-+#
-+# Graphics support
-+#
-+# CONFIG_VGASTATE is not set
-+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-+CONFIG_FB=y
-+# CONFIG_FIRMWARE_EDID is not set
-+# CONFIG_FB_DDC is not set
-+CONFIG_FB_CFB_FILLRECT=y
-+CONFIG_FB_CFB_COPYAREA=y
-+CONFIG_FB_CFB_IMAGEBLIT=y
-+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-+# CONFIG_FB_SYS_FILLRECT is not set
-+# CONFIG_FB_SYS_COPYAREA is not set
-+# CONFIG_FB_SYS_IMAGEBLIT is not set
-+# CONFIG_FB_SYS_FOPS is not set
-+CONFIG_FB_DEFERRED_IO=y
-+# CONFIG_FB_SVGALIB is not set
-+# CONFIG_FB_MACMODES is not set
-+# CONFIG_FB_BACKLIGHT is not set
-+# CONFIG_FB_MODE_HELPERS is not set
-+# CONFIG_FB_TILEBLITTING is not set
++ ret = -EINVAL;
++ cfglo = cfghi = 0;
++ switch (req->direction) {
++ case DMA_DIR_MEM_TO_PERIPH:
++ direction = DMA_TO_DEVICE;
++ cfghi = req->periph_id << (43 - 32);
++ break;
+
-+#
-+# Frame buffer hardware drivers
-+#
-+# CONFIG_FB_S1D13XXX is not set
-+CONFIG_FB_ATMEL=y
-+# CONFIG_FB_VIRTUAL is not set
-+CONFIG_BACKLIGHT_LCD_SUPPORT=y
-+CONFIG_LCD_CLASS_DEVICE=y
-+CONFIG_LCD_LTV350QV=y
-+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
++ case DMA_DIR_PERIPH_TO_MEM:
++ direction = DMA_FROM_DEVICE;
++ cfghi = req->periph_id << (39 - 32);
++ break;
++ default:
++ goto out_unclaim_channel;
++ }
+
-+#
-+# Display device support
-+#
-+# CONFIG_DISPLAY_SUPPORT is not set
-+# CONFIG_LOGO is not set
++ chan->direction = direction;
+
-+#
-+# Sound
-+#
-+# CONFIG_SOUND is not set
-+CONFIG_USB_SUPPORT=y
-+# CONFIG_USB_ARCH_HAS_HCD is not set
-+# CONFIG_USB_ARCH_HAS_OHCI is not set
-+# CONFIG_USB_ARCH_HAS_EHCI is not set
++ dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
++ dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
+
-+#
-+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-+#
++ ctlhi = block_size >> req->width;
++ ctllo = ((req->direction << 20)
++ // | (1 << 14) | (1 << 11) // source/dest burst trans len
++ | (req->width << 4) | (req->width << 1)
++ | (1 << 0)); // interrupt enable
+
-+#
-+# USB Gadget Support
-+#
-+CONFIG_USB_GADGET=y
-+# CONFIG_USB_GADGET_DEBUG_FILES is not set
-+CONFIG_USB_GADGET_SELECTED=y
-+# CONFIG_USB_GADGET_AMD5536UDC is not set
-+CONFIG_USB_GADGET_ATMEL_USBA=y
-+CONFIG_USB_ATMEL_USBA=y
-+# CONFIG_USB_GADGET_FSL_USB2 is not set
-+# CONFIG_USB_GADGET_NET2280 is not set
-+# CONFIG_USB_GADGET_PXA2XX is not set
-+# CONFIG_USB_GADGET_M66592 is not set
-+# CONFIG_USB_GADGET_GOKU is not set
-+# CONFIG_USB_GADGET_LH7A40X is not set
-+# CONFIG_USB_GADGET_OMAP is not set
-+# CONFIG_USB_GADGET_S3C2410 is not set
-+# CONFIG_USB_GADGET_AT91 is not set
-+# CONFIG_USB_GADGET_DUMMY_HCD is not set
-+CONFIG_USB_GADGET_DUALSPEED=y
-+# CONFIG_USB_ZERO is not set
-+CONFIG_USB_ETH=y
-+# CONFIG_USB_ETH_RNDIS is not set
-+# CONFIG_USB_GADGETFS is not set
-+# CONFIG_USB_FILE_STORAGE is not set
-+# CONFIG_USB_G_SERIAL is not set
-+# CONFIG_USB_MIDI_GADGET is not set
-+# CONFIG_MMC is not set
-+# CONFIG_NEW_LEDS is not set
-+CONFIG_RTC_LIB=y
-+CONFIG_RTC_CLASS=y
-+CONFIG_RTC_HCTOSYS=y
-+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-+# CONFIG_RTC_DEBUG is not set
++ if (nr_blocks == 1) {
++ /* Only one block: No need to use block chaining */
++ if (direction == DMA_TO_DEVICE) {
++ dmac_chan_writel_lo(dmac, req->req.channel, SAR,
++ req->sg->dma_address);
++ dmac_chan_writel_lo(dmac, req->req.channel, DAR,
++ req->data_reg);
++ ctllo |= 2 << 7; // no dst increment
++ } else {
++ dmac_chan_writel_lo(dmac, req->req.channel, SAR,
++ req->data_reg);
++ dmac_chan_writel_lo(dmac, req->req.channel, DAR,
++ req->sg->dma_address);
++ ctllo |= 2 << 9; // no src increment
++ }
++ dmac_chan_writel_lo(dmac, req->req.channel, CTL, ctllo);
++ dmac_chan_writel_hi(dmac, req->req.channel, CTL, ctlhi);
++ pr_debug("ctl hi:lo 0x%lx:%lx\n", ctlhi, ctllo);
++ } else {
++ struct dw_dma_lli *lli, *lli_prev = NULL;
++ int j = 0, offset = 0;
+
-+#
-+# RTC interfaces
-+#
-+CONFIG_RTC_INTF_SYSFS=y
-+# CONFIG_RTC_INTF_PROC is not set
-+CONFIG_RTC_INTF_DEV=y
-+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-+# CONFIG_RTC_DRV_TEST is not set
++ ret = -ENOMEM;
++ chan->block = allocate_blocks(dmac, nr_blocks);
++ if (!chan->block)
++ goto out_unclaim_channel;
+
-+#
-+# SPI RTC drivers
-+#
-+# CONFIG_RTC_DRV_RS5C348 is not set
-+# CONFIG_RTC_DRV_MAX6902 is not set
++ if (direction == DMA_TO_DEVICE)
++ ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
++ else
++ ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
+
-+#
-+# Platform RTC drivers
-+#
-+# CONFIG_RTC_DRV_DS1553 is not set
-+# CONFIG_RTC_DRV_STK17TA8 is not set
-+# CONFIG_RTC_DRV_DS1742 is not set
-+# CONFIG_RTC_DRV_M48T86 is not set
-+# CONFIG_RTC_DRV_M48T59 is not set
-+# CONFIG_RTC_DRV_V3020 is not set
++ /*
++ * Map scatterlist items to blocks. One scatterlist
++ * item may need more than one block for the reasons
++ * mentioned above.
++ */
++ for (i = 0; i < nr_blocks; i++) {
++ lli = chan->block[i].lli_vaddr;
++ if (lli_prev) {
++ lli_prev->llp = chan->block[i].lli_dma_addr;
++ pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr,
++ lli_prev->sar, lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi);
++ }
++ lli->llp = 0;
++ lli->ctllo = ctllo;
++ lli->ctlhi = ctlhi;
++ if (direction == DMA_TO_DEVICE) {
++ lli->sar = req->sg[j].dma_address + offset;
++ lli->dar = req->data_reg;
++ } else {
++ lli->sar = req->data_reg;
++ lli->dar = req->sg[j].dma_address + offset;
++ }
++ lli_prev = lli;
+
-+#
-+# on-CPU RTC drivers
-+#
-+CONFIG_RTC_DRV_AT32AP700X=y
++ offset += block_size;
++ if (offset > req->sg[j].length) {
++ j++;
++ offset = 0;
++ }
++ }
+
-+#
-+# Userspace I/O
-+#
-+# CONFIG_UIO is not set
++ pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr, lli_prev->sar,
++ lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi);
+
-+#
-+# File systems
-+#
-+# CONFIG_INOTIFY is not set
-+# CONFIG_QUOTA is not set
-+# CONFIG_DNOTIFY is not set
-+# CONFIG_AUTOFS_FS is not set
-+# CONFIG_AUTOFS4_FS is not set
-+# CONFIG_FUSE_FS is not set
++ /*
++ * SAR, DAR and CTL are initialized from the LLI. We
++ * only have to enable the LLI bits in CTL.
++ */
++ dmac_chan_writel_hi(dmac, req->req.channel, CTL, 0);
++ dmac_chan_writel_lo(dmac, req->req.channel, LLP,
++ chan->block[0].lli_dma_addr);
++ dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
++ }
+
-+#
-+# Pseudo filesystems
-+#
-+CONFIG_PROC_FS=y
-+CONFIG_PROC_KCORE=y
-+CONFIG_PROC_SYSCTL=y
-+CONFIG_SYSFS=y
-+CONFIG_TMPFS=y
-+# CONFIG_TMPFS_POSIX_ACL is not set
-+# CONFIG_HUGETLB_PAGE is not set
-+# CONFIG_CONFIGFS_FS is not set
++ set_channel_bit(dmac, MASK_XFER, req->req.channel);
++ set_channel_bit(dmac, MASK_ERROR, req->req.channel);
++ if (req->req.block_complete)
++ set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
++ else
++ clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
+
-+#
-+# Miscellaneous filesystems
-+#
-+CONFIG_JFFS2_FS=y
-+CONFIG_JFFS2_FS_DEBUG=0
-+# CONFIG_JFFS2_FS_WRITEBUFFER is not set
-+# CONFIG_JFFS2_SUMMARY is not set
-+# CONFIG_JFFS2_FS_XATTR is not set
-+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-+CONFIG_JFFS2_ZLIB=y
-+# CONFIG_JFFS2_LZO is not set
-+CONFIG_JFFS2_RTIME=y
-+# CONFIG_JFFS2_RUBIN is not set
-+# CONFIG_NETWORK_FILESYSTEMS is not set
-+# CONFIG_NLS is not set
-+# CONFIG_DLM is not set
-+# CONFIG_INSTRUMENTATION is not set
++ return 0;
+
-+#
-+# Kernel hacking
-+#
-+# CONFIG_PRINTK_TIME is not set
-+CONFIG_ENABLE_WARN_DEPRECATED=y
-+CONFIG_ENABLE_MUST_CHECK=y
-+CONFIG_MAGIC_SYSRQ=y
-+# CONFIG_UNUSED_SYMBOLS is not set
-+# CONFIG_DEBUG_FS is not set
-+# CONFIG_HEADERS_CHECK is not set
-+# CONFIG_DEBUG_KERNEL is not set
-+# CONFIG_DEBUG_BUGVERBOSE is not set
-+# CONFIG_SAMPLES is not set
++out_unclaim_channel:
++ chan->state = CH_STATE_ALLOCATED;
++ return ret;
++}
+
-+#
-+# Security options
-+#
-+# CONFIG_KEYS is not set
-+# CONFIG_SECURITY is not set
-+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-+# CONFIG_CRYPTO is not set
++static int dmac_prepare_request_cyclic(struct dma_controller *_dmac,
++ struct dma_request_cyclic *req)
++{
++ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
++ struct dw_dma_channel *chan;
++ unsigned long ctlhi, ctllo, cfghi, cfglo;
++ unsigned long block_size;
++ int ret, i, direction;
++ unsigned long flags;
+
-+#
-+# Library routines
-+#
-+CONFIG_BITREVERSE=y
-+# CONFIG_CRC_CCITT is not set
-+# CONFIG_CRC16 is not set
-+# CONFIG_CRC_ITU_T is not set
-+CONFIG_CRC32=y
-+# CONFIG_CRC7 is not set
-+# CONFIG_LIBCRC32C is not set
-+CONFIG_ZLIB_INFLATE=y
-+CONFIG_ZLIB_DEFLATE=y
-+CONFIG_HAS_IOMEM=y
-+CONFIG_HAS_IOPORT=y
-+CONFIG_HAS_DMA=y
---- /dev/null
-+++ b/arch/avr32/drivers/dw-dmac.c
-@@ -0,0 +1,761 @@
-+/*
-+ * Driver for the Synopsys DesignWare DMA Controller
-+ *
-+ * Copyright (C) 2005-2006 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dmapool.h>
-+#include <linux/init.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
++ spin_lock_irqsave(&dmac->lock, flags);
+
-+#include <asm/dma-controller.h>
-+#include <asm/io.h>
++ block_size = (req->buffer_size/req->periods) >> req->width;
+
-+#include "dw-dmac.h"
++ ret = -EINVAL;
++ if (req->req.channel >= DMAC_NR_CHANNELS
++ || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
++ || (req->periods == 0)
++ || block_size > DMAC_MAX_BLOCKSIZE) {
++ spin_unlock_irqrestore(&dmac->lock, flags);
++ return -EINVAL;
++ }
+
-+#define DMAC_NR_CHANNELS 3
-+#define DMAC_MAX_BLOCKSIZE 4095
++ chan = &dmac->channel[req->req.channel];
++ chan->state = CH_STATE_BUSY;
++ chan->is_cyclic = 1;
++ chan->req_cyclic = req;
+
-+enum {
-+ CH_STATE_FREE = 0,
-+ CH_STATE_ALLOCATED,
-+ CH_STATE_BUSY,
-+};
++ /*
++ * We have marked the channel as busy, so no need to keep the
++ * lock as long as we only touch the channel-specific
++ * registers
++ */
++ spin_unlock_irqrestore(&dmac->lock, flags);
+
-+struct dw_dma_lli {
-+ dma_addr_t sar;
-+ dma_addr_t dar;
-+ dma_addr_t llp;
-+ u32 ctllo;
-+ u32 ctlhi;
-+ u32 sstat;
-+ u32 dstat;
-+};
++ /*
++ Setup
++ */
++ BUG_ON(req->buffer_size % req->periods);
++ /* printk(KERN_INFO "block_size = %lu, periods = %u\n", block_size, req->periods); */
+
-+struct dw_dma_block {
-+ struct dw_dma_lli *lli_vaddr;
-+ dma_addr_t lli_dma_addr;
-+};
-+
-+struct dw_dma_channel {
-+ unsigned int state;
-+ int is_cyclic;
-+ struct dma_request_sg *req_sg;
-+ struct dma_request_cyclic *req_cyclic;
-+ unsigned int nr_blocks;
-+ int direction;
-+ struct dw_dma_block *block;
-+};
-+
-+struct dw_dma_controller {
-+ spinlock_t lock;
-+ void * __iomem regs;
-+ struct dma_pool *lli_pool;
-+ struct clk *hclk;
-+ struct dma_controller dma;
-+ struct dw_dma_channel channel[DMAC_NR_CHANNELS];
-+};
-+#define to_dw_dmac(dmac) container_of(dmac, struct dw_dma_controller, dma)
-+
-+#define dmac_writel_hi(dmac, reg, value) \
-+ __raw_writel((value), (dmac)->regs + DW_DMAC_##reg + 4)
-+#define dmac_readl_hi(dmac, reg) \
-+ __raw_readl((dmac)->regs + DW_DMAC_##reg + 4)
-+#define dmac_writel_lo(dmac, reg, value) \
-+ __raw_writel((value), (dmac)->regs + DW_DMAC_##reg)
-+#define dmac_readl_lo(dmac, reg) \
-+ __raw_readl((dmac)->regs + DW_DMAC_##reg)
-+#define dmac_chan_writel_hi(dmac, chan, reg, value) \
-+ __raw_writel((value), ((dmac)->regs + 0x58 * (chan) \
-+ + DW_DMAC_CHAN_##reg + 4))
-+#define dmac_chan_readl_hi(dmac, chan, reg) \
-+ __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg + 4)
-+#define dmac_chan_writel_lo(dmac, chan, reg, value) \
-+ __raw_writel((value), (dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
-+#define dmac_chan_readl_lo(dmac, chan, reg) \
-+ __raw_readl((dmac)->regs + 0x58 * (chan) + DW_DMAC_CHAN_##reg)
-+#define set_channel_bit(dmac, reg, chan) \
-+ dmac_writel_lo(dmac, reg, (1 << (chan)) | (1 << ((chan) + 8)))
-+#define clear_channel_bit(dmac, reg, chan) \
-+ dmac_writel_lo(dmac, reg, (0 << (chan)) | (1 << ((chan) + 8)))
-+
-+static int dmac_alloc_channel(struct dma_controller *_dmac)
-+{
-+ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
-+ struct dw_dma_channel *chan;
-+ unsigned long flags;
-+ int i;
-+
-+ spin_lock_irqsave(&dmac->lock, flags);
-+ for (i = 0; i < DMAC_NR_CHANNELS; i++)
-+ if (dmac->channel[i].state == CH_STATE_FREE)
-+ break;
-+
-+ if (i < DMAC_NR_CHANNELS) {
-+ chan = &dmac->channel[i];
-+ chan->state = CH_STATE_ALLOCATED;
-+ } else {
-+ i = -EBUSY;
-+ }
-+
-+ spin_unlock_irqrestore(&dmac->lock, flags);
-+
-+ return i;
-+}
-+
-+static void dmac_release_channel(struct dma_controller *_dmac, int channel)
-+{
-+ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
-+
-+ BUG_ON(channel >= DMAC_NR_CHANNELS
-+ || dmac->channel[channel].state != CH_STATE_ALLOCATED);
-+
-+ dmac->channel[channel].state = CH_STATE_FREE;
-+}
-+
-+static struct dw_dma_block *allocate_blocks(struct dw_dma_controller *dmac,
-+ unsigned int nr_blocks)
-+{
-+ struct dw_dma_block *block;
-+ void *p;
-+ unsigned int i;
-+
-+ block = kmalloc(nr_blocks * sizeof(*block),
-+ GFP_KERNEL);
-+ if (unlikely(!block))
-+ return NULL;
-+
-+ for (i = 0; i < nr_blocks; i++) {
-+ p = dma_pool_alloc(dmac->lli_pool, GFP_KERNEL,
-+ &block[i].lli_dma_addr);
-+ block[i].lli_vaddr = p;
-+ if (unlikely(!p))
-+ goto fail;
-+ }
-+
-+ return block;
-+
-+fail:
-+ for (i = 0; i < nr_blocks; i++) {
-+ if (!block[i].lli_vaddr)
-+ break;
-+ dma_pool_free(dmac->lli_pool, block[i].lli_vaddr,
-+ block[i].lli_dma_addr);
-+ }
-+ kfree(block);
-+ return NULL;
-+}
-+
-+static void cleanup_channel(struct dw_dma_controller *dmac,
-+ struct dw_dma_channel *chan)
-+{
-+ unsigned int i;
-+
-+ if (chan->nr_blocks > 1) {
-+ for (i = 0; i < chan->nr_blocks; i++)
-+ dma_pool_free(dmac->lli_pool, chan->block[i].lli_vaddr,
-+ chan->block[i].lli_dma_addr);
-+ kfree(chan->block);
-+ }
-+
-+ chan->state = CH_STATE_ALLOCATED;
-+}
-+
-+static int dmac_prepare_request_sg(struct dma_controller *_dmac,
-+ struct dma_request_sg *req)
-+{
-+ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
-+ struct dw_dma_channel *chan;
-+ unsigned long ctlhi, ctllo, cfghi, cfglo;
-+ unsigned long block_size;
-+ unsigned int nr_blocks;
-+ int ret, i, direction;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&dmac->lock, flags);
-+
-+ ret = -EINVAL;
-+ if (req->req.channel >= DMAC_NR_CHANNELS
-+ || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
-+ || req->block_size > DMAC_MAX_BLOCKSIZE) {
-+ spin_unlock_irqrestore(&dmac->lock, flags);
-+ return -EINVAL;
-+ }
-+
-+ chan = &dmac->channel[req->req.channel];
-+ chan->state = CH_STATE_BUSY;
-+ chan->req_sg = req;
-+ chan->is_cyclic = 0;
-+
-+ /*
-+ * We have marked the channel as busy, so no need to keep the
-+ * lock as long as we only touch the channel-specific
-+ * registers
-+ */
-+ spin_unlock_irqrestore(&dmac->lock, flags);
-+
-+ /*
-+ * There may be limitations in the driver and/or the DMA
-+ * controller that prevents us from sending a whole
-+ * scatterlist item in one go. Taking this into account,
-+ * calculate the number of block transfers we need to set up.
-+ *
-+ * FIXME: Let the peripheral driver know about the maximum
-+ * block size we support. We really don't want to use a
-+ * different block size than what was suggested by the
-+ * peripheral.
-+ *
-+ * Each block will get its own Linked List Item (LLI) below.
-+ */
-+ block_size = req->block_size;
-+ nr_blocks = req->nr_blocks;
-+ pr_debug("block_size %lu, nr_blocks %u nr_sg = %u\n",
-+ block_size, nr_blocks, req->nr_sg);
-+
-+ BUG_ON(nr_blocks == 0);
-+ chan->nr_blocks = nr_blocks;
++ chan->nr_blocks = req->periods;
+
+ ret = -EINVAL;
+ cfglo = cfghi = 0;
+ dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
+ dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
+
-+ ctlhi = block_size >> req->width;
++ ctlhi = block_size;
+ ctllo = ((req->direction << 20)
-+ // | (1 << 14) | (1 << 11) // source/dest burst trans len
+ | (req->width << 4) | (req->width << 1)
+ | (1 << 0)); // interrupt enable
+
-+ if (nr_blocks == 1) {
-+ /* Only one block: No need to use block chaining */
-+ if (direction == DMA_TO_DEVICE) {
-+ dmac_chan_writel_lo(dmac, req->req.channel, SAR,
-+ req->sg->dma_address);
-+ dmac_chan_writel_lo(dmac, req->req.channel, DAR,
-+ req->data_reg);
-+ ctllo |= 2 << 7; // no dst increment
-+ } else {
-+ dmac_chan_writel_lo(dmac, req->req.channel, SAR,
-+ req->data_reg);
-+ dmac_chan_writel_lo(dmac, req->req.channel, DAR,
-+ req->sg->dma_address);
-+ ctllo |= 2 << 9; // no src increment
-+ }
-+ dmac_chan_writel_lo(dmac, req->req.channel, CTL, ctllo);
-+ dmac_chan_writel_hi(dmac, req->req.channel, CTL, ctlhi);
-+ pr_debug("ctl hi:lo 0x%lx:%lx\n", ctlhi, ctllo);
-+ } else {
-+ struct dw_dma_lli *lli, *lli_prev = NULL;
-+ int j = 0, offset = 0;
++ {
++ struct dw_dma_lli *lli = NULL, *lli_prev = NULL;
+
+ ret = -ENOMEM;
-+ chan->block = allocate_blocks(dmac, nr_blocks);
++ chan->block = allocate_blocks(dmac, req->periods);
+ if (!chan->block)
+ goto out_unclaim_channel;
+
+ ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
+
+ /*
-+ * Map scatterlist items to blocks. One scatterlist
-+ * item may need more than one block for the reasons
-+ * mentioned above.
++ * Set up a linked list items where each period gets
++ * an item. The linked list item for the last period
++ * points back to the star of the buffer making a
++ * cyclic buffer.
+ */
-+ for (i = 0; i < nr_blocks; i++) {
++ for (i = 0; i < req->periods; i++) {
+ lli = chan->block[i].lli_vaddr;
+ if (lli_prev) {
+ lli_prev->llp = chan->block[i].lli_dma_addr;
-+ pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
-+ i - 1, chan->block[i - 1].lli_vaddr,
-+ chan->block[i - 1].lli_dma_addr,
-+ lli_prev->sar, lli_prev->dar, lli_prev->llp,
-+ lli_prev->ctllo, lli_prev->ctlhi);
++ /* printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr,
++ lli_prev->sar, lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi);*/
+ }
+ lli->llp = 0;
+ lli->ctllo = ctllo;
+ lli->ctlhi = ctlhi;
+ if (direction == DMA_TO_DEVICE) {
-+ lli->sar = req->sg[j].dma_address + offset;
++ lli->sar = req->buffer_start + i*(block_size << req->width);
+ lli->dar = req->data_reg;
+ } else {
+ lli->sar = req->data_reg;
-+ lli->dar = req->sg[j].dma_address + offset;
++ lli->dar = req->buffer_start + i*(block_size << req->width);
+ }
+ lli_prev = lli;
-+
-+ offset += block_size;
-+ if (offset > req->sg[j].length) {
-+ j++;
-+ offset = 0;
-+ }
+ }
++ lli->llp = chan->block[0].lli_dma_addr;
+
-+ pr_debug("lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
-+ i - 1, chan->block[i - 1].lli_vaddr,
-+ chan->block[i - 1].lli_dma_addr, lli_prev->sar,
-+ lli_prev->dar, lli_prev->llp,
-+ lli_prev->ctllo, lli_prev->ctlhi);
++ /*printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
++ i - 1, chan->block[i - 1].lli_vaddr,
++ chan->block[i - 1].lli_dma_addr, lli_prev->sar,
++ lli_prev->dar, lli_prev->llp,
++ lli_prev->ctllo, lli_prev->ctlhi); */
+
+ /*
+ * SAR, DAR and CTL are initialized from the LLI. We
+ * only have to enable the LLI bits in CTL.
+ */
-+ dmac_chan_writel_hi(dmac, req->req.channel, CTL, 0);
+ dmac_chan_writel_lo(dmac, req->req.channel, LLP,
+ chan->block[0].lli_dma_addr);
+ dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
+ }
+
-+ set_channel_bit(dmac, MASK_XFER, req->req.channel);
++ clear_channel_bit(dmac, MASK_XFER, req->req.channel);
+ set_channel_bit(dmac, MASK_ERROR, req->req.channel);
+ if (req->req.block_complete)
+ set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
+ return ret;
+}
+
-+static int dmac_prepare_request_cyclic(struct dma_controller *_dmac,
-+ struct dma_request_cyclic *req)
++static int dmac_start_request(struct dma_controller *_dmac,
++ unsigned int channel)
+{
+ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
-+ struct dw_dma_channel *chan;
-+ unsigned long ctlhi, ctllo, cfghi, cfglo;
-+ unsigned long block_size;
-+ int ret, i, direction;
-+ unsigned long flags;
+
-+ spin_lock_irqsave(&dmac->lock, flags);
-+
-+ block_size = (req->buffer_size/req->periods) >> req->width;
-+
-+ ret = -EINVAL;
-+ if (req->req.channel >= DMAC_NR_CHANNELS
-+ || dmac->channel[req->req.channel].state != CH_STATE_ALLOCATED
-+ || (req->periods == 0)
-+ || block_size > DMAC_MAX_BLOCKSIZE) {
-+ spin_unlock_irqrestore(&dmac->lock, flags);
-+ return -EINVAL;
-+ }
-+
-+ chan = &dmac->channel[req->req.channel];
-+ chan->state = CH_STATE_BUSY;
-+ chan->is_cyclic = 1;
-+ chan->req_cyclic = req;
-+
-+ /*
-+ * We have marked the channel as busy, so no need to keep the
-+ * lock as long as we only touch the channel-specific
-+ * registers
-+ */
-+ spin_unlock_irqrestore(&dmac->lock, flags);
-+
-+ /*
-+ Setup
-+ */
-+ BUG_ON(req->buffer_size % req->periods);
-+ /* printk(KERN_INFO "block_size = %lu, periods = %u\n", block_size, req->periods); */
-+
-+ chan->nr_blocks = req->periods;
-+
-+ ret = -EINVAL;
-+ cfglo = cfghi = 0;
-+ switch (req->direction) {
-+ case DMA_DIR_MEM_TO_PERIPH:
-+ direction = DMA_TO_DEVICE;
-+ cfghi = req->periph_id << (43 - 32);
-+ break;
-+
-+ case DMA_DIR_PERIPH_TO_MEM:
-+ direction = DMA_FROM_DEVICE;
-+ cfghi = req->periph_id << (39 - 32);
-+ break;
-+ default:
-+ goto out_unclaim_channel;
-+ }
-+
-+ chan->direction = direction;
-+
-+ dmac_chan_writel_hi(dmac, req->req.channel, CFG, cfghi);
-+ dmac_chan_writel_lo(dmac, req->req.channel, CFG, cfglo);
-+
-+ ctlhi = block_size;
-+ ctllo = ((req->direction << 20)
-+ | (req->width << 4) | (req->width << 1)
-+ | (1 << 0)); // interrupt enable
-+
-+ {
-+ struct dw_dma_lli *lli = NULL, *lli_prev = NULL;
-+
-+ ret = -ENOMEM;
-+ chan->block = allocate_blocks(dmac, req->periods);
-+ if (!chan->block)
-+ goto out_unclaim_channel;
-+
-+ if (direction == DMA_TO_DEVICE)
-+ ctllo |= 1 << 28 | 1 << 27 | 2 << 7;
-+ else
-+ ctllo |= 1 << 28 | 1 << 27 | 2 << 9;
-+
-+ /*
-+ * Set up a linked list items where each period gets
-+ * an item. The linked list item for the last period
-+ * points back to the star of the buffer making a
-+ * cyclic buffer.
-+ */
-+ for (i = 0; i < req->periods; i++) {
-+ lli = chan->block[i].lli_vaddr;
-+ if (lli_prev) {
-+ lli_prev->llp = chan->block[i].lli_dma_addr;
-+ /* printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
-+ i - 1, chan->block[i - 1].lli_vaddr,
-+ chan->block[i - 1].lli_dma_addr,
-+ lli_prev->sar, lli_prev->dar, lli_prev->llp,
-+ lli_prev->ctllo, lli_prev->ctlhi);*/
-+ }
-+ lli->llp = 0;
-+ lli->ctllo = ctllo;
-+ lli->ctlhi = ctlhi;
-+ if (direction == DMA_TO_DEVICE) {
-+ lli->sar = req->buffer_start + i*(block_size << req->width);
-+ lli->dar = req->data_reg;
-+ } else {
-+ lli->sar = req->data_reg;
-+ lli->dar = req->buffer_start + i*(block_size << req->width);
-+ }
-+ lli_prev = lli;
-+ }
-+ lli->llp = chan->block[0].lli_dma_addr;
-+
-+ /*printk(KERN_INFO "lli[%d] (0x%p/0x%x): 0x%x 0x%x 0x%x 0x%x 0x%x\n",
-+ i - 1, chan->block[i - 1].lli_vaddr,
-+ chan->block[i - 1].lli_dma_addr, lli_prev->sar,
-+ lli_prev->dar, lli_prev->llp,
-+ lli_prev->ctllo, lli_prev->ctlhi); */
-+
-+ /*
-+ * SAR, DAR and CTL are initialized from the LLI. We
-+ * only have to enable the LLI bits in CTL.
-+ */
-+ dmac_chan_writel_lo(dmac, req->req.channel, LLP,
-+ chan->block[0].lli_dma_addr);
-+ dmac_chan_writel_lo(dmac, req->req.channel, CTL, 1 << 28 | 1 << 27);
-+ }
-+
-+ clear_channel_bit(dmac, MASK_XFER, req->req.channel);
-+ set_channel_bit(dmac, MASK_ERROR, req->req.channel);
-+ if (req->req.block_complete)
-+ set_channel_bit(dmac, MASK_BLOCK, req->req.channel);
-+ else
-+ clear_channel_bit(dmac, MASK_BLOCK, req->req.channel);
-+
-+ return 0;
-+
-+out_unclaim_channel:
-+ chan->state = CH_STATE_ALLOCATED;
-+ return ret;
-+}
-+
-+static int dmac_start_request(struct dma_controller *_dmac,
-+ unsigned int channel)
-+{
-+ struct dw_dma_controller *dmac = to_dw_dmac(_dmac);
-+
-+ BUG_ON(channel >= DMAC_NR_CHANNELS);
++ BUG_ON(channel >= DMAC_NR_CHANNELS);
+
+ set_channel_bit(dmac, CH_EN, channel);
+
+#define DW_DMAC_CHAN_DSR 0x050
+
+#endif /* __AVR32_DW_DMAC_H__ */
---- /dev/null
-+++ b/arch/avr32/drivers/Makefile
-@@ -0,0 +1 @@
-+obj-$(CONFIG_DW_DMAC) += dw-dmac.o
---- a/arch/avr32/Kconfig
-+++ b/arch/avr32/Kconfig
-@@ -45,6 +45,9 @@
- config GENERIC_TIME
- def_bool y
-
-+config GENERIC_CLOCKEVENTS
-+ def_bool y
+--- a/arch/avr32/kernel/Makefile
++++ b/arch/avr32/kernel/Makefile
+@@ -9,6 +9,7 @@
+ obj-y += setup.o traps.o semaphore.o ocd.o ptrace.o
+ obj-y += signal.o sys_avr32.o process.o time.o
+ obj-y += init_task.o switch_to.o cpu.o
++obj-y += dma-controller.o
+ obj-$(CONFIG_MODULES) += module.o avr32_ksyms.o
+ obj-$(CONFIG_KPROBES) += kprobes.o
+ obj-$(CONFIG_STACKTRACE) += stacktrace.o
+--- a/arch/avr32/kernel/avr32_ksyms.c
++++ b/arch/avr32/kernel/avr32_ksyms.c
+@@ -29,7 +29,9 @@
+ */
+ EXPORT_SYMBOL(memset);
+ EXPORT_SYMBOL(memcpy);
+
- config RWSEM_XCHGADD_ALGORITHM
- def_bool n
-
-@@ -54,6 +57,9 @@
- config ARCH_HAS_ILOG2_U64
- def_bool n
+ EXPORT_SYMBOL(clear_page);
++EXPORT_SYMBOL(copy_page);
-+config ARCH_SUPPORTS_OPROFILE
-+ def_bool y
+ /*
+ * Userspace access stuff.
+@@ -41,6 +43,8 @@
+ EXPORT_SYMBOL(__strncpy_from_user);
+ EXPORT_SYMBOL(clear_user);
+ EXPORT_SYMBOL(__clear_user);
++EXPORT_SYMBOL(strnlen_user);
+
- config GENERIC_HWEIGHT
- def_bool y
+ EXPORT_SYMBOL(csum_partial);
+ EXPORT_SYMBOL(csum_partial_copy_generic);
-@@ -68,6 +74,8 @@
+--- /dev/null
++++ b/arch/avr32/kernel/dma-controller.c
+@@ -0,0 +1,34 @@
++/*
++ * Preliminary DMA controller framework for AVR32
++ *
++ * Copyright (C) 2005-2006 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <asm/dma-controller.h>
++
++static LIST_HEAD(controllers);
++
++int register_dma_controller(struct dma_controller *dmac)
++{
++ static int next_id;
++
++ dmac->id = next_id++;
++ list_add_tail(&dmac->list, &controllers);
++
++ return 0;
++}
++EXPORT_SYMBOL(register_dma_controller);
++
++struct dma_controller *find_dma_controller(int id)
++{
++ struct dma_controller *dmac;
++
++ list_for_each_entry(dmac, &controllers, list)
++ if (dmac->id == id)
++ return dmac;
++ return NULL;
++}
++EXPORT_SYMBOL(find_dma_controller);
+--- a/arch/avr32/kernel/entry-avr32b.S
++++ b/arch/avr32/kernel/entry-avr32b.S
+@@ -74,50 +74,41 @@
+ .align 2
+ bral do_dtlb_modified
- menu "System Type and features"
+- /*
+- * r0 : PGD/PT/PTE
+- * r1 : Offending address
+- * r2 : Scratch register
+- * r3 : Cause (5, 12 or 13)
+- */
+ #define tlbmiss_save pushm r0-r3
+ #define tlbmiss_restore popm r0-r3
+
+- .section .tlbx.ex.text,"ax",@progbits
++ .org 0x50
+ .global itlb_miss
+ itlb_miss:
+ tlbmiss_save
+ rjmp tlb_miss_common
+
+- .section .tlbr.ex.text,"ax",@progbits
++ .org 0x60
+ dtlb_miss_read:
+ tlbmiss_save
+ rjmp tlb_miss_common
+
+- .section .tlbw.ex.text,"ax",@progbits
++ .org 0x70
+ dtlb_miss_write:
+ tlbmiss_save
+
+ .global tlb_miss_common
++ .align 2
+ tlb_miss_common:
+ mfsr r0, SYSREG_TLBEAR
+ mfsr r1, SYSREG_PTBR
+
+- /* Is it the vmalloc space? */
+- bld r0, 31
+- brcs handle_vmalloc_miss
+-
+- /* First level lookup */
++ /*
++ * First level lookup: The PGD contains virtual pointers to
++ * the second-level page tables, but they may be NULL if not
++ * present.
++ */
+ pgtbl_lookup:
+ lsr r2, r0, PGDIR_SHIFT
+ ld.w r3, r1[r2 << 2]
+ bfextu r1, r0, PAGE_SHIFT, PGDIR_SHIFT - PAGE_SHIFT
+- bld r3, _PAGE_BIT_PRESENT
+- brcc page_table_not_present
+-
+- /* Translate to virtual address in P1. */
+- andl r3, 0xf000
+- sbr r3, 31
++ cp.w r3, 0
++ breq page_table_not_present
+
+ /* Second level lookup */
+ ld.w r2, r3[r1 << 2]
+@@ -148,16 +139,55 @@
+ tlbmiss_restore
+ rete
+
+-handle_vmalloc_miss:
+- /* Simply do the lookup in init's page table */
++ /* The slow path of the TLB miss handler */
++ .align 2
++page_table_not_present:
++ /* Do we need to synchronize with swapper_pg_dir? */
++ bld r0, 31
++ brcs sync_with_swapper_pg_dir
++
++page_not_present:
++ tlbmiss_restore
++ sub sp, 4
++ stmts --sp, r0-lr
++ rcall save_full_context_ex
++ mfsr r12, SYSREG_ECR
++ mov r11, sp
++ rcall do_page_fault
++ rjmp ret_from_exception
++
++ .align 2
++sync_with_swapper_pg_dir:
++ /*
++ * If swapper_pg_dir contains a non-NULL second-level page
++ * table pointer, copy it into the current PGD. If not, we
++ * must handle it as a full-blown page fault.
++ *
++ * Jumping back to pgtbl_lookup causes an unnecessary lookup,
++ * but it is guaranteed to be a cache hit, it won't happen
++ * very often, and we absolutely do not want to sacrifice any
++ * performance in the fast path in order to improve this.
++ */
+ mov r1, lo(swapper_pg_dir)
+ orh r1, hi(swapper_pg_dir)
++ ld.w r3, r1[r2 << 2]
++ cp.w r3, 0
++ breq page_not_present
++ mfsr r1, SYSREG_PTBR
++ st.w r1[r2 << 2], r3
+ rjmp pgtbl_lookup
-+source "kernel/time/Kconfig"
++ /*
++ * We currently have two bytes left at this point until we
++ * crash into the system call handler...
++ *
++ * Don't worry, the assembler will let us know.
++ */
+
- config SUBARCH_AVR32B
- bool
- config MMU
-@@ -81,19 +89,23 @@
- select MMU
- select PERFORMANCE_COUNTERS
--choice
-- prompt "AVR32 CPU type"
-- default CPU_AT32AP7000
-+#
-+# CPU types
-+#
-
--config CPU_AT32AP7000
-- bool "AT32AP7000"
-+# AP7000 derivatives
-+config CPU_AT32AP700X
-+ bool
- select PLATFORM_AT32AP
--endchoice
--
--#
--# CPU Daughterboards for ATSTK1000
--config BOARD_ATSTK1002
-+config CPU_AT32AP7000
-+ bool
-+ select CPU_AT32AP700X
-+config CPU_AT32AP7001
-+ bool
-+ select CPU_AT32AP700X
-+config CPU_AT32AP7002
- bool
-+ select CPU_AT32AP700X
+ /* --- System Call --- */
+
+- .section .scall.text,"ax",@progbits
++ .org 0x100
+ system_call:
+ #ifdef CONFIG_PREEMPT
+ mask_interrupts
+@@ -266,18 +296,6 @@
+ brcc syscall_exit_cont
+ rjmp enter_monitor_mode
+
+- /* The slow path of the TLB miss handler */
+-page_table_not_present:
+-page_not_present:
+- tlbmiss_restore
+- sub sp, 4
+- stmts --sp, r0-lr
+- rcall save_full_context_ex
+- mfsr r12, SYSREG_ECR
+- mov r11, sp
+- rcall do_page_fault
+- rjmp ret_from_exception
+-
+ /* This function expects to find offending PC in SYSREG_RAR_EX */
+ .type save_full_context_ex, @function
+ .align 2
+@@ -741,26 +759,6 @@
- choice
- prompt "AVR32 board type"
-@@ -101,15 +113,18 @@
+ .section .irq.text,"ax",@progbits
- config BOARD_ATSTK1000
- bool "ATSTK1000 evaluation board"
-- select BOARD_ATSTK1002 if CPU_AT32AP7000
+-.global cpu_idle_sleep
+-cpu_idle_sleep:
+- mask_interrupts
+- get_thread_info r8
+- ld.w r9, r8[TI_flags]
+- bld r9, TIF_NEED_RESCHED
+- brcs cpu_idle_enable_int_and_exit
+- sbr r9, TIF_CPU_GOING_TO_SLEEP
+- st.w r8[TI_flags], r9
+- unmask_interrupts
+- sleep 0
+-cpu_idle_skip_sleep:
+- mask_interrupts
+- ld.w r9, r8[TI_flags]
+- cbr r9, TIF_CPU_GOING_TO_SLEEP
+- st.w r8[TI_flags], r9
+-cpu_idle_enable_int_and_exit:
+- unmask_interrupts
+- retal r12
+-
+ .global irq_level0
+ .global irq_level1
+ .global irq_level2
+--- a/arch/avr32/kernel/process.c
++++ b/arch/avr32/kernel/process.c
+@@ -18,11 +18,11 @@
+ #include <asm/sysreg.h>
+ #include <asm/ocd.h>
- config BOARD_ATNGW100
- bool "ATNGW100 Network Gateway"
-+ select CPU_AT32AP7000
- endchoice
-
- if BOARD_ATSTK1000
- source "arch/avr32/boards/atstk1000/Kconfig"
- endif
-+if BOARD_ATNGW100
-+source "arch/avr32/boards/atngw100/Kconfig"
-+endif
-
- choice
- prompt "Boot loader type"
-@@ -123,15 +138,15 @@
-
- config LOAD_ADDRESS
- hex
-- default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP7000=y
-+ default 0x10000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
-
- config ENTRY_ADDRESS
- hex
-- default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP7000=y
-+ default 0x90000000 if LOADER_U_BOOT=y && CPU_AT32AP700X=y
-
- config PHYS_OFFSET
- hex
-- default 0x10000000 if CPU_AT32AP7000=y
-+ default 0x10000000 if CPU_AT32AP700X=y
-
- source "kernel/Kconfig.preempt"
-
-@@ -163,6 +178,20 @@
- enabling Nexus-compliant debuggers to keep track of the PID of the
- currently executing task.
-
-+config NMI_DEBUGGING
-+ bool "NMI Debugging"
-+ default n
-+ help
-+ Say Y here and pass the nmi_debug command-line parameter to
-+ the kernel to turn on NMI debugging. Depending on the value
-+ of the nmi_debug option, various pieces of information will
-+ be dumped to the console when a Non-Maskable Interrupt
-+ happens.
-+
-+config DW_DMAC
-+ tristate "Synopsys DesignWare DMA Controller support"
-+ default y if CPU_AT32AP7000
++#include <asm/arch/pm.h>
+
- # FPU emulation goes here
+ void (*pm_power_off)(void) = NULL;
+ EXPORT_SYMBOL(pm_power_off);
- source "kernel/Kconfig.hz"
-@@ -219,6 +248,8 @@
+-extern void cpu_idle_sleep(void);
+-
+ /*
+ * This file handles the architecture-dependent parts of process handling..
+ */
+@@ -54,6 +54,8 @@
- source "fs/Kconfig"
+ void machine_power_off(void)
+ {
++ if (pm_power_off)
++ pm_power_off();
+ }
-+source "kernel/Kconfig.instrumentation"
-+
- source "arch/avr32/Kconfig.debug"
+ void machine_restart(char *cmd)
+--- a/arch/avr32/kernel/setup.c
++++ b/arch/avr32/kernel/setup.c
+@@ -274,6 +274,8 @@
+ printk(KERN_WARNING
+ "Failed to allocate framebuffer memory\n");
+ fbmem_size = 0;
++ } else {
++ memset(__va(fbmem_start), 0, fbmem_size);
+ }
+ }
- source "security/Kconfig"
---- a/arch/avr32/Kconfig.debug
-+++ b/arch/avr32/Kconfig.debug
-@@ -6,14 +6,4 @@
+--- a/arch/avr32/kernel/signal.c
++++ b/arch/avr32/kernel/signal.c
+@@ -93,6 +93,9 @@
+ if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
+ goto badframe;
- source "lib/Kconfig.debug"
++ if (do_sigaltstack(&frame->uc.uc_stack, NULL, regs->sp) == -EFAULT)
++ goto badframe;
++
+ pr_debug("Context restored: pc = %08lx, lr = %08lx, sp = %08lx\n",
+ regs->pc, regs->lr, regs->sp);
--config KPROBES
-- bool "Kprobes"
-- depends on DEBUG_KERNEL
-- help
-- Kprobes allows you to trap at almost any kernel address and
-- execute a callback function. register_kprobe() establishes
-- a probepoint and specifies the callback. Kprobes is useful
-- for kernel debugging, non-intrusive instrumentation and testing.
-- If in doubt, say "N".
+--- a/arch/avr32/kernel/time.c
++++ b/arch/avr32/kernel/time.c
+@@ -1,233 +1,147 @@
+ /*
+ * Copyright (C) 2004-2007 Atmel Corporation
+ *
+- * Based on MIPS implementation arch/mips/kernel/time.c
+- * Copyright 2001 MontaVista Software Inc.
+- *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
-
- endmenu
---- a/arch/avr32/kernel/cpu.c
-+++ b/arch/avr32/kernel/cpu.c
-@@ -13,6 +13,7 @@
- #include <linux/percpu.h>
- #include <linux/param.h>
- #include <linux/errno.h>
-+#include <linux/clk.h>
+ #include <linux/clk.h>
+-#include <linux/clocksource.h>
+-#include <linux/time.h>
+-#include <linux/module.h>
++#include <linux/clockchips.h>
++#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/irq.h>
+-#include <linux/kernel_stat.h>
+-#include <linux/errno.h>
+-#include <linux/init.h>
+-#include <linux/profile.h>
+-#include <linux/sysdev.h>
+-#include <linux/err.h>
++#include <linux/kernel.h>
++#include <linux/time.h>
- #include <asm/setup.h>
+-#include <asm/div64.h>
#include <asm/sysreg.h>
-@@ -187,9 +188,20 @@
+-#include <asm/io.h>
+-#include <asm/sections.h>
- subsys_initcall(topology_init);
+-/* how many counter cycles in a jiffy? */
+-static u32 cycles_per_jiffy;
++#include <asm/arch/pm.h>
-+struct chip_id_map {
-+ u16 mid;
-+ u16 pn;
-+ const char *name;
-+};
-+
-+static const struct chip_id_map chip_names[] = {
-+ { .mid = 0x1f, .pn = 0x1e82, .name = "AT32AP700x" },
-+};
-+#define NR_CHIP_NAMES ARRAY_SIZE(chip_names)
-+
- static const char *cpu_names[] = {
- "Morgan",
-- "AP7000",
-+ "AP7",
- };
- #define NR_CPU_NAMES ARRAY_SIZE(cpu_names)
+-/* the count value for the next timer interrupt */
+-static u32 expirelo;
+
+-cycle_t __weak read_cycle_count(void)
++static cycle_t read_cycle_count(void)
+ {
+ return (cycle_t)sysreg_read(COUNT);
+ }
-@@ -206,12 +218,32 @@
- "MPU"
+-struct clocksource __weak clocksource_avr32 = {
+- .name = "avr32",
+- .rating = 350,
++/*
++ * The architectural cycle count registers are a fine clocksource unless
++ * the system idle loop use sleep states like "idle": the CPU cycles
++ * measured by COUNT (and COMPARE) don't happen during sleep states.
++ * Their duration also changes if cpufreq changes the CPU clock rate.
++ * So we rate the clocksource using COUNT as very low quality.
++ */
++static struct clocksource counter = {
++ .name = "avr32_counter",
++ .rating = 50,
+ .read = read_cycle_count,
+ .mask = CLOCKSOURCE_MASK(32),
+ .shift = 16,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
-+static const char *cpu_feature_flags[] = {
-+ "rmw", "dsp", "simd", "ocd", "perfctr", "java", "fpu",
-+};
-+
-+static const char *get_chip_name(struct avr32_cpuinfo *cpu)
-+{
-+ unsigned int i;
-+ unsigned int mid = avr32_get_manufacturer_id(cpu);
-+ unsigned int pn = avr32_get_product_number(cpu);
-+
-+ for (i = 0; i < NR_CHIP_NAMES; i++) {
-+ if (chip_names[i].mid == mid && chip_names[i].pn == pn)
-+ return chip_names[i].name;
-+ }
-+
-+ return "(unknown)";
-+}
-+
- void __init setup_processor(void)
+-irqreturn_t __weak timer_interrupt(int irq, void *dev_id);
+-
+-struct irqaction timer_irqaction = {
+- .handler = timer_interrupt,
+- .flags = IRQF_DISABLED,
+- .name = "timer",
+-};
+-
+-/*
+- * By default we provide the null RTC ops
+- */
+-static unsigned long null_rtc_get_time(void)
+-{
+- return mktime(2007, 1, 1, 0, 0, 0);
+-}
+-
+-static int null_rtc_set_time(unsigned long sec)
++static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
- unsigned long config0, config1;
- unsigned long features;
- unsigned cpu_id, cpu_rev, arch_id, arch_rev, mmu_type;
-+ unsigned device_id;
- unsigned tmp;
-+ unsigned i;
-
- config0 = sysreg_read(CONFIG0);
- config1 = sysreg_read(CONFIG1);
-@@ -221,11 +253,14 @@
- arch_rev = SYSREG_BFEXT(AR, config0);
- mmu_type = SYSREG_BFEXT(MMUT, config0);
-
-+ device_id = ocd_read(DID);
-+
- boot_cpu_data.arch_type = arch_id;
- boot_cpu_data.cpu_type = cpu_id;
- boot_cpu_data.arch_revision = arch_rev;
- boot_cpu_data.cpu_revision = cpu_rev;
- boot_cpu_data.tlb_config = mmu_type;
-+ boot_cpu_data.device_id = device_id;
-
- tmp = SYSREG_BFEXT(ILSZ, config1);
- if (tmp) {
-@@ -247,41 +282,34 @@
- return;
- }
+- return 0;
+-}
+-
+-static unsigned long (*rtc_get_time)(void) = null_rtc_get_time;
+-static int (*rtc_set_time)(unsigned long) = null_rtc_set_time;
++ struct clock_event_device *evdev = dev_id;
-- printk ("CPU: %s [%02x] revision %d (%s revision %d)\n",
-+ printk ("CPU: %s chip revision %c\n", get_chip_name(&boot_cpu_data),
-+ avr32_get_chip_revision(&boot_cpu_data) + 'A');
-+ printk ("CPU: %s [%02x] core revision %d (%s arch revision %d)\n",
- cpu_names[cpu_id], cpu_id, cpu_rev,
- arch_names[arch_id], arch_rev);
- printk ("CPU: MMU configuration: %s\n", mmu_types[mmu_type]);
-
- printk ("CPU: features:");
- features = 0;
-- if (config0 & SYSREG_BIT(CONFIG0_R)) {
-+ if (config0 & SYSREG_BIT(CONFIG0_R))
- features |= AVR32_FEATURE_RMW;
-- printk(" rmw");
-- }
-- if (config0 & SYSREG_BIT(CONFIG0_D)) {
-+ if (config0 & SYSREG_BIT(CONFIG0_D))
- features |= AVR32_FEATURE_DSP;
-- printk(" dsp");
-- }
-- if (config0 & SYSREG_BIT(CONFIG0_S)) {
-+ if (config0 & SYSREG_BIT(CONFIG0_S))
- features |= AVR32_FEATURE_SIMD;
-- printk(" simd");
-- }
-- if (config0 & SYSREG_BIT(CONFIG0_O)) {
-+ if (config0 & SYSREG_BIT(CONFIG0_O))
- features |= AVR32_FEATURE_OCD;
-- printk(" ocd");
+-static void avr32_timer_ack(void)
+-{
+- u32 count;
+-
+- /* Ack this timer interrupt and set the next one */
+- expirelo += cycles_per_jiffy;
+- /* setting COMPARE to 0 stops the COUNT-COMPARE */
+- if (expirelo == 0) {
+- sysreg_write(COMPARE, expirelo + 1);
+- } else {
+- sysreg_write(COMPARE, expirelo);
- }
-- if (config0 & SYSREG_BIT(CONFIG0_P)) {
-+ if (config0 & SYSREG_BIT(CONFIG0_P))
- features |= AVR32_FEATURE_PCTR;
-- printk(" perfctr");
++ /*
++ * Disable the interrupt until the clockevent subsystem
++ * reprograms it.
++ */
++ sysreg_write(COMPARE, 0);
+
+- /* Check to see if we have missed any timer interrupts */
+- count = sysreg_read(COUNT);
+- if ((count - expirelo) < 0x7fffffff) {
+- expirelo = count + cycles_per_jiffy;
+- sysreg_write(COMPARE, expirelo);
- }
-- if (config0 & SYSREG_BIT(CONFIG0_J)) {
-+ if (config0 & SYSREG_BIT(CONFIG0_J))
- features |= AVR32_FEATURE_JAVA;
-- printk(" java");
++ evdev->event_handler(evdev);
++ return IRQ_HANDLED;
+ }
+
+-int __weak avr32_hpt_init(void)
+-{
+- int ret;
+- unsigned long mult, shift, count_hz;
+-
+- count_hz = clk_get_rate(boot_cpu_data.clk);
+- shift = clocksource_avr32.shift;
+- mult = clocksource_hz2mult(count_hz, shift);
+- clocksource_avr32.mult = mult;
+-
+- {
+- u64 tmp;
+-
+- tmp = TICK_NSEC;
+- tmp <<= shift;
+- tmp += mult / 2;
+- do_div(tmp, mult);
+-
+- cycles_per_jiffy = tmp;
- }
-- if (config0 & SYSREG_BIT(CONFIG0_F)) {
-+ if (config0 & SYSREG_BIT(CONFIG0_F))
- features |= AVR32_FEATURE_FPU;
-- printk(" fpu");
++static struct irqaction timer_irqaction = {
++ .handler = timer_interrupt,
++ .flags = IRQF_TIMER | IRQF_DISABLED,
++ .name = "avr32_comparator",
++};
+
+- ret = setup_irq(0, &timer_irqaction);
+- if (ret) {
+- pr_debug("timer: could not request IRQ 0: %d\n", ret);
+- return -ENODEV;
- }
-+
-+ for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
-+ if (features & (1 << i))
-+ printk(" %s", cpu_feature_flags[i]);
-+
- printk("\n");
- boot_cpu_data.features = features;
- }
-@@ -291,6 +319,8 @@
- {
- unsigned int icache_size, dcache_size;
- unsigned int cpu = smp_processor_id();
-+ unsigned int freq;
-+ unsigned int i;
++static int comparator_next_event(unsigned long delta,
++ struct clock_event_device *evdev)
++{
++ unsigned long flags;
+
+- printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
+- "%lu.%03lu MHz\n",
+- ((count_hz + 500) / 1000) / 1000,
+- ((count_hz + 500) / 1000) % 1000);
++ raw_local_irq_save(flags);
+
+- return 0;
+-}
++ /* The time to read COUNT then update COMPARE must be less
++ * than the min_delta_ns value for this clockevent source.
++ */
++ sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
- icache_size = boot_cpu_data.icache.ways *
- boot_cpu_data.icache.sets *
-@@ -301,15 +331,21 @@
-
- seq_printf(m, "processor\t: %d\n", cpu);
-
-+ seq_printf(m, "chip type\t: %s revision %c\n",
-+ get_chip_name(&boot_cpu_data),
-+ avr32_get_chip_revision(&boot_cpu_data) + 'A');
- if (boot_cpu_data.arch_type < NR_ARCH_NAMES)
-- seq_printf(m, "cpu family\t: %s revision %d\n",
-+ seq_printf(m, "cpu arch\t: %s revision %d\n",
- arch_names[boot_cpu_data.arch_type],
- boot_cpu_data.arch_revision);
- if (boot_cpu_data.cpu_type < NR_CPU_NAMES)
-- seq_printf(m, "cpu type\t: %s revision %d\n",
-+ seq_printf(m, "cpu core\t: %s revision %d\n",
- cpu_names[boot_cpu_data.cpu_type],
- boot_cpu_data.cpu_revision);
-
-+ freq = (clk_get_rate(boot_cpu_data.clk) + 500) / 1000;
-+ seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, freq % 1000);
-+
- seq_printf(m, "i-cache\t\t: %dK (%u ways x %u sets x %u)\n",
- icache_size >> 10,
- boot_cpu_data.icache.ways,
-@@ -320,7 +356,13 @@
- boot_cpu_data.dcache.ways,
- boot_cpu_data.dcache.sets,
- boot_cpu_data.dcache.linesz);
-- seq_printf(m, "bogomips\t: %lu.%02lu\n",
-+
-+ seq_printf(m, "features\t:");
-+ for (i = 0; i < ARRAY_SIZE(cpu_feature_flags); i++)
-+ if (boot_cpu_data.features & (1 << i))
-+ seq_printf(m, " %s", cpu_feature_flags[i]);
-+
-+ seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
- boot_cpu_data.loops_per_jiffy / (500000/HZ),
- (boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100);
-
-@@ -343,7 +385,7 @@
+-/*
+- * Taken from MIPS c0_hpt_timer_init().
+- *
+- * The reason COUNT is written twice is probably to make sure we don't get any
+- * timer interrupts while we are messing with the counter.
+- */
+-int __weak avr32_hpt_start(void)
+-{
+- u32 count = sysreg_read(COUNT);
+- expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
+- sysreg_write(COUNT, expirelo - cycles_per_jiffy);
+- sysreg_write(COMPARE, expirelo);
+- sysreg_write(COUNT, count);
++ raw_local_irq_restore(flags);
+ return 0;
}
--struct seq_operations cpuinfo_op = {
-+const struct seq_operations cpuinfo_op = {
- .start = c_start,
- .next = c_next,
- .stop = c_stop,
---- /dev/null
-+++ b/arch/avr32/kernel/dma-controller.c
-@@ -0,0 +1,34 @@
-+/*
-+ * Preliminary DMA controller framework for AVR32
-+ *
-+ * Copyright (C) 2005-2006 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <asm/dma-controller.h>
-+
-+static LIST_HEAD(controllers);
-+
-+int register_dma_controller(struct dma_controller *dmac)
-+{
-+ static int next_id;
-+
-+ dmac->id = next_id++;
-+ list_add_tail(&dmac->list, &controllers);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL(register_dma_controller);
-+
-+struct dma_controller *find_dma_controller(int id)
-+{
-+ struct dma_controller *dmac;
-+
-+ list_for_each_entry(dmac, &controllers, list)
-+ if (dmac->id == id)
-+ return dmac;
-+ return NULL;
-+}
-+EXPORT_SYMBOL(find_dma_controller);
---- a/arch/avr32/kernel/entry-avr32b.S
-+++ b/arch/avr32/kernel/entry-avr32b.S
-@@ -741,26 +741,6 @@
-
- .section .irq.text,"ax",@progbits
+-/*
+- * local_timer_interrupt() does profiling and process accounting on a
+- * per-CPU basis.
+- *
+- * In UP mode, it is invoked from the (global) timer_interrupt.
+- */
+-void local_timer_interrupt(int irq, void *dev_id)
++static void comparator_mode(enum clock_event_mode mode,
++ struct clock_event_device *evdev)
+ {
+- if (current->pid)
+- profile_tick(CPU_PROFILING);
+- update_process_times(user_mode(get_irq_regs()));
++ switch (mode) {
++ case CLOCK_EVT_MODE_ONESHOT:
++ pr_debug("%s: start\n", evdev->name);
++ /* FALLTHROUGH */
++ case CLOCK_EVT_MODE_RESUME:
++ cpu_disable_idle_sleep();
++ break;
++ case CLOCK_EVT_MODE_UNUSED:
++ case CLOCK_EVT_MODE_SHUTDOWN:
++ sysreg_write(COMPARE, 0);
++ pr_debug("%s: stop\n", evdev->name);
++ cpu_enable_idle_sleep();
++ break;
++ default:
++ BUG();
++ }
+ }
--.global cpu_idle_sleep
--cpu_idle_sleep:
-- mask_interrupts
-- get_thread_info r8
-- ld.w r9, r8[TI_flags]
-- bld r9, TIF_NEED_RESCHED
-- brcs cpu_idle_enable_int_and_exit
-- sbr r9, TIF_CPU_GOING_TO_SLEEP
-- st.w r8[TI_flags], r9
-- unmask_interrupts
-- sleep 0
--cpu_idle_skip_sleep:
-- mask_interrupts
-- ld.w r9, r8[TI_flags]
-- cbr r9, TIF_CPU_GOING_TO_SLEEP
-- st.w r8[TI_flags], r9
--cpu_idle_enable_int_and_exit:
-- unmask_interrupts
-- retal r12
+-irqreturn_t __weak timer_interrupt(int irq, void *dev_id)
+-{
+- /* ack timer interrupt and try to set next interrupt */
+- avr32_timer_ack();
-
- .global irq_level0
- .global irq_level1
- .global irq_level2
---- a/arch/avr32/kernel/irq.c
-+++ b/arch/avr32/kernel/irq.c
-@@ -25,6 +25,17 @@
- printk("unexpected IRQ %u\n", irq);
- }
+- /*
+- * Call the generic timer interrupt handler
+- */
+- write_seqlock(&xtime_lock);
+- do_timer(1);
+- write_sequnlock(&xtime_lock);
+-
+- /*
+- * In UP mode, we call local_timer_interrupt() to do profiling
+- * and process accounting.
+- *
+- * SMP is not supported yet.
+- */
+- local_timer_interrupt(irq, dev_id);
+-
+- return IRQ_HANDLED;
+-}
++static struct clock_event_device comparator = {
++ .name = "avr32_comparator",
++ .features = CLOCK_EVT_FEAT_ONESHOT,
++ .shift = 16,
++ .rating = 50,
++ .cpumask = CPU_MASK_CPU0,
++ .set_next_event = comparator_next_event,
++ .set_mode = comparator_mode,
++};
-+/* May be overridden by platform code */
-+int __weak nmi_enable(void)
-+{
-+ return -ENOSYS;
-+}
-+
-+void __weak nmi_disable(void)
-+{
-+
-+}
-+
- #ifdef CONFIG_PROC_FS
- int show_interrupts(struct seq_file *p, void *v)
- {
---- a/arch/avr32/kernel/kprobes.c
-+++ b/arch/avr32/kernel/kprobes.c
-@@ -48,6 +48,7 @@
- void __kprobes arch_arm_kprobe(struct kprobe *p)
- {
- pr_debug("arming kprobe at %p\n", p->addr);
-+ ocd_enable(NULL);
- *p->addr = BREAKPOINT_INSTRUCTION;
- flush_icache_range((unsigned long)p->addr,
- (unsigned long)p->addr + sizeof(kprobe_opcode_t));
-@@ -56,6 +57,7 @@
- void __kprobes arch_disarm_kprobe(struct kprobe *p)
- {
- pr_debug("disarming kprobe at %p\n", p->addr);
-+ ocd_disable(NULL);
- *p->addr = p->opcode;
- flush_icache_range((unsigned long)p->addr,
- (unsigned long)p->addr + sizeof(kprobe_opcode_t));
-@@ -260,9 +262,6 @@
-
- int __init arch_init_kprobes(void)
+ void __init time_init(void)
{
-- printk("KPROBES: Enabling monitor mode (MM|DBE)...\n");
-- ocd_write(DC, (1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT));
++ unsigned long counter_hz;
+ int ret;
+
+- /*
+- * Make sure we don't get any COMPARE interrupts before we can
+- * handle them.
+- */
+- sysreg_write(COMPARE, 0);
-
- /* TODO: Register kretprobe trampoline */
- return 0;
- }
---- a/arch/avr32/kernel/Makefile
-+++ b/arch/avr32/kernel/Makefile
-@@ -6,9 +6,11 @@
+- xtime.tv_sec = rtc_get_time();
++ xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
+ xtime.tv_nsec = 0;
- obj-$(CONFIG_SUBARCH_AVR32B) += entry-avr32b.o
- obj-y += syscall_table.o syscall-stubs.o irq.o
--obj-y += setup.o traps.o semaphore.o ptrace.o
-+obj-y += setup.o traps.o semaphore.o ocd.o ptrace.o
- obj-y += signal.o sys_avr32.o process.o time.o
- obj-y += init_task.o switch_to.o cpu.o
-+obj-y += dma-controller.o
- obj-$(CONFIG_MODULES) += module.o avr32_ksyms.o
- obj-$(CONFIG_KPROBES) += kprobes.o
- obj-$(CONFIG_STACKTRACE) += stacktrace.o
-+obj-$(CONFIG_NMI_DEBUGGING) += nmi_debug.o
---- /dev/null
-+++ b/arch/avr32/kernel/nmi_debug.c
-@@ -0,0 +1,82 @@
-+/*
-+ * Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/delay.h>
-+#include <linux/kdebug.h>
-+#include <linux/notifier.h>
-+#include <linux/sched.h>
-+
-+#include <asm/irq.h>
-+
-+enum nmi_action {
-+ NMI_SHOW_STATE = 1 << 0,
-+ NMI_SHOW_REGS = 1 << 1,
-+ NMI_DIE = 1 << 2,
-+ NMI_DEBOUNCE = 1 << 3,
-+};
-+
-+static unsigned long nmi_actions;
-+
-+static int nmi_debug_notify(struct notifier_block *self,
-+ unsigned long val, void *data)
-+{
-+ struct die_args *args = data;
-+
-+ if (likely(val != DIE_NMI))
-+ return NOTIFY_DONE;
-+
-+ if (nmi_actions & NMI_SHOW_STATE)
-+ show_state();
-+ if (nmi_actions & NMI_SHOW_REGS)
-+ show_regs(args->regs);
-+ if (nmi_actions & NMI_DEBOUNCE)
-+ mdelay(10);
-+ if (nmi_actions & NMI_DIE)
-+ return NOTIFY_BAD;
-+
-+ return NOTIFY_OK;
-+}
-+
-+static struct notifier_block nmi_debug_nb = {
-+ .notifier_call = nmi_debug_notify,
-+};
-+
-+static int __init nmi_debug_setup(char *str)
-+{
-+ char *p, *sep;
-+
-+ register_die_notifier(&nmi_debug_nb);
-+ if (nmi_enable()) {
-+ printk(KERN_WARNING "Unable to enable NMI.\n");
-+ return 0;
+ set_normalized_timespec(&wall_to_monotonic,
+ -xtime.tv_sec, -xtime.tv_nsec);
+
+- ret = avr32_hpt_init();
+- if (ret) {
+- pr_debug("timer: failed setup: %d\n", ret);
+- return;
+- }
++ /* figure rate for counter */
++ counter_hz = clk_get_rate(boot_cpu_data.clk);
++ counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
+
+- ret = clocksource_register(&clocksource_avr32);
++ ret = clocksource_register(&counter);
+ if (ret)
+ pr_debug("timer: could not register clocksource: %d\n", ret);
+
+- ret = avr32_hpt_start();
+- if (ret) {
+- pr_debug("timer: failed starting: %d\n", ret);
+- return;
+- }
+-}
++ /* setup COMPARE clockevent */
++ comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
++ comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
++ comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
+
+-static struct sysdev_class timer_class = {
+- .name = "timer",
+-};
++ sysreg_write(COMPARE, 0);
++ timer_irqaction.dev_id = &comparator;
+
+-static struct sys_device timer_device = {
+- .id = 0,
+- .cls = &timer_class,
+-};
++ ret = setup_irq(0, &timer_irqaction);
++ if (ret)
++ pr_debug("timer: could not request IRQ 0: %d\n", ret);
++ else {
++ clockevents_register_device(&comparator);
+
+-static int __init init_timer_sysfs(void)
+-{
+- int err = sysdev_class_register(&timer_class);
+- if (!err)
+- err = sysdev_register(&timer_device);
+- return err;
++ pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
++ ((counter_hz + 500) / 1000) / 1000,
++ ((counter_hz + 500) / 1000) % 1000);
+ }
+ }
+-
+-device_initcall(init_timer_sysfs);
+--- a/arch/avr32/kernel/vmlinux.lds.S
++++ b/arch/avr32/kernel/vmlinux.lds.S
+@@ -68,14 +68,6 @@
+ _evba = .;
+ _text = .;
+ *(.ex.text)
+- . = 0x50;
+- *(.tlbx.ex.text)
+- . = 0x60;
+- *(.tlbr.ex.text)
+- . = 0x70;
+- *(.tlbw.ex.text)
+- . = 0x100;
+- *(.scall.text)
+ *(.irq.text)
+ KPROBES_TEXT
+ TEXT_TEXT
+@@ -107,6 +99,10 @@
+ */
+ *(.data.init_task)
+
++ /* Then, the page-aligned data */
++ . = ALIGN(PAGE_SIZE);
++ *(.data.page_aligned)
++
+ /* Then, the cacheline aligned data */
+ . = ALIGN(L1_CACHE_BYTES);
+ *(.data.cacheline_aligned)
+--- a/arch/avr32/lib/io-readsb.S
++++ b/arch/avr32/lib/io-readsb.S
+@@ -41,7 +41,7 @@
+ 2: sub r10, -4
+ reteq r12
+
+-3: ld.uh r8, r12[0]
++3: ld.ub r8, r12[0]
+ sub r10, 1
+ st.b r11++, r8
+ brne 3b
+--- a/arch/avr32/mach-at32ap/Kconfig
++++ b/arch/avr32/mach-at32ap/Kconfig
+@@ -26,6 +26,13 @@
+
+ endchoice
+
++config GPIO_DEV
++ bool "GPIO /dev interface"
++ select CONFIGFS_FS
++ default n
++ help
++ Say `Y' to enable a /dev interface to the GPIO pins.
+
-+ if (*str != '=')
-+ return 0;
-+
-+ for (p = str + 1; *p; p = sep + 1) {
-+ sep = strchr(p, ',');
-+ if (sep)
-+ *sep = 0;
-+ if (strcmp(p, "state") == 0)
-+ nmi_actions |= NMI_SHOW_STATE;
-+ else if (strcmp(p, "regs") == 0)
-+ nmi_actions |= NMI_SHOW_REGS;
-+ else if (strcmp(p, "debounce") == 0)
-+ nmi_actions |= NMI_DEBOUNCE;
-+ else if (strcmp(p, "die") == 0)
-+ nmi_actions |= NMI_DIE;
-+ else
-+ printk(KERN_WARNING "NMI: Unrecognized action `%s'\n",
-+ p);
-+ if (!sep)
-+ break;
-+ }
+ endmenu
+
+ endif # PLATFORM_AT32AP
+--- a/arch/avr32/mach-at32ap/Makefile
++++ b/arch/avr32/mach-at32ap/Makefile
+@@ -1,4 +1,9 @@
+-obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
+-obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o
+-obj-$(CONFIG_CPU_AT32AP700X) += time-tc.o
++obj-y += pdc.o clock.o intc.o extint.o pio.o hsmc.o
++obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
+ obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
++obj-$(CONFIG_GPIO_DEV) += gpio-dev.o
++obj-$(CONFIG_PM) += pm.o
+
-+ return 0;
-+}
-+__setup("nmi_debug", nmi_debug_setup);
---- /dev/null
-+++ b/arch/avr32/kernel/ocd.c
-@@ -0,0 +1,163 @@
-+/*
-+ * Copyright (C) 2007 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/init.h>
-+#include <linux/sched.h>
-+#include <linux/spinlock.h>
-+
-+#include <asm/ocd.h>
-+
-+static long ocd_count;
-+static spinlock_t ocd_lock;
++ifeq ($(CONFIG_PM_DEBUG),y)
++CFLAGS_pm.o += -DDEBUG
++endif
+--- a/arch/avr32/mach-at32ap/at32ap.c
++++ /dev/null
+@@ -1,56 +0,0 @@
+-/*
+- * Copyright (C) 2006 Atmel Corporation
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- */
+-
+-#include <linux/clk.h>
+-#include <linux/err.h>
+-#include <linux/init.h>
+-#include <linux/platform_device.h>
+-
+-#include <asm/arch/init.h>
+-
+-void __init setup_platform(void)
+-{
+- at32_clock_init();
+- at32_portmux_init();
+-}
+-
+-static int __init pdc_probe(struct platform_device *pdev)
+-{
+- struct clk *pclk, *hclk;
+-
+- pclk = clk_get(&pdev->dev, "pclk");
+- if (IS_ERR(pclk)) {
+- dev_err(&pdev->dev, "no pclk defined\n");
+- return PTR_ERR(pclk);
+- }
+- hclk = clk_get(&pdev->dev, "hclk");
+- if (IS_ERR(hclk)) {
+- dev_err(&pdev->dev, "no hclk defined\n");
+- clk_put(pclk);
+- return PTR_ERR(hclk);
+- }
+-
+- clk_enable(pclk);
+- clk_enable(hclk);
+-
+- dev_info(&pdev->dev, "Atmel Peripheral DMA Controller enabled\n");
+- return 0;
+-}
+-
+-static struct platform_driver pdc_driver = {
+- .probe = pdc_probe,
+- .driver = {
+- .name = "pdc",
+- },
+-};
+-
+-static int __init pdc_init(void)
+-{
+- return platform_driver_register(&pdc_driver);
+-}
+-arch_initcall(pdc_init);
+--- a/arch/avr32/mach-at32ap/at32ap700x.c
++++ b/arch/avr32/mach-at32ap/at32ap700x.c
+@@ -6,11 +6,13 @@
+ * published by the Free Software Foundation.
+ */
+ #include <linux/clk.h>
++#include <linux/delay.h>
+ #include <linux/fb.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/spi/spi.h>
++#include <linux/usb/atmel_usba_udc.h>
+
+ #include <asm/io.h>
+ #include <asm/irq.h>
+@@ -18,6 +20,7 @@
+ #include <asm/arch/at32ap700x.h>
+ #include <asm/arch/board.h>
+ #include <asm/arch/portmux.h>
++#include <asm/arch/sram.h>
+
+ #include <video/atmel_lcdc.h>
+
+@@ -91,25 +94,18 @@
+
+ static DEFINE_SPINLOCK(pm_lock);
+
+-unsigned long at32ap7000_osc_rates[3] = {
+- [0] = 32768,
+- /* FIXME: these are ATSTK1002-specific */
+- [1] = 20000000,
+- [2] = 12000000,
+-};
++static struct clk osc0;
++static struct clk osc1;
+
+ static unsigned long osc_get_rate(struct clk *clk)
+ {
+- return at32ap7000_osc_rates[clk->index];
++ return at32_board_osc_rates[clk->index];
+ }
+
+ static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
+ {
+ unsigned long div, mul, rate;
+
+- if (!(control & PM_BIT(PLLEN)))
+- return 0;
+-
+ div = PM_BFEXT(PLLDIV, control) + 1;
+ mul = PM_BFEXT(PLLMUL, control) + 1;
+
+@@ -120,6 +116,71 @@
+ return rate;
+ }
+
++static long pll_set_rate(struct clk *clk, unsigned long rate,
++ u32 *pll_ctrl)
++{
++ unsigned long mul;
++ unsigned long mul_best_fit = 0;
++ unsigned long div;
++ unsigned long div_min;
++ unsigned long div_max;
++ unsigned long div_best_fit = 0;
++ unsigned long base;
++ unsigned long pll_in;
++ unsigned long actual = 0;
++ unsigned long rate_error;
++ unsigned long rate_error_prev = ~0UL;
++ u32 ctrl;
++
++ /* Rate must be between 80 MHz and 200 Mhz. */
++ if (rate < 80000000UL || rate > 200000000UL)
++ return -EINVAL;
+
-+/**
-+ * ocd_enable - enable on-chip debugging
-+ * @child: task to be debugged
-+ *
-+ * If @child is non-NULL, ocd_enable() first checks if debugging has
-+ * already been enabled for @child, and if it has, does nothing.
-+ *
-+ * If @child is NULL (e.g. when debugging the kernel), or debugging
-+ * has not already been enabled for it, ocd_enable() increments the
-+ * reference count and enables the debugging hardware.
-+ */
-+void ocd_enable(struct task_struct *child)
-+{
-+ u32 dc;
++ ctrl = PM_BF(PLLOPT, 4);
++ base = clk->parent->get_rate(clk->parent);
+
-+ if (child)
-+ pr_debug("ocd_enable: child=%s [%u]\n",
-+ child->comm, child->pid);
-+ else
-+ pr_debug("ocd_enable (no child)\n");
-+
-+ if (!child || !test_and_set_tsk_thread_flag(child, TIF_DEBUG)) {
-+ spin_lock(&ocd_lock);
-+ ocd_count++;
-+ dc = ocd_read(DC);
-+ dc |= (1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT);
-+ ocd_write(DC, dc);
-+ spin_unlock(&ocd_lock);
-+ }
-+}
++ /* PLL input frequency must be between 6 MHz and 32 MHz. */
++ div_min = DIV_ROUND_UP(base, 32000000UL);
++ div_max = base / 6000000UL;
+
-+/**
-+ * ocd_disable - disable on-chip debugging
-+ * @child: task that was being debugged, but isn't anymore
-+ *
-+ * If @child is non-NULL, ocd_disable() checks if debugging is enabled
-+ * for @child, and if it isn't, does nothing.
-+ *
-+ * If @child is NULL (e.g. when debugging the kernel), or debugging is
-+ * enabled, ocd_disable() decrements the reference count, and if it
-+ * reaches zero, disables the debugging hardware.
-+ */
-+void ocd_disable(struct task_struct *child)
-+{
-+ u32 dc;
++ if (div_max < div_min)
++ return -EINVAL;
+
-+ if (!child)
-+ pr_debug("ocd_disable (no child)\n");
-+ else if (test_tsk_thread_flag(child, TIF_DEBUG))
-+ pr_debug("ocd_disable: child=%s [%u]\n",
-+ child->comm, child->pid);
++ for (div = div_min; div <= div_max; div++) {
++ pll_in = (base + div / 2) / div;
++ mul = (rate + pll_in / 2) / pll_in;
+
-+ if (!child || test_and_clear_tsk_thread_flag(child, TIF_DEBUG)) {
-+ spin_lock(&ocd_lock);
-+ ocd_count--;
++ if (mul == 0)
++ continue;
+
-+ WARN_ON(ocd_count < 0);
++ actual = pll_in * mul;
++ rate_error = abs(actual - rate);
+
-+ if (ocd_count <= 0) {
-+ dc = ocd_read(DC);
-+ dc &= ~((1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT));
-+ ocd_write(DC, dc);
++ if (rate_error < rate_error_prev) {
++ mul_best_fit = mul;
++ div_best_fit = div;
++ rate_error_prev = rate_error;
+ }
-+ spin_unlock(&ocd_lock);
++
++ if (rate_error == 0)
++ break;
+ }
-+}
+
-+#ifdef CONFIG_DEBUG_FS
-+#include <linux/debugfs.h>
-+#include <linux/module.h>
++ if (div_best_fit == 0)
++ return -EINVAL;
+
-+static struct dentry *ocd_debugfs_root;
-+static struct dentry *ocd_debugfs_DC;
-+static struct dentry *ocd_debugfs_DS;
-+static struct dentry *ocd_debugfs_count;
++ ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
++ ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
++ ctrl |= PM_BF(PLLCOUNT, 16);
+
-+static u64 ocd_DC_get(void *data)
-+{
-+ return ocd_read(DC);
-+}
-+static void ocd_DC_set(void *data, u64 val)
-+{
-+ ocd_write(DC, val);
-+}
-+DEFINE_SIMPLE_ATTRIBUTE(fops_DC, ocd_DC_get, ocd_DC_set, "0x%08llx\n");
++ if (clk->parent == &osc1)
++ ctrl |= PM_BIT(PLLOSC);
+
-+static u64 ocd_DS_get(void *data)
-+{
-+ return ocd_read(DS);
-+}
-+DEFINE_SIMPLE_ATTRIBUTE(fops_DS, ocd_DS_get, NULL, "0x%08llx\n");
++ *pll_ctrl = ctrl;
+
-+static u64 ocd_count_get(void *data)
-+{
-+ return ocd_count;
++ return actual;
+}
-+DEFINE_SIMPLE_ATTRIBUTE(fops_count, ocd_count_get, NULL, "%lld\n");
+
-+static void ocd_debugfs_init(void)
+ static unsigned long pll0_get_rate(struct clk *clk)
+ {
+ u32 control;
+@@ -129,6 +190,41 @@
+ return pll_get_rate(clk, control);
+ }
+
++static void pll1_mode(struct clk *clk, int enabled)
+{
-+ struct dentry *root;
-+
-+ root = debugfs_create_dir("ocd", NULL);
-+ if (IS_ERR(root) || !root)
-+ goto err_root;
-+ ocd_debugfs_root = root;
++ unsigned long timeout;
++ u32 status;
++ u32 ctrl;
+
-+ ocd_debugfs_DC = debugfs_create_file("DC", S_IRUSR | S_IWUSR,
-+ root, NULL, &fops_DC);
-+ if (!ocd_debugfs_DC)
-+ goto err_DC;
++ ctrl = pm_readl(PLL1);
+
-+ ocd_debugfs_DS = debugfs_create_file("DS", S_IRUSR, root,
-+ NULL, &fops_DS);
-+ if (!ocd_debugfs_DS)
-+ goto err_DS;
++ if (enabled) {
++ if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
++ pr_debug("clk %s: failed to enable, rate not set\n",
++ clk->name);
++ return;
++ }
+
-+ ocd_debugfs_count = debugfs_create_file("count", S_IRUSR, root,
-+ NULL, &fops_count);
-+ if (!ocd_debugfs_count)
-+ goto err_count;
++ ctrl |= PM_BIT(PLLEN);
++ pm_writel(PLL1, ctrl);
+
-+ return;
++ /* Wait for PLL lock. */
++ for (timeout = 10000; timeout; timeout--) {
++ status = pm_readl(ISR);
++ if (status & PM_BIT(LOCK1))
++ break;
++ udelay(10);
++ }
+
-+err_count:
-+ debugfs_remove(ocd_debugfs_DS);
-+err_DS:
-+ debugfs_remove(ocd_debugfs_DC);
-+err_DC:
-+ debugfs_remove(ocd_debugfs_root);
-+err_root:
-+ printk(KERN_WARNING "OCD: Failed to create debugfs entries\n");
++ if (!(status & PM_BIT(LOCK1)))
++ printk(KERN_ERR "clk %s: timeout waiting for lock\n",
++ clk->name);
++ } else {
++ ctrl &= ~PM_BIT(PLLEN);
++ pm_writel(PLL1, ctrl);
++ }
+}
-+#else
-+static inline void ocd_debugfs_init(void)
++
+ static unsigned long pll1_get_rate(struct clk *clk)
+ {
+ u32 control;
+@@ -138,6 +234,49 @@
+ return pll_get_rate(clk, control);
+ }
+
++static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
+{
++ u32 ctrl = 0;
++ unsigned long actual_rate;
++
++ actual_rate = pll_set_rate(clk, rate, &ctrl);
++
++ if (apply) {
++ if (actual_rate != rate)
++ return -EINVAL;
++ if (clk->users > 0)
++ return -EBUSY;
++ pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
++ clk->name, rate, actual_rate);
++ pm_writel(PLL1, ctrl);
++ }
+
++ return actual_rate;
+}
-+#endif
+
-+static int __init ocd_init(void)
++static int pll1_set_parent(struct clk *clk, struct clk *parent)
+{
-+ spin_lock_init(&ocd_lock);
-+ ocd_debugfs_init();
++ u32 ctrl;
++
++ if (clk->users > 0)
++ return -EBUSY;
++
++ ctrl = pm_readl(PLL1);
++ WARN_ON(ctrl & PM_BIT(PLLEN));
++
++ if (parent == &osc0)
++ ctrl &= ~PM_BIT(PLLOSC);
++ else if (parent == &osc1)
++ ctrl |= PM_BIT(PLLOSC);
++ else
++ return -EINVAL;
++
++ pm_writel(PLL1, ctrl);
++ clk->parent = parent;
++
+ return 0;
+}
-+arch_initcall(ocd_init);
---- a/arch/avr32/kernel/process.c
-+++ b/arch/avr32/kernel/process.c
-@@ -11,17 +11,18 @@
- #include <linux/fs.h>
- #include <linux/ptrace.h>
- #include <linux/reboot.h>
-+#include <linux/tick.h>
- #include <linux/uaccess.h>
- #include <linux/unistd.h>
-
- #include <asm/sysreg.h>
- #include <asm/ocd.h>
-
-+#include <asm/arch/pm.h>
+
- void (*pm_power_off)(void) = NULL;
- EXPORT_SYMBOL(pm_power_off);
-
--extern void cpu_idle_sleep(void);
--
/*
- * This file handles the architecture-dependent parts of process handling..
- */
-@@ -30,8 +31,10 @@
- {
- /* endless idle loop with no priority at all */
- while (1) {
-+ tick_nohz_stop_sched_tick();
- while (!need_resched())
- cpu_idle_sleep();
-+ tick_nohz_restart_sched_tick();
- preempt_enable_no_resched();
- schedule();
- preempt_disable();
-@@ -103,7 +106,7 @@
- */
- void exit_thread(void)
- {
-- /* nothing to do */
-+ ocd_disable(current);
- }
-
- void flush_thread(void)
-@@ -345,6 +348,10 @@
- p->thread.cpu_context.ksp = (unsigned long)childregs;
- p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
+ * The AT32AP7000 has five primary clock sources: One 32kHz
+ * oscillator, two crystal oscillators and two PLLs.
+@@ -166,7 +305,10 @@
+ };
+ static struct clk pll1 = {
+ .name = "pll1",
++ .mode = pll1_mode,
+ .get_rate = pll1_get_rate,
++ .set_rate = pll1_set_rate,
++ .set_parent = pll1_set_parent,
+ .parent = &osc0,
+ };
-+ clear_tsk_thread_flag(p, TIF_DEBUG);
-+ if ((clone_flags & CLONE_PTRACE) && test_thread_flag(TIF_DEBUG))
-+ ocd_enable(p);
-+
- return 0;
- }
+@@ -534,6 +676,14 @@
+ .users = 1,
+ .index = 3,
+ };
++static struct clk sdramc_clk = {
++ .name = "sdramc_clk",
++ .parent = &pbb_clk,
++ .mode = pbb_clk_mode,
++ .get_rate = pbb_clk_get_rate,
++ .users = 1,
++ .index = 14,
++};
---- a/arch/avr32/kernel/ptrace.c
-+++ b/arch/avr32/kernel/ptrace.c
-@@ -58,6 +58,7 @@
- {
- clear_tsk_thread_flag(child, TIF_SINGLE_STEP);
- clear_tsk_thread_flag(child, TIF_BREAKPOINT);
-+ ocd_disable(child);
+ static struct resource smc0_resource[] = {
+ PBMEM(0xfff03400),
+@@ -605,19 +755,32 @@
}
- /*
-@@ -144,10 +145,6 @@
- {
- int ret;
-
-- pr_debug("ptrace: Enabling monitor mode...\n");
-- ocd_write(DC, ocd_read(DC) | (1 << OCD_DC_MM_BIT)
-- | (1 << OCD_DC_DBE_BIT));
--
- switch (request) {
- /* Read the word at location addr in the child process */
- case PTRACE_PEEKTEXT:
---- a/arch/avr32/kernel/setup.c
-+++ b/arch/avr32/kernel/setup.c
-@@ -273,6 +273,8 @@
- printk(KERN_WARNING
- "Failed to allocate framebuffer memory\n");
- fbmem_size = 0;
-+ } else {
-+ memset(__va(fbmem_start), 0, fbmem_size);
- }
- }
-
---- a/arch/avr32/kernel/signal.c
-+++ b/arch/avr32/kernel/signal.c
-@@ -270,19 +270,12 @@
- if (!user_mode(regs))
- return 0;
-
-- if (try_to_freeze()) {
-- signr = 0;
-- if (!signal_pending(current))
-- goto no_signal;
-- }
--
- if (test_thread_flag(TIF_RESTORE_SIGMASK))
- oldset = ¤t->saved_sigmask;
- else if (!oldset)
- oldset = ¤t->blocked;
-
- signr = get_signal_to_deliver(&info, &ka, regs, NULL);
--no_signal:
- if (syscall) {
- switch (regs->r12) {
- case -ERESTART_RESTARTBLOCK:
---- a/arch/avr32/kernel/time.c
-+++ b/arch/avr32/kernel/time.c
-@@ -1,16 +1,12 @@
- /*
- * Copyright (C) 2004-2007 Atmel Corporation
- *
-- * Based on MIPS implementation arch/mips/kernel/time.c
-- * Copyright 2001 MontaVista Software Inc.
-- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
--
- #include <linux/clk.h>
--#include <linux/clocksource.h>
-+#include <linux/clockchips.h>
- #include <linux/time.h>
- #include <linux/module.h>
- #include <linux/interrupt.h>
-@@ -27,207 +23,133 @@
- #include <asm/io.h>
- #include <asm/sections.h>
+ /* --------------------------------------------------------------------
+- * System Timer/Counter (TC)
++ * Timer/Counter (TC)
+ * -------------------------------------------------------------------- */
+-static struct resource at32_systc0_resource[] = {
++
++static struct resource at32_tcb0_resource[] = {
+ PBMEM(0xfff00c00),
+ IRQ(22),
+ };
+-struct platform_device at32_systc0_device = {
+- .name = "systc",
++static struct platform_device at32_tcb0_device = {
++ .name = "atmel_tcb",
+ .id = 0,
+- .resource = at32_systc0_resource,
+- .num_resources = ARRAY_SIZE(at32_systc0_resource),
++ .resource = at32_tcb0_resource,
++ .num_resources = ARRAY_SIZE(at32_tcb0_resource),
++};
++DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
++
++static struct resource at32_tcb1_resource[] = {
++ PBMEM(0xfff01000),
++ IRQ(23),
++};
++static struct platform_device at32_tcb1_device = {
++ .name = "atmel_tcb",
++ .id = 1,
++ .resource = at32_tcb1_resource,
++ .num_resources = ARRAY_SIZE(at32_tcb1_resource),
+ };
+-DEV_CLK(pclk, at32_systc0, pbb, 3);
++DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
--/* how many counter cycles in a jiffy? */
--static u32 cycles_per_jiffy;
-+#include <asm/arch/pm.h>
+ /* --------------------------------------------------------------------
+ * PIO
+@@ -669,7 +832,8 @@
+ platform_device_register(&pdc_device);
+ platform_device_register(&dmaca0_device);
--/* the count value for the next timer interrupt */
--static u32 expirelo;
+- platform_device_register(&at32_systc0_device);
++ platform_device_register(&at32_tcb0_device);
++ platform_device_register(&at32_tcb1_device);
--cycle_t __weak read_cycle_count(void)
-+static cycle_t read_cycle_count(void)
- {
- return (cycle_t)sysreg_read(COUNT);
+ platform_device_register(&pio0_device);
+ platform_device_register(&pio1_device);
+@@ -679,6 +843,81 @@
}
--struct clocksource __weak clocksource_avr32 = {
-- .name = "avr32",
-- .rating = 350,
-+/*
-+ * The architectural cycle count registers are a fine clocksource unless
-+ * the system idle loop use sleep states like "idle": the CPU cycles
-+ * measured by COUNT (and COMPARE) don't happen during sleep states.
-+ * Their duration also changes if cpufreq changes the CPU clock rate.
-+ * So we rate the clocksource using COUNT as very low quality.
-+ */
-+static struct clocksource counter = {
-+ .name = "avr32_counter",
-+ .rating = 50,
- .read = read_cycle_count,
- .mask = CLOCKSOURCE_MASK(32),
- .shift = 16,
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+ /* --------------------------------------------------------------------
++ * PSIF
++ * -------------------------------------------------------------------- */
++static struct resource atmel_psif0_resource[] __initdata = {
++ {
++ .start = 0xffe03c00,
++ .end = 0xffe03cff,
++ .flags = IORESOURCE_MEM,
++ },
++ IRQ(18),
++};
++static struct clk atmel_psif0_pclk = {
++ .name = "pclk",
++ .parent = &pba_clk,
++ .mode = pba_clk_mode,
++ .get_rate = pba_clk_get_rate,
++ .index = 15,
++};
++
++static struct resource atmel_psif1_resource[] __initdata = {
++ {
++ .start = 0xffe03d00,
++ .end = 0xffe03dff,
++ .flags = IORESOURCE_MEM,
++ },
++ IRQ(18),
++};
++static struct clk atmel_psif1_pclk = {
++ .name = "pclk",
++ .parent = &pba_clk,
++ .mode = pba_clk_mode,
++ .get_rate = pba_clk_get_rate,
++ .index = 15,
++};
++
++struct platform_device *__init at32_add_device_psif(unsigned int id)
++{
++ struct platform_device *pdev;
++
++ if (!(id == 0 || id == 1))
++ return NULL;
++
++ pdev = platform_device_alloc("atmel_psif", id);
++ if (!pdev)
++ return NULL;
++
++ switch (id) {
++ case 0:
++ if (platform_device_add_resources(pdev, atmel_psif0_resource,
++ ARRAY_SIZE(atmel_psif0_resource)))
++ goto err_add_resources;
++ atmel_psif0_pclk.dev = &pdev->dev;
++ select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
++ select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
++ break;
++ case 1:
++ if (platform_device_add_resources(pdev, atmel_psif1_resource,
++ ARRAY_SIZE(atmel_psif1_resource)))
++ goto err_add_resources;
++ atmel_psif1_pclk.dev = &pdev->dev;
++ select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
++ select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
++ break;
++ default:
++ return NULL;
++ }
++
++ platform_device_add(pdev);
++ return pdev;
++
++err_add_resources:
++ platform_device_put(pdev);
++ return NULL;
++}
++
++/* --------------------------------------------------------------------
+ * USART
+ * -------------------------------------------------------------------- */
+
+@@ -951,7 +1190,8 @@
+ switch (id) {
+ case 0:
+ pdev = &atmel_spi0_device;
+- select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
++ /* pullup MISO so a level is always defined */
++ select_peripheral(PA(0), PERIPH_A, AT32_GPIOF_PULLUP);
+ select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
+ select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
+ at32_spi_setup_slaves(0, b, n, spi0_pins);
+@@ -959,7 +1199,8 @@
+
+ case 1:
+ pdev = &atmel_spi1_device;
+- select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
++ /* pullup MISO so a level is always defined */
++ select_peripheral(PB(0), PERIPH_B, AT32_GPIOF_PULLUP);
+ select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
+ select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
+ at32_spi_setup_slaves(1, b, n, spi1_pins);
+@@ -989,7 +1230,9 @@
+ .index = 2,
};
--irqreturn_t __weak timer_interrupt(int irq, void *dev_id);
--
--struct irqaction timer_irqaction = {
-- .handler = timer_interrupt,
-- .flags = IRQF_DISABLED,
-- .name = "timer",
--};
--
--/*
-- * By default we provide the null RTC ops
-- */
--static unsigned long null_rtc_get_time(void)
-+static irqreturn_t timer_interrupt(int irq, void *dev_id)
+-struct platform_device *__init at32_add_device_twi(unsigned int id)
++struct platform_device *__init at32_add_device_twi(unsigned int id,
++ struct i2c_board_info *b,
++ unsigned int n)
{
-- return mktime(2007, 1, 1, 0, 0, 0);
--}
--
--static int null_rtc_set_time(unsigned long sec)
--{
-- return 0;
--}
-+ struct clock_event_device *evdev = dev_id;
+ struct platform_device *pdev;
--static unsigned long (*rtc_get_time)(void) = null_rtc_get_time;
--static int (*rtc_set_time)(unsigned long) = null_rtc_set_time;
--
--static void avr32_timer_ack(void)
--{
-- u32 count;
--
-- /* Ack this timer interrupt and set the next one */
-- expirelo += cycles_per_jiffy;
-- /* setting COMPARE to 0 stops the COUNT-COMPARE */
-- if (expirelo == 0) {
-- sysreg_write(COMPARE, expirelo + 1);
-- } else {
-- sysreg_write(COMPARE, expirelo);
-- }
-+ /*
-+ * Disable the interrupt until the clockevent subsystem
-+ * reprograms it.
-+ */
-+ sysreg_write(COMPARE, 0);
+@@ -1009,6 +1252,9 @@
-- /* Check to see if we have missed any timer interrupts */
-- count = sysreg_read(COUNT);
-- if ((count - expirelo) < 0x7fffffff) {
-- expirelo = count + cycles_per_jiffy;
-- sysreg_write(COMPARE, expirelo);
-- }
-+ evdev->event_handler(evdev);
-+ return IRQ_HANDLED;
- }
+ atmel_twi0_pclk.dev = &pdev->dev;
--int __weak avr32_hpt_init(void)
--{
-- int ret;
-- unsigned long mult, shift, count_hz;
--
-- count_hz = clk_get_rate(boot_cpu_data.clk);
-- shift = clocksource_avr32.shift;
-- mult = clocksource_hz2mult(count_hz, shift);
-- clocksource_avr32.mult = mult;
--
-- {
-- u64 tmp;
--
-- tmp = TICK_NSEC;
-- tmp <<= shift;
-- tmp += mult / 2;
-- do_div(tmp, mult);
--
-- cycles_per_jiffy = tmp;
-- }
-+static struct irqaction timer_irqaction = {
-+ .handler = timer_interrupt,
-+ .flags = IRQF_TIMER | IRQF_DISABLED,
-+ .name = "avr32_comparator",
-+};
++ if (b)
++ i2c_register_board_info(id, b, n);
++
+ platform_device_add(pdev);
+ return pdev;
-- ret = setup_irq(0, &timer_irqaction);
-- if (ret) {
-- pr_debug("timer: could not request IRQ 0: %d\n", ret);
-- return -ENODEV;
-- }
-+static int comparator_next_event(unsigned long delta,
-+ struct clock_event_device *evdev)
-+{
-+ unsigned long flags;
+@@ -1032,7 +1278,8 @@
+ .index = 9,
+ };
-- printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
-- "%lu.%03lu MHz\n",
-- ((count_hz + 500) / 1000) / 1000,
-- ((count_hz + 500) / 1000) % 1000);
-+ raw_local_irq_save(flags);
+-struct platform_device *__init at32_add_device_mci(unsigned int id)
++struct platform_device *__init
++at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
+ {
+ struct platform_device *pdev;
-- return 0;
--}
-+ /* The time to read COUNT then update COMPARE must be less
-+ * than the min_delta_ns value for this clockevent source.
-+ */
-+ sysreg_write(COMPARE, (sysreg_read(COUNT) + delta) ? : 1);
+@@ -1041,11 +1288,15 @@
--/*
-- * Taken from MIPS c0_hpt_timer_init().
-- *
-- * The reason COUNT is written twice is probably to make sure we don't get any
-- * timer interrupts while we are messing with the counter.
-- */
--int __weak avr32_hpt_start(void)
--{
-- u32 count = sysreg_read(COUNT);
-- expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
-- sysreg_write(COUNT, expirelo - cycles_per_jiffy);
-- sysreg_write(COMPARE, expirelo);
-- sysreg_write(COUNT, count);
-+ raw_local_irq_restore(flags);
+ pdev = platform_device_alloc("atmel_mci", id);
+ if (!pdev)
+- return NULL;
++ goto fail;
- return 0;
+ if (platform_device_add_resources(pdev, atmel_mci0_resource,
+ ARRAY_SIZE(atmel_mci0_resource)))
+- goto err_add_resources;
++ goto fail;
++
++ if (data && platform_device_add_data(pdev, data,
++ sizeof(struct mci_platform_data)))
++ goto fail;
+
+ select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
+ select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
+@@ -1054,12 +1305,19 @@
+ select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
+ select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
+
++ if (data) {
++ if (data->detect_pin != GPIO_PIN_NONE)
++ at32_select_gpio(data->detect_pin, 0);
++ if (data->wp_pin != GPIO_PIN_NONE)
++ at32_select_gpio(data->wp_pin, 0);
++ }
++
+ atmel_mci0_pclk.dev = &pdev->dev;
+
+ platform_device_add(pdev);
+ return pdev;
+
+-err_add_resources:
++fail:
+ platform_device_put(pdev);
+ return NULL;
}
+@@ -1097,7 +1355,8 @@
--/*
-- * local_timer_interrupt() does profiling and process accounting on a
-- * per-CPU basis.
-- *
-- * In UP mode, it is invoked from the (global) timer_interrupt.
-- */
--void local_timer_interrupt(int irq, void *dev_id)
-+static void comparator_mode(enum clock_event_mode mode,
-+ struct clock_event_device *evdev)
+ struct platform_device *__init
+ at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
+- unsigned long fbmem_start, unsigned long fbmem_len)
++ unsigned long fbmem_start, unsigned long fbmem_len,
++ unsigned int pin_config)
{
-- if (current->pid)
-- profile_tick(CPU_PROFILING);
-- update_process_times(user_mode(get_irq_regs()));
-+ switch (mode) {
-+ case CLOCK_EVT_MODE_ONESHOT:
-+ pr_debug("%s: start\n", evdev->name);
-+ /* FALLTHROUGH */
-+ case CLOCK_EVT_MODE_RESUME:
-+ cpu_disable_idle_sleep();
-+ break;
-+ case CLOCK_EVT_MODE_UNUSED:
-+ case CLOCK_EVT_MODE_SHUTDOWN:
-+ sysreg_write(COMPARE, 0);
-+ pr_debug("%s: stop\n", evdev->name);
-+ cpu_enable_idle_sleep();
-+ break;
-+ default:
-+ BUG();
-+ }
- }
+ struct platform_device *pdev;
+ struct atmel_lcdfb_info *info;
+@@ -1124,37 +1383,77 @@
+ switch (id) {
+ case 0:
+ pdev = &atmel_lcdfb0_device;
+- select_peripheral(PC(19), PERIPH_A, 0); /* CC */
+- select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
+- select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
+- select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
+- select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
+- select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
+- select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
+- select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
+- select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
+- select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
+- select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
+- select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
+- select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
+- select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
+- select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
+- select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
+- select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
+- select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
+- select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
+- select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
+- select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
+- select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
+- select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
+- select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
+- select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
+- select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
+- select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
+- select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
+- select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
+- select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
+- select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
++
++ switch (pin_config) {
++ case 0:
++ select_peripheral(PC(19), PERIPH_A, 0); /* CC */
++ select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
++ select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
++ select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
++ select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
++ select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
++ select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
++ select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
++ select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
++ select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
++ select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
++ select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
++ select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
++ select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
++ select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
++ select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
++ select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
++ select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
++ select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
++ select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
++ select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
++ select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
++ select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
++ select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
++ select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
++ select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
++ select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
++ select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
++ select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
++ select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
++ select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
++ break;
++ case 1:
++ select_peripheral(PE(0), PERIPH_B, 0); /* CC */
++ select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
++ select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
++ select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
++ select_peripheral(PE(1), PERIPH_B, 0); /* DVAL */
++ select_peripheral(PE(2), PERIPH_B, 0); /* MODE */
++ select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
++ select_peripheral(PE(3), PERIPH_B, 0); /* DATA0 */
++ select_peripheral(PE(4), PERIPH_B, 0); /* DATA1 */
++ select_peripheral(PE(5), PERIPH_B, 0); /* DATA2 */
++ select_peripheral(PE(6), PERIPH_B, 0); /* DATA3 */
++ select_peripheral(PE(7), PERIPH_B, 0); /* DATA4 */
++ select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
++ select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
++ select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
++ select_peripheral(PE(8), PERIPH_B, 0); /* DATA8 */
++ select_peripheral(PE(9), PERIPH_B, 0); /* DATA9 */
++ select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
++ select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
++ select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
++ select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
++ select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
++ select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
++ select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
++ select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
++ select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
++ select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
++ select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
++ select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
++ select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
++ select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
++ break;
++ default:
++ goto err_invalid_id;
++ }
--irqreturn_t __weak timer_interrupt(int irq, void *dev_id)
--{
-- /* ack timer interrupt and try to set next interrupt */
-- avr32_timer_ack();
--
-- /*
-- * Call the generic timer interrupt handler
-- */
-- write_seqlock(&xtime_lock);
-- do_timer(1);
-- write_sequnlock(&xtime_lock);
--
-- /*
-- * In UP mode, we call local_timer_interrupt() to do profiling
-- * and process accounting.
-- *
-- * SMP is not supported yet.
-- */
-- local_timer_interrupt(irq, dev_id);
--
-- return IRQ_HANDLED;
--}
-+static struct clock_event_device comparator = {
-+ .name = "avr32_comparator",
-+ .features = CLOCK_EVT_FEAT_ONESHOT,
-+ .shift = 16,
-+ .rating = 50,
-+ .cpumask = CPU_MASK_CPU0,
-+ .set_next_event = comparator_next_event,
-+ .set_mode = comparator_mode,
-+};
+ clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
+ clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
+@@ -1351,9 +1650,39 @@
+ .index = 6,
+ };
- void __init time_init(void)
++#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
++ [idx] = { \
++ .name = nam, \
++ .index = idx, \
++ .fifo_size = maxpkt, \
++ .nr_banks = maxbk, \
++ .can_dma = dma, \
++ .can_isoc = isoc, \
++ }
++
++static struct usba_ep_data at32_usba_ep[] __initdata = {
++ EP("ep0", 0, 64, 1, 0, 0),
++ EP("ep1", 1, 512, 2, 1, 1),
++ EP("ep2", 2, 512, 2, 1, 1),
++ EP("ep3-int", 3, 64, 3, 1, 0),
++ EP("ep4-int", 4, 64, 3, 1, 0),
++ EP("ep5", 5, 1024, 3, 1, 1),
++ EP("ep6", 6, 1024, 3, 1, 1),
++};
++
++#undef EP
++
+ struct platform_device *__init
+ at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
{
-+ unsigned long counter_hz;
- int ret;
++ /*
++ * pdata doesn't have room for any endpoints, so we need to
++ * append room for the ones we need right after it.
++ */
++ struct {
++ struct usba_platform_data pdata;
++ struct usba_ep_data ep[7];
++ } usba_data;
+ struct platform_device *pdev;
-- /*
-- * Make sure we don't get any COMPARE interrupts before we can
-- * handle them.
-- */
-- sysreg_write(COMPARE, 0);
--
-- xtime.tv_sec = rtc_get_time();
-+ xtime.tv_sec = mktime(2007, 1, 1, 0, 0, 0);
- xtime.tv_nsec = 0;
+ if (id != 0)
+@@ -1367,13 +1696,20 @@
+ ARRAY_SIZE(usba0_resource)))
+ goto out_free_pdev;
- set_normalized_timespec(&wall_to_monotonic,
- -xtime.tv_sec, -xtime.tv_nsec);
+- if (data) {
+- if (platform_device_add_data(pdev, data, sizeof(*data)))
+- goto out_free_pdev;
++ if (data)
++ usba_data.pdata.vbus_pin = data->vbus_pin;
++ else
++ usba_data.pdata.vbus_pin = -EINVAL;
-- ret = avr32_hpt_init();
-- if (ret) {
-- pr_debug("timer: failed setup: %d\n", ret);
-- return;
+- if (data->vbus_pin != GPIO_PIN_NONE)
+- at32_select_gpio(data->vbus_pin, 0);
- }
-+ /* figure rate for counter */
-+ counter_hz = clk_get_rate(boot_cpu_data.clk);
-+ counter.mult = clocksource_hz2mult(counter_hz, counter.shift);
++ data = &usba_data.pdata;
++ data->num_ep = ARRAY_SIZE(at32_usba_ep);
++ memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
++
++ if (platform_device_add_data(pdev, data, sizeof(usba_data)))
++ goto out_free_pdev;
++
++ if (data->vbus_pin >= 0)
++ at32_select_gpio(data->vbus_pin, 0);
-- ret = clocksource_register(&clocksource_avr32);
-+ ret = clocksource_register(&counter);
- if (ret)
- pr_debug("timer: could not register clocksource: %d\n", ret);
+ usba0_pclk.dev = &pdev->dev;
+ usba0_hclk.dev = &pdev->dev;
+@@ -1526,6 +1862,58 @@
+ #endif
-- ret = avr32_hpt_start();
-- if (ret) {
-- pr_debug("timer: failed starting: %d\n", ret);
-- return;
-- }
--}
-+ /* setup COMPARE clockevent */
-+ comparator.mult = div_sc(counter_hz, NSEC_PER_SEC, comparator.shift);
-+ comparator.max_delta_ns = clockevent_delta2ns((u32)~0, &comparator);
-+ comparator.min_delta_ns = clockevent_delta2ns(50, &comparator) + 1;
+ /* --------------------------------------------------------------------
++ * NAND Flash / SmartMedia
++ * -------------------------------------------------------------------- */
++static struct resource smc_cs3_resource[] __initdata = {
++ {
++ .start = 0x0c000000,
++ .end = 0x0fffffff,
++ .flags = IORESOURCE_MEM,
++ }, {
++ .start = 0xfff03c00,
++ .end = 0xfff03fff,
++ .flags = IORESOURCE_MEM,
++ },
++};
++
++struct platform_device *__init
++at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
++{
++ struct platform_device *pdev;
++
++ if (id != 0 || !data)
++ return NULL;
++
++ pdev = platform_device_alloc("atmel_nand", id);
++ if (!pdev)
++ goto fail;
++
++ if (platform_device_add_resources(pdev, smc_cs3_resource,
++ ARRAY_SIZE(smc_cs3_resource)))
++ goto fail;
++
++ if (platform_device_add_data(pdev, data,
++ sizeof(struct atmel_nand_data)))
++ goto fail;
++
++ set_ebi_sfr_bits(HMATRIX_BIT(CS3A));
++ if (data->enable_pin)
++ at32_select_gpio(data->enable_pin,
++ AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
++ if (data->rdy_pin)
++ at32_select_gpio(data->rdy_pin, 0);
++ if (data->det_pin)
++ at32_select_gpio(data->det_pin, 0);
++
++ platform_device_add(pdev);
++ return pdev;
++
++fail:
++ platform_device_put(pdev);
++ return NULL;
++}
++
++/* --------------------------------------------------------------------
+ * AC97C
+ * -------------------------------------------------------------------- */
+ static struct resource atmel_ac97c0_resource[] __initdata = {
+@@ -1540,9 +1928,11 @@
+ .index = 10,
+ };
--static struct sysdev_class timer_class = {
-- set_kset_name("timer"),
--};
-+ sysreg_write(COMPARE, 0);
-+ timer_irqaction.dev_id = &comparator;
+-struct platform_device *__init at32_add_device_ac97c(unsigned int id)
++struct platform_device *__init
++at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
+ {
+ struct platform_device *pdev;
++ struct ac97c_platform_data _data;
--static struct sys_device timer_device = {
-- .id = 0,
-- .cls = &timer_class,
--};
-+ ret = setup_irq(0, &timer_irqaction);
-+ if (ret)
-+ pr_debug("timer: could not request IRQ 0: %d\n", ret);
-+ else {
-+ clockevents_register_device(&comparator);
+ if (id != 0)
+ return NULL;
+@@ -1553,19 +1943,37 @@
--static int __init init_timer_sysfs(void)
--{
-- int err = sysdev_class_register(&timer_class);
-- if (!err)
-- err = sysdev_register(&timer_device);
-- return err;
-+ pr_info("%s: irq 0, %lu.%03lu MHz\n", comparator.name,
-+ ((counter_hz + 500) / 1000) / 1000,
-+ ((counter_hz + 500) / 1000) % 1000);
-+ }
- }
--
--device_initcall(init_timer_sysfs);
---- a/arch/avr32/kernel/traps.c
-+++ b/arch/avr32/kernel/traps.c
-@@ -9,6 +9,7 @@
- #include <linux/bug.h>
- #include <linux/init.h>
- #include <linux/kallsyms.h>
-+#include <linux/kdebug.h>
- #include <linux/module.h>
- #include <linux/notifier.h>
- #include <linux/sched.h>
-@@ -107,9 +108,23 @@
+ if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
+ ARRAY_SIZE(atmel_ac97c0_resource)))
+- goto err_add_resources;
++ goto fail;
- asmlinkage void do_nmi(unsigned long ecr, struct pt_regs *regs)
- {
-- printk(KERN_ALERT "Got Non-Maskable Interrupt, dumping regs\n");
-- show_regs_log_lvl(regs, KERN_ALERT);
-- show_stack_log_lvl(current, regs->sp, regs, KERN_ALERT);
-+ int ret;
+- select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
+- select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
+- select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
+- select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
++ if (!data) {
++ data = &_data;
++ memset(data, 0, sizeof(struct ac97c_platform_data));
++ data->reset_pin = GPIO_PIN_NONE;
++ }
+
-+ nmi_enter();
++ data->dma_rx_periph_id = 3;
++ data->dma_tx_periph_id = 4;
++ data->dma_controller_id = 0;
+
-+ ret = notify_die(DIE_NMI, "NMI", regs, 0, ecr, SIGINT);
-+ switch (ret) {
-+ case NOTIFY_OK:
-+ case NOTIFY_STOP:
-+ return;
-+ case NOTIFY_BAD:
-+ die("Fatal Non-Maskable Interrupt", regs, SIGINT);
-+ default:
-+ break;
-+ }
++ if (platform_device_add_data(pdev, data,
++ sizeof(struct ac97c_platform_data)))
++ goto fail;
+
-+ printk(KERN_ALERT "Got NMI, but nobody cared. Disabling...\n");
-+ nmi_disable();
- }
++ select_peripheral(PB(20), PERIPH_B, 0); /* SDO */
++ select_peripheral(PB(21), PERIPH_B, 0); /* SYNC */
++ select_peripheral(PB(22), PERIPH_B, 0); /* SCLK */
++ select_peripheral(PB(23), PERIPH_B, 0); /* SDI */
++
++ /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
++ if (data->reset_pin != GPIO_PIN_NONE)
++ at32_select_gpio(data->reset_pin, 0);
- asmlinkage void do_critical_exception(unsigned long ecr, struct pt_regs *regs)
---- a/arch/avr32/mach-at32ap/at32ap7000.c
-+++ /dev/null
-@@ -1,1730 +0,0 @@
--/*
-- * Copyright (C) 2005-2006 Atmel Corporation
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--#include <linux/clk.h>
--#include <linux/fb.h>
--#include <linux/init.h>
--#include <linux/platform_device.h>
--#include <linux/dma-mapping.h>
--#include <linux/spi/spi.h>
--
--#include <asm/io.h>
--
--#include <asm/arch/at32ap7000.h>
--#include <asm/arch/board.h>
--#include <asm/arch/portmux.h>
--
--#include <video/atmel_lcdc.h>
--
--#include "clock.h"
--#include "hmatrix.h"
--#include "pio.h"
--#include "pm.h"
--
--
--#define PBMEM(base) \
-- { \
-- .start = base, \
-- .end = base + 0x3ff, \
-- .flags = IORESOURCE_MEM, \
-- }
--#define IRQ(num) \
-- { \
-- .start = num, \
-- .end = num, \
-- .flags = IORESOURCE_IRQ, \
-- }
--#define NAMED_IRQ(num, _name) \
-- { \
-- .start = num, \
-- .end = num, \
-- .name = _name, \
-- .flags = IORESOURCE_IRQ, \
-- }
--
--/* REVISIT these assume *every* device supports DMA, but several
-- * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
-- */
--#define DEFINE_DEV(_name, _id) \
--static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
--static struct platform_device _name##_id##_device = { \
-- .name = #_name, \
-- .id = _id, \
-- .dev = { \
-- .dma_mask = &_name##_id##_dma_mask, \
-- .coherent_dma_mask = DMA_32BIT_MASK, \
-- }, \
-- .resource = _name##_id##_resource, \
-- .num_resources = ARRAY_SIZE(_name##_id##_resource), \
--}
--#define DEFINE_DEV_DATA(_name, _id) \
--static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
--static struct platform_device _name##_id##_device = { \
-- .name = #_name, \
-- .id = _id, \
-- .dev = { \
-- .dma_mask = &_name##_id##_dma_mask, \
-- .platform_data = &_name##_id##_data, \
-- .coherent_dma_mask = DMA_32BIT_MASK, \
-- }, \
-- .resource = _name##_id##_resource, \
-- .num_resources = ARRAY_SIZE(_name##_id##_resource), \
--}
--
--#define select_peripheral(pin, periph, flags) \
-- at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
--
--#define DEV_CLK(_name, devname, bus, _index) \
--static struct clk devname##_##_name = { \
-- .name = #_name, \
-- .dev = &devname##_device.dev, \
-- .parent = &bus##_clk, \
-- .mode = bus##_clk_mode, \
-- .get_rate = bus##_clk_get_rate, \
-- .index = _index, \
--}
--
--static DEFINE_SPINLOCK(pm_lock);
--
--unsigned long at32ap7000_osc_rates[3] = {
-- [0] = 32768,
-- /* FIXME: these are ATSTK1002-specific */
-- [1] = 20000000,
-- [2] = 12000000,
--};
--
--static unsigned long osc_get_rate(struct clk *clk)
--{
-- return at32ap7000_osc_rates[clk->index];
--}
--
--static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
--{
-- unsigned long div, mul, rate;
--
-- if (!(control & PM_BIT(PLLEN)))
-- return 0;
--
-- div = PM_BFEXT(PLLDIV, control) + 1;
-- mul = PM_BFEXT(PLLMUL, control) + 1;
--
-- rate = clk->parent->get_rate(clk->parent);
-- rate = (rate + div / 2) / div;
-- rate *= mul;
--
-- return rate;
--}
--
--static unsigned long pll0_get_rate(struct clk *clk)
--{
-- u32 control;
--
-- control = pm_readl(PLL0);
--
-- return pll_get_rate(clk, control);
--}
--
--static unsigned long pll1_get_rate(struct clk *clk)
--{
-- u32 control;
--
-- control = pm_readl(PLL1);
--
-- return pll_get_rate(clk, control);
--}
--
--/*
-- * The AT32AP7000 has five primary clock sources: One 32kHz
-- * oscillator, two crystal oscillators and two PLLs.
-- */
--static struct clk osc32k = {
-- .name = "osc32k",
-- .get_rate = osc_get_rate,
-- .users = 1,
-- .index = 0,
--};
--static struct clk osc0 = {
-- .name = "osc0",
-- .get_rate = osc_get_rate,
-- .users = 1,
-- .index = 1,
--};
--static struct clk osc1 = {
-- .name = "osc1",
-- .get_rate = osc_get_rate,
-- .index = 2,
--};
--static struct clk pll0 = {
-- .name = "pll0",
-- .get_rate = pll0_get_rate,
-- .parent = &osc0,
--};
--static struct clk pll1 = {
-- .name = "pll1",
-- .get_rate = pll1_get_rate,
-- .parent = &osc0,
--};
--
--/*
-- * The main clock can be either osc0 or pll0. The boot loader may
-- * have chosen one for us, so we don't really know which one until we
-- * have a look at the SM.
-- */
--static struct clk *main_clock;
--
--/*
-- * Synchronous clocks are generated from the main clock. The clocks
-- * must satisfy the constraint
-- * fCPU >= fHSB >= fPB
-- * i.e. each clock must not be faster than its parent.
-- */
--static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
--{
-- return main_clock->get_rate(main_clock) >> shift;
--};
--
--static void cpu_clk_mode(struct clk *clk, int enabled)
--{
-- unsigned long flags;
-- u32 mask;
--
-- spin_lock_irqsave(&pm_lock, flags);
-- mask = pm_readl(CPU_MASK);
-- if (enabled)
-- mask |= 1 << clk->index;
-- else
-- mask &= ~(1 << clk->index);
-- pm_writel(CPU_MASK, mask);
-- spin_unlock_irqrestore(&pm_lock, flags);
--}
--
--static unsigned long cpu_clk_get_rate(struct clk *clk)
--{
-- unsigned long cksel, shift = 0;
--
-- cksel = pm_readl(CKSEL);
-- if (cksel & PM_BIT(CPUDIV))
-- shift = PM_BFEXT(CPUSEL, cksel) + 1;
--
-- return bus_clk_get_rate(clk, shift);
--}
--
--static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
--{
-- u32 control;
-- unsigned long parent_rate, child_div, actual_rate, div;
--
-- parent_rate = clk->parent->get_rate(clk->parent);
-- control = pm_readl(CKSEL);
--
-- if (control & PM_BIT(HSBDIV))
-- child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
-- else
-- child_div = 1;
--
-- if (rate > 3 * (parent_rate / 4) || child_div == 1) {
-- actual_rate = parent_rate;
-- control &= ~PM_BIT(CPUDIV);
-- } else {
-- unsigned int cpusel;
-- div = (parent_rate + rate / 2) / rate;
-- if (div > child_div)
-- div = child_div;
-- cpusel = (div > 1) ? (fls(div) - 2) : 0;
-- control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
-- actual_rate = parent_rate / (1 << (cpusel + 1));
-- }
--
-- pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
-- clk->name, rate, actual_rate);
--
-- if (apply)
-- pm_writel(CKSEL, control);
--
-- return actual_rate;
--}
--
--static void hsb_clk_mode(struct clk *clk, int enabled)
--{
-- unsigned long flags;
-- u32 mask;
--
-- spin_lock_irqsave(&pm_lock, flags);
-- mask = pm_readl(HSB_MASK);
-- if (enabled)
-- mask |= 1 << clk->index;
-- else
-- mask &= ~(1 << clk->index);
-- pm_writel(HSB_MASK, mask);
-- spin_unlock_irqrestore(&pm_lock, flags);
--}
--
--static unsigned long hsb_clk_get_rate(struct clk *clk)
--{
-- unsigned long cksel, shift = 0;
--
-- cksel = pm_readl(CKSEL);
-- if (cksel & PM_BIT(HSBDIV))
-- shift = PM_BFEXT(HSBSEL, cksel) + 1;
--
-- return bus_clk_get_rate(clk, shift);
--}
--
--static void pba_clk_mode(struct clk *clk, int enabled)
--{
-- unsigned long flags;
-- u32 mask;
--
-- spin_lock_irqsave(&pm_lock, flags);
-- mask = pm_readl(PBA_MASK);
-- if (enabled)
-- mask |= 1 << clk->index;
-- else
-- mask &= ~(1 << clk->index);
-- pm_writel(PBA_MASK, mask);
-- spin_unlock_irqrestore(&pm_lock, flags);
--}
--
--static unsigned long pba_clk_get_rate(struct clk *clk)
--{
-- unsigned long cksel, shift = 0;
--
-- cksel = pm_readl(CKSEL);
-- if (cksel & PM_BIT(PBADIV))
-- shift = PM_BFEXT(PBASEL, cksel) + 1;
--
-- return bus_clk_get_rate(clk, shift);
--}
--
--static void pbb_clk_mode(struct clk *clk, int enabled)
--{
-- unsigned long flags;
-- u32 mask;
--
-- spin_lock_irqsave(&pm_lock, flags);
-- mask = pm_readl(PBB_MASK);
-- if (enabled)
-- mask |= 1 << clk->index;
-- else
-- mask &= ~(1 << clk->index);
-- pm_writel(PBB_MASK, mask);
-- spin_unlock_irqrestore(&pm_lock, flags);
--}
--
--static unsigned long pbb_clk_get_rate(struct clk *clk)
--{
-- unsigned long cksel, shift = 0;
--
-- cksel = pm_readl(CKSEL);
-- if (cksel & PM_BIT(PBBDIV))
-- shift = PM_BFEXT(PBBSEL, cksel) + 1;
--
-- return bus_clk_get_rate(clk, shift);
--}
--
--static struct clk cpu_clk = {
-- .name = "cpu",
-- .get_rate = cpu_clk_get_rate,
-- .set_rate = cpu_clk_set_rate,
-- .users = 1,
--};
--static struct clk hsb_clk = {
-- .name = "hsb",
-- .parent = &cpu_clk,
-- .get_rate = hsb_clk_get_rate,
--};
--static struct clk pba_clk = {
-- .name = "pba",
-- .parent = &hsb_clk,
-- .mode = hsb_clk_mode,
-- .get_rate = pba_clk_get_rate,
-- .index = 1,
--};
--static struct clk pbb_clk = {
-- .name = "pbb",
-- .parent = &hsb_clk,
-- .mode = hsb_clk_mode,
-- .get_rate = pbb_clk_get_rate,
-- .users = 1,
-- .index = 2,
--};
--
--/* --------------------------------------------------------------------
-- * Generic Clock operations
-- * -------------------------------------------------------------------- */
--
--static void genclk_mode(struct clk *clk, int enabled)
--{
-- u32 control;
--
-- control = pm_readl(GCCTRL(clk->index));
-- if (enabled)
-- control |= PM_BIT(CEN);
-- else
-- control &= ~PM_BIT(CEN);
-- pm_writel(GCCTRL(clk->index), control);
--}
--
--static unsigned long genclk_get_rate(struct clk *clk)
--{
-- u32 control;
-- unsigned long div = 1;
--
-- control = pm_readl(GCCTRL(clk->index));
-- if (control & PM_BIT(DIVEN))
-- div = 2 * (PM_BFEXT(DIV, control) + 1);
--
-- return clk->parent->get_rate(clk->parent) / div;
--}
--
--static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
--{
-- u32 control;
-- unsigned long parent_rate, actual_rate, div;
--
-- parent_rate = clk->parent->get_rate(clk->parent);
-- control = pm_readl(GCCTRL(clk->index));
--
-- if (rate > 3 * parent_rate / 4) {
-- actual_rate = parent_rate;
-- control &= ~PM_BIT(DIVEN);
-- } else {
-- div = (parent_rate + rate) / (2 * rate) - 1;
-- control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
-- actual_rate = parent_rate / (2 * (div + 1));
-- }
--
-- dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
-- clk->name, rate, actual_rate);
--
-- if (apply)
-- pm_writel(GCCTRL(clk->index), control);
--
-- return actual_rate;
--}
--
--int genclk_set_parent(struct clk *clk, struct clk *parent)
--{
-- u32 control;
--
-- dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
-- clk->name, parent->name, clk->parent->name);
--
-- control = pm_readl(GCCTRL(clk->index));
--
-- if (parent == &osc1 || parent == &pll1)
-- control |= PM_BIT(OSCSEL);
-- else if (parent == &osc0 || parent == &pll0)
-- control &= ~PM_BIT(OSCSEL);
-- else
-- return -EINVAL;
--
-- if (parent == &pll0 || parent == &pll1)
-- control |= PM_BIT(PLLSEL);
-- else
-- control &= ~PM_BIT(PLLSEL);
--
-- pm_writel(GCCTRL(clk->index), control);
-- clk->parent = parent;
--
-- return 0;
--}
--
--static void __init genclk_init_parent(struct clk *clk)
+ atmel_ac97c0_pclk.dev = &pdev->dev;
+
+ platform_device_add(pdev);
+ return pdev;
+
+-err_add_resources:
++fail:
+ platform_device_put(pdev);
+ return NULL;
+ }
+@@ -1683,6 +2091,7 @@
+ &hmatrix_clk,
+ &ebi_clk,
+ &hramc_clk,
++ &sdramc_clk,
+ &smc0_pclk,
+ &smc0_mck,
+ &pdc_hclk,
+@@ -1694,7 +2103,10 @@
+ &pio2_mck,
+ &pio3_mck,
+ &pio4_mck,
+- &at32_systc0_pclk,
++ &at32_tcb0_t0_clk,
++ &at32_tcb1_t0_clk,
++ &atmel_psif0_pclk,
++ &atmel_psif1_pclk,
+ &atmel_usart0_usart,
+ &atmel_usart1_usart,
+ &atmel_usart2_usart,
+@@ -1730,16 +2142,7 @@
+ };
+ unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
+
+-void __init at32_portmux_init(void)
-{
-- u32 control;
-- struct clk *parent;
--
-- BUG_ON(clk->index > 7);
--
-- control = pm_readl(GCCTRL(clk->index));
-- if (control & PM_BIT(OSCSEL))
-- parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
-- else
-- parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
--
-- clk->parent = parent;
+- at32_init_pio(&pio0_device);
+- at32_init_pio(&pio1_device);
+- at32_init_pio(&pio2_device);
+- at32_init_pio(&pio3_device);
+- at32_init_pio(&pio4_device);
-}
-
--/* --------------------------------------------------------------------
-- * System peripherals
-- * -------------------------------------------------------------------- */
--static struct resource at32_pm0_resource[] = {
-- {
-- .start = 0xfff00000,
-- .end = 0xfff0007f,
-- .flags = IORESOURCE_MEM,
-- },
-- IRQ(20),
--};
--
--static struct resource at32ap700x_rtc0_resource[] = {
-- {
-- .start = 0xfff00080,
-- .end = 0xfff000af,
-- .flags = IORESOURCE_MEM,
-- },
-- IRQ(21),
--};
--
--static struct resource at32_wdt0_resource[] = {
-- {
-- .start = 0xfff000b0,
-- .end = 0xfff000cf,
-- .flags = IORESOURCE_MEM,
-- },
--};
--
--static struct resource at32_eic0_resource[] = {
-- {
-- .start = 0xfff00100,
-- .end = 0xfff0013f,
-- .flags = IORESOURCE_MEM,
-- },
-- IRQ(19),
--};
--
--DEFINE_DEV(at32_pm, 0);
--DEFINE_DEV(at32ap700x_rtc, 0);
--DEFINE_DEV(at32_wdt, 0);
--DEFINE_DEV(at32_eic, 0);
--
--/*
-- * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
-- * is always running.
-- */
--static struct clk at32_pm_pclk = {
-- .name = "pclk",
-- .dev = &at32_pm0_device.dev,
-- .parent = &pbb_clk,
-- .mode = pbb_clk_mode,
-- .get_rate = pbb_clk_get_rate,
-- .users = 1,
-- .index = 0,
--};
--
--static struct resource intc0_resource[] = {
-- PBMEM(0xfff00400),
--};
--struct platform_device at32_intc0_device = {
-- .name = "intc",
-- .id = 0,
-- .resource = intc0_resource,
-- .num_resources = ARRAY_SIZE(intc0_resource),
--};
--DEV_CLK(pclk, at32_intc0, pbb, 1);
--
--static struct clk ebi_clk = {
-- .name = "ebi",
-- .parent = &hsb_clk,
-- .mode = hsb_clk_mode,
-- .get_rate = hsb_clk_get_rate,
-- .users = 1,
--};
--static struct clk hramc_clk = {
-- .name = "hramc",
-- .parent = &hsb_clk,
-- .mode = hsb_clk_mode,
-- .get_rate = hsb_clk_get_rate,
-- .users = 1,
-- .index = 3,
--};
--
--static struct resource smc0_resource[] = {
-- PBMEM(0xfff03400),
--};
--DEFINE_DEV(smc, 0);
--DEV_CLK(pclk, smc0, pbb, 13);
--DEV_CLK(mck, smc0, hsb, 0);
--
--static struct platform_device pdc_device = {
-- .name = "pdc",
-- .id = 0,
--};
--DEV_CLK(hclk, pdc, hsb, 4);
--DEV_CLK(pclk, pdc, pba, 16);
--
--static struct clk pico_clk = {
-- .name = "pico",
-- .parent = &cpu_clk,
-- .mode = cpu_clk_mode,
-- .get_rate = cpu_clk_get_rate,
-- .users = 1,
--};
--
--static struct resource dmaca0_resource[] = {
-- {
-- .start = 0xff200000,
-- .end = 0xff20ffff,
-- .flags = IORESOURCE_MEM,
-- },
-- IRQ(2),
--};
--DEFINE_DEV(dmaca, 0);
--DEV_CLK(hclk, dmaca0, hsb, 10);
--
--/* --------------------------------------------------------------------
-- * HMATRIX
-- * -------------------------------------------------------------------- */
--
--static struct clk hmatrix_clk = {
-- .name = "hmatrix_clk",
-- .parent = &pbb_clk,
-- .mode = pbb_clk_mode,
-- .get_rate = pbb_clk_get_rate,
-- .index = 2,
-- .users = 1,
--};
--#define HMATRIX_BASE ((void __iomem *)0xfff00800)
--
--#define hmatrix_readl(reg) \
-- __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
--#define hmatrix_writel(reg,value) \
-- __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
--
--/*
-- * Set bits in the HMATRIX Special Function Register (SFR) used by the
-- * External Bus Interface (EBI). This can be used to enable special
-- * features like CompactFlash support, NAND Flash support, etc. on
-- * certain chipselects.
-- */
--static inline void set_ebi_sfr_bits(u32 mask)
--{
-- u32 sfr;
+-void __init at32_clock_init(void)
++void __init setup_platform(void)
+ {
+ u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
+ int i;
+@@ -1794,4 +2197,36 @@
+ pm_writel(HSB_MASK, hsb_mask);
+ pm_writel(PBA_MASK, pba_mask);
+ pm_writel(PBB_MASK, pbb_mask);
++
++ /* Initialize the port muxes */
++ at32_init_pio(&pio0_device);
++ at32_init_pio(&pio1_device);
++ at32_init_pio(&pio2_device);
++ at32_init_pio(&pio3_device);
++ at32_init_pio(&pio4_device);
++}
++
++struct gen_pool *sram_pool;
++
++static int __init sram_init(void)
++{
++ struct gen_pool *pool;
++
++ /* 1KiB granularity */
++ pool = gen_pool_create(10, -1);
++ if (!pool)
++ goto fail;
++
++ if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
++ goto err_pool_add;
++
++ sram_pool = pool;
++ return 0;
++
++err_pool_add:
++ gen_pool_destroy(pool);
++fail:
++ pr_err("Failed to create SRAM pool\n");
++ return -ENOMEM;
+ }
++core_initcall(sram_init);
+--- a/arch/avr32/mach-at32ap/cpufreq.c
++++ b/arch/avr32/mach-at32ap/cpufreq.c
+@@ -108,5 +108,4 @@
+ {
+ return cpufreq_register_driver(&at32_driver);
+ }
-
-- clk_enable(&hmatrix_clk);
-- sfr = hmatrix_readl(SFR4);
-- sfr |= mask;
-- hmatrix_writel(SFR4, sfr);
-- clk_disable(&hmatrix_clk);
--}
--
--/* --------------------------------------------------------------------
-- * System Timer/Counter (TC)
-- * -------------------------------------------------------------------- */
--static struct resource at32_systc0_resource[] = {
-- PBMEM(0xfff00c00),
-- IRQ(22),
--};
--struct platform_device at32_systc0_device = {
-- .name = "systc",
-- .id = 0,
-- .resource = at32_systc0_resource,
-- .num_resources = ARRAY_SIZE(at32_systc0_resource),
--};
--DEV_CLK(pclk, at32_systc0, pbb, 3);
--
--/* --------------------------------------------------------------------
-- * PIO
-- * -------------------------------------------------------------------- */
--
--static struct resource pio0_resource[] = {
-- PBMEM(0xffe02800),
-- IRQ(13),
--};
--DEFINE_DEV(pio, 0);
--DEV_CLK(mck, pio0, pba, 10);
--
--static struct resource pio1_resource[] = {
-- PBMEM(0xffe02c00),
-- IRQ(14),
--};
--DEFINE_DEV(pio, 1);
--DEV_CLK(mck, pio1, pba, 11);
--
--static struct resource pio2_resource[] = {
-- PBMEM(0xffe03000),
-- IRQ(15),
--};
--DEFINE_DEV(pio, 2);
--DEV_CLK(mck, pio2, pba, 12);
--
--static struct resource pio3_resource[] = {
-- PBMEM(0xffe03400),
-- IRQ(16),
--};
--DEFINE_DEV(pio, 3);
--DEV_CLK(mck, pio3, pba, 13);
--
--static struct resource pio4_resource[] = {
-- PBMEM(0xffe03800),
-- IRQ(17),
--};
--DEFINE_DEV(pio, 4);
--DEV_CLK(mck, pio4, pba, 14);
--
--void __init at32_add_system_devices(void)
--{
-- platform_device_register(&at32_pm0_device);
-- platform_device_register(&at32_intc0_device);
-- platform_device_register(&at32ap700x_rtc0_device);
-- platform_device_register(&at32_wdt0_device);
-- platform_device_register(&at32_eic0_device);
-- platform_device_register(&smc0_device);
-- platform_device_register(&pdc_device);
-- platform_device_register(&dmaca0_device);
--
-- platform_device_register(&at32_systc0_device);
--
-- platform_device_register(&pio0_device);
-- platform_device_register(&pio1_device);
-- platform_device_register(&pio2_device);
-- platform_device_register(&pio3_device);
-- platform_device_register(&pio4_device);
--}
--
--/* --------------------------------------------------------------------
-- * USART
-- * -------------------------------------------------------------------- */
--
--static struct atmel_uart_data atmel_usart0_data = {
-- .use_dma_tx = 1,
-- .use_dma_rx = 1,
--};
--static struct resource atmel_usart0_resource[] = {
-- PBMEM(0xffe00c00),
-- IRQ(6),
--};
--DEFINE_DEV_DATA(atmel_usart, 0);
--DEV_CLK(usart, atmel_usart0, pba, 3);
--
--static struct atmel_uart_data atmel_usart1_data = {
-- .use_dma_tx = 1,
-- .use_dma_rx = 1,
--};
--static struct resource atmel_usart1_resource[] = {
-- PBMEM(0xffe01000),
-- IRQ(7),
--};
--DEFINE_DEV_DATA(atmel_usart, 1);
--DEV_CLK(usart, atmel_usart1, pba, 4);
--
--static struct atmel_uart_data atmel_usart2_data = {
-- .use_dma_tx = 1,
-- .use_dma_rx = 1,
--};
--static struct resource atmel_usart2_resource[] = {
-- PBMEM(0xffe01400),
-- IRQ(8),
--};
--DEFINE_DEV_DATA(atmel_usart, 2);
--DEV_CLK(usart, atmel_usart2, pba, 5);
--
--static struct atmel_uart_data atmel_usart3_data = {
-- .use_dma_tx = 1,
-- .use_dma_rx = 1,
--};
--static struct resource atmel_usart3_resource[] = {
-- PBMEM(0xffe01800),
-- IRQ(9),
--};
--DEFINE_DEV_DATA(atmel_usart, 3);
--DEV_CLK(usart, atmel_usart3, pba, 6);
--
--static inline void configure_usart0_pins(void)
--{
-- select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
-- select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
--}
--
--static inline void configure_usart1_pins(void)
--{
-- select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
-- select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
--}
--
--static inline void configure_usart2_pins(void)
--{
-- select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
-- select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
--}
--
--static inline void configure_usart3_pins(void)
--{
-- select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
-- select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
--}
--
--static struct platform_device *__initdata at32_usarts[4];
--
--void __init at32_map_usart(unsigned int hw_id, unsigned int line)
--{
-- struct platform_device *pdev;
--
-- switch (hw_id) {
-- case 0:
-- pdev = &atmel_usart0_device;
-- configure_usart0_pins();
-- break;
-- case 1:
-- pdev = &atmel_usart1_device;
-- configure_usart1_pins();
-- break;
-- case 2:
-- pdev = &atmel_usart2_device;
-- configure_usart2_pins();
-- break;
-- case 3:
-- pdev = &atmel_usart3_device;
-- configure_usart3_pins();
-- break;
-- default:
-- return;
-- }
--
-- if (PXSEG(pdev->resource[0].start) == P4SEG) {
-- /* Addresses in the P4 segment are permanently mapped 1:1 */
-- struct atmel_uart_data *data = pdev->dev.platform_data;
-- data->regs = (void __iomem *)pdev->resource[0].start;
-- }
--
-- pdev->id = line;
-- at32_usarts[line] = pdev;
--}
--
--struct platform_device *__init at32_add_device_usart(unsigned int id)
--{
-- platform_device_register(at32_usarts[id]);
-- return at32_usarts[id];
--}
--
--struct platform_device *atmel_default_console_device;
--
--void __init at32_setup_serial_console(unsigned int usart_id)
--{
-- atmel_default_console_device = at32_usarts[usart_id];
--}
--
--/* --------------------------------------------------------------------
-- * Ethernet
-- * -------------------------------------------------------------------- */
--
--static struct eth_platform_data macb0_data;
--static struct resource macb0_resource[] = {
-- PBMEM(0xfff01800),
-- IRQ(25),
--};
--DEFINE_DEV_DATA(macb, 0);
--DEV_CLK(hclk, macb0, hsb, 8);
--DEV_CLK(pclk, macb0, pbb, 6);
--
--static struct eth_platform_data macb1_data;
--static struct resource macb1_resource[] = {
-- PBMEM(0xfff01c00),
-- IRQ(26),
--};
--DEFINE_DEV_DATA(macb, 1);
--DEV_CLK(hclk, macb1, hsb, 9);
--DEV_CLK(pclk, macb1, pbb, 7);
--
--struct platform_device *__init
--at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
--{
-- struct platform_device *pdev;
--
-- switch (id) {
-- case 0:
-- pdev = &macb0_device;
--
-- select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
-- select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
-- select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
-- select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
-- select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
-- select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
-- select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
-- select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
-- select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
-- select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
--
-- if (!data->is_rmii) {
-- select_peripheral(PC(0), PERIPH_A, 0); /* COL */
-- select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
-- select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
-- select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
-- select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
-- select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
-- select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
-- select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
-- select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
-- }
-- break;
--
-- case 1:
-- pdev = &macb1_device;
--
-- select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
-- select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
-- select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
-- select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
-- select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
-- select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
-- select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
-- select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
-- select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
-- select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
--
-- if (!data->is_rmii) {
-- select_peripheral(PC(19), PERIPH_B, 0); /* COL */
-- select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
-- select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
-- select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
-- select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
-- select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
-- select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
-- select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
-- select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
-- }
-- break;
--
-- default:
-- return NULL;
-- }
--
-- memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
-- platform_device_register(pdev);
--
-- return pdev;
--}
--
--/* --------------------------------------------------------------------
-- * SPI
-- * -------------------------------------------------------------------- */
--static struct resource atmel_spi0_resource[] = {
-- PBMEM(0xffe00000),
-- IRQ(3),
--};
--DEFINE_DEV(atmel_spi, 0);
--DEV_CLK(spi_clk, atmel_spi0, pba, 0);
--
--static struct resource atmel_spi1_resource[] = {
-- PBMEM(0xffe00400),
-- IRQ(4),
--};
--DEFINE_DEV(atmel_spi, 1);
--DEV_CLK(spi_clk, atmel_spi1, pba, 1);
--
--static void __init
--at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
-- unsigned int n, const u8 *pins)
--{
-- unsigned int pin, mode;
--
-- for (; n; n--, b++) {
-- b->bus_num = bus_num;
-- if (b->chip_select >= 4)
-- continue;
-- pin = (unsigned)b->controller_data;
-- if (!pin) {
-- pin = pins[b->chip_select];
-- b->controller_data = (void *)pin;
-- }
-- mode = AT32_GPIOF_OUTPUT;
-- if (!(b->mode & SPI_CS_HIGH))
-- mode |= AT32_GPIOF_HIGH;
-- at32_select_gpio(pin, mode);
-- }
--}
--
--struct platform_device *__init
--at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
--{
-- /*
-- * Manage the chipselects as GPIOs, normally using the same pins
-- * the SPI controller expects; but boards can use other pins.
-- */
-- static u8 __initdata spi0_pins[] =
-- { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
-- GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
-- static u8 __initdata spi1_pins[] =
-- { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
-- GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
-- struct platform_device *pdev;
--
-- switch (id) {
-- case 0:
-- pdev = &atmel_spi0_device;
-- select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
-- select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
-- select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
-- at32_spi_setup_slaves(0, b, n, spi0_pins);
-- break;
--
-- case 1:
-- pdev = &atmel_spi1_device;
-- select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
-- select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
-- select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
-- at32_spi_setup_slaves(1, b, n, spi1_pins);
-- break;
--
-- default:
-- return NULL;
-- }
--
-- spi_register_board_info(b, n);
-- platform_device_register(pdev);
-- return pdev;
--}
--
--/* --------------------------------------------------------------------
-- * TWI
-- * -------------------------------------------------------------------- */
--static struct resource atmel_twi0_resource[] __initdata = {
-- PBMEM(0xffe00800),
-- IRQ(5),
--};
--static struct clk atmel_twi0_pclk = {
-- .name = "twi_pclk",
-- .parent = &pba_clk,
-- .mode = pba_clk_mode,
-- .get_rate = pba_clk_get_rate,
-- .index = 2,
--};
--
--struct platform_device *__init at32_add_device_twi(unsigned int id)
--{
-- struct platform_device *pdev;
--
-- if (id != 0)
-- return NULL;
--
-- pdev = platform_device_alloc("atmel_twi", id);
-- if (!pdev)
-- return NULL;
--
-- if (platform_device_add_resources(pdev, atmel_twi0_resource,
-- ARRAY_SIZE(atmel_twi0_resource)))
-- goto err_add_resources;
--
-- select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
-- select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
--
-- atmel_twi0_pclk.dev = &pdev->dev;
--
-- platform_device_add(pdev);
-- return pdev;
--
--err_add_resources:
-- platform_device_put(pdev);
-- return NULL;
--}
--
--/* --------------------------------------------------------------------
-- * MMC
-- * -------------------------------------------------------------------- */
--static struct resource atmel_mci0_resource[] __initdata = {
-- PBMEM(0xfff02400),
-- IRQ(28),
--};
--static struct clk atmel_mci0_pclk = {
-- .name = "mci_clk",
-- .parent = &pbb_clk,
-- .mode = pbb_clk_mode,
-- .get_rate = pbb_clk_get_rate,
-- .index = 9,
--};
--
--struct platform_device *__init at32_add_device_mci(unsigned int id)
--{
-- struct platform_device *pdev;
--
-- if (id != 0)
-- return NULL;
--
-- pdev = platform_device_alloc("atmel_mci", id);
-- if (!pdev)
-- return NULL;
--
-- if (platform_device_add_resources(pdev, atmel_mci0_resource,
-- ARRAY_SIZE(atmel_mci0_resource)))
-- goto err_add_resources;
--
-- select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
-- select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
-- select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
-- select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
-- select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
-- select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
--
-- atmel_mci0_pclk.dev = &pdev->dev;
--
-- platform_device_add(pdev);
-- return pdev;
--
--err_add_resources:
-- platform_device_put(pdev);
-- return NULL;
--}
--
--/* --------------------------------------------------------------------
-- * LCDC
-- * -------------------------------------------------------------------- */
--static struct atmel_lcdfb_info atmel_lcdfb0_data;
--static struct resource atmel_lcdfb0_resource[] = {
-- {
-- .start = 0xff000000,
-- .end = 0xff000fff,
-- .flags = IORESOURCE_MEM,
-- },
-- IRQ(1),
-- {
-- /* Placeholder for pre-allocated fb memory */
-- .start = 0x00000000,
-- .end = 0x00000000,
-- .flags = 0,
-- },
--};
--DEFINE_DEV_DATA(atmel_lcdfb, 0);
--DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
--static struct clk atmel_lcdfb0_pixclk = {
-- .name = "lcdc_clk",
-- .dev = &atmel_lcdfb0_device.dev,
-- .mode = genclk_mode,
-- .get_rate = genclk_get_rate,
-- .set_rate = genclk_set_rate,
-- .set_parent = genclk_set_parent,
-- .index = 7,
--};
--
--struct platform_device *__init
--at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
-- unsigned long fbmem_start, unsigned long fbmem_len)
--{
-- struct platform_device *pdev;
-- struct atmel_lcdfb_info *info;
-- struct fb_monspecs *monspecs;
-- struct fb_videomode *modedb;
-- unsigned int modedb_size;
--
-- /*
-- * Do a deep copy of the fb data, monspecs and modedb. Make
-- * sure all allocations are done before setting up the
-- * portmux.
-- */
-- monspecs = kmemdup(data->default_monspecs,
-- sizeof(struct fb_monspecs), GFP_KERNEL);
-- if (!monspecs)
-- return NULL;
--
-- modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
-- modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
-- if (!modedb)
-- goto err_dup_modedb;
-- monspecs->modedb = modedb;
--
-- switch (id) {
-- case 0:
-- pdev = &atmel_lcdfb0_device;
-- select_peripheral(PC(19), PERIPH_A, 0); /* CC */
-- select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
-- select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
-- select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
-- select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
-- select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
-- select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
-- select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
-- select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
-- select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
-- select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
-- select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
-- select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
-- select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
-- select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
-- select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
-- select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
-- select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
-- select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
-- select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
-- select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
-- select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
-- select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
-- select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
-- select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
-- select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
-- select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
-- select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
-- select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
-- select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
-- select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
--
-- clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
-- clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
-- break;
--
-- default:
-- goto err_invalid_id;
-- }
--
-- if (fbmem_len) {
-- pdev->resource[2].start = fbmem_start;
-- pdev->resource[2].end = fbmem_start + fbmem_len - 1;
-- pdev->resource[2].flags = IORESOURCE_MEM;
-- }
--
-- info = pdev->dev.platform_data;
-- memcpy(info, data, sizeof(struct atmel_lcdfb_info));
-- info->default_monspecs = monspecs;
--
-- platform_device_register(pdev);
-- return pdev;
--
--err_invalid_id:
-- kfree(modedb);
--err_dup_modedb:
-- kfree(monspecs);
-- return NULL;
--}
--
--/* --------------------------------------------------------------------
-- * SSC
-- * -------------------------------------------------------------------- */
--static struct resource ssc0_resource[] = {
-- PBMEM(0xffe01c00),
-- IRQ(10),
--};
--DEFINE_DEV(ssc, 0);
--DEV_CLK(pclk, ssc0, pba, 7);
--
--static struct resource ssc1_resource[] = {
-- PBMEM(0xffe02000),
-- IRQ(11),
--};
--DEFINE_DEV(ssc, 1);
--DEV_CLK(pclk, ssc1, pba, 8);
--
--static struct resource ssc2_resource[] = {
-- PBMEM(0xffe02400),
-- IRQ(12),
--};
--DEFINE_DEV(ssc, 2);
--DEV_CLK(pclk, ssc2, pba, 9);
--
--struct platform_device *__init
--at32_add_device_ssc(unsigned int id, unsigned int flags)
--{
-- struct platform_device *pdev;
--
-- switch (id) {
-- case 0:
-- pdev = &ssc0_device;
-- if (flags & ATMEL_SSC_RF)
-- select_peripheral(PA(21), PERIPH_A, 0); /* RF */
-- if (flags & ATMEL_SSC_RK)
-- select_peripheral(PA(22), PERIPH_A, 0); /* RK */
-- if (flags & ATMEL_SSC_TK)
-- select_peripheral(PA(23), PERIPH_A, 0); /* TK */
-- if (flags & ATMEL_SSC_TF)
-- select_peripheral(PA(24), PERIPH_A, 0); /* TF */
-- if (flags & ATMEL_SSC_TD)
-- select_peripheral(PA(25), PERIPH_A, 0); /* TD */
-- if (flags & ATMEL_SSC_RD)
-- select_peripheral(PA(26), PERIPH_A, 0); /* RD */
-- break;
-- case 1:
-- pdev = &ssc1_device;
-- if (flags & ATMEL_SSC_RF)
-- select_peripheral(PA(0), PERIPH_B, 0); /* RF */
-- if (flags & ATMEL_SSC_RK)
-- select_peripheral(PA(1), PERIPH_B, 0); /* RK */
-- if (flags & ATMEL_SSC_TK)
-- select_peripheral(PA(2), PERIPH_B, 0); /* TK */
-- if (flags & ATMEL_SSC_TF)
-- select_peripheral(PA(3), PERIPH_B, 0); /* TF */
-- if (flags & ATMEL_SSC_TD)
-- select_peripheral(PA(4), PERIPH_B, 0); /* TD */
-- if (flags & ATMEL_SSC_RD)
-- select_peripheral(PA(5), PERIPH_B, 0); /* RD */
-- break;
-- case 2:
-- pdev = &ssc2_device;
-- if (flags & ATMEL_SSC_TD)
-- select_peripheral(PB(13), PERIPH_A, 0); /* TD */
-- if (flags & ATMEL_SSC_RD)
-- select_peripheral(PB(14), PERIPH_A, 0); /* RD */
-- if (flags & ATMEL_SSC_TK)
-- select_peripheral(PB(15), PERIPH_A, 0); /* TK */
-- if (flags & ATMEL_SSC_TF)
-- select_peripheral(PB(16), PERIPH_A, 0); /* TF */
-- if (flags & ATMEL_SSC_RF)
-- select_peripheral(PB(17), PERIPH_A, 0); /* RF */
-- if (flags & ATMEL_SSC_RK)
-- select_peripheral(PB(18), PERIPH_A, 0); /* RK */
-- break;
-- default:
-- return NULL;
-- }
--
-- platform_device_register(pdev);
-- return pdev;
--}
--
--/* --------------------------------------------------------------------
-- * USB Device Controller
-- * -------------------------------------------------------------------- */
--static struct resource usba0_resource[] __initdata = {
-- {
-- .start = 0xff300000,
-- .end = 0xff3fffff,
-- .flags = IORESOURCE_MEM,
-- }, {
-- .start = 0xfff03000,
-- .end = 0xfff033ff,
-- .flags = IORESOURCE_MEM,
-- },
-- IRQ(31),
--};
--static struct clk usba0_pclk = {
-- .name = "pclk",
-- .parent = &pbb_clk,
-- .mode = pbb_clk_mode,
-- .get_rate = pbb_clk_get_rate,
-- .index = 12,
--};
--static struct clk usba0_hclk = {
-- .name = "hclk",
-- .parent = &hsb_clk,
-- .mode = hsb_clk_mode,
-- .get_rate = hsb_clk_get_rate,
-- .index = 6,
--};
--
--struct platform_device *__init
--at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
--{
-- struct platform_device *pdev;
--
-- if (id != 0)
-- return NULL;
--
-- pdev = platform_device_alloc("atmel_usba_udc", 0);
-- if (!pdev)
-- return NULL;
--
-- if (platform_device_add_resources(pdev, usba0_resource,
-- ARRAY_SIZE(usba0_resource)))
-- goto out_free_pdev;
--
-- if (data) {
-- if (platform_device_add_data(pdev, data, sizeof(*data)))
-- goto out_free_pdev;
--
-- if (data->vbus_pin != GPIO_PIN_NONE)
-- at32_select_gpio(data->vbus_pin, 0);
-- }
--
-- usba0_pclk.dev = &pdev->dev;
-- usba0_hclk.dev = &pdev->dev;
--
-- platform_device_add(pdev);
--
-- return pdev;
--
--out_free_pdev:
-- platform_device_put(pdev);
-- return NULL;
--}
--
--/* --------------------------------------------------------------------
-- * IDE / CompactFlash
-- * -------------------------------------------------------------------- */
--static struct resource at32_smc_cs4_resource[] __initdata = {
-- {
-- .start = 0x04000000,
-- .end = 0x07ffffff,
-- .flags = IORESOURCE_MEM,
-- },
-- IRQ(~0UL), /* Magic IRQ will be overridden */
--};
--static struct resource at32_smc_cs5_resource[] __initdata = {
-- {
-- .start = 0x20000000,
-- .end = 0x23ffffff,
-- .flags = IORESOURCE_MEM,
-- },
-- IRQ(~0UL), /* Magic IRQ will be overridden */
--};
--
--static int __init at32_init_ide_or_cf(struct platform_device *pdev,
-- unsigned int cs, unsigned int extint)
--{
-- static unsigned int extint_pin_map[4] __initdata = {
-- GPIO_PIN_PB(25),
-- GPIO_PIN_PB(26),
-- GPIO_PIN_PB(27),
-- GPIO_PIN_PB(28),
-- };
-- static bool common_pins_initialized __initdata = false;
-- unsigned int extint_pin;
-- int ret;
--
-- if (extint >= ARRAY_SIZE(extint_pin_map))
-- return -EINVAL;
-- extint_pin = extint_pin_map[extint];
--
-- switch (cs) {
-- case 4:
-- ret = platform_device_add_resources(pdev,
-- at32_smc_cs4_resource,
-- ARRAY_SIZE(at32_smc_cs4_resource));
-- if (ret)
-- return ret;
--
-- select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
-- set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
-- break;
-- case 5:
-- ret = platform_device_add_resources(pdev,
-- at32_smc_cs5_resource,
-- ARRAY_SIZE(at32_smc_cs5_resource));
-- if (ret)
-- return ret;
--
-- select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
-- set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
-- break;
-- default:
-- return -EINVAL;
-- }
--
-- if (!common_pins_initialized) {
-- select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
-- select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
-- select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
-- select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
-- common_pins_initialized = true;
-- }
--
-- at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
--
-- pdev->resource[1].start = EIM_IRQ_BASE + extint;
-- pdev->resource[1].end = pdev->resource[1].start;
--
-- return 0;
--}
--
--struct platform_device *__init
--at32_add_device_ide(unsigned int id, unsigned int extint,
-- struct ide_platform_data *data)
--{
-- struct platform_device *pdev;
--
-- pdev = platform_device_alloc("at32_ide", id);
-- if (!pdev)
-- goto fail;
--
-- if (platform_device_add_data(pdev, data,
-- sizeof(struct ide_platform_data)))
-- goto fail;
--
-- if (at32_init_ide_or_cf(pdev, data->cs, extint))
-- goto fail;
--
-- platform_device_add(pdev);
-- return pdev;
--
--fail:
-- platform_device_put(pdev);
-- return NULL;
--}
--
--struct platform_device *__init
--at32_add_device_cf(unsigned int id, unsigned int extint,
-- struct cf_platform_data *data)
--{
-- struct platform_device *pdev;
--
-- pdev = platform_device_alloc("at32_cf", id);
-- if (!pdev)
-- goto fail;
--
-- if (platform_device_add_data(pdev, data,
-- sizeof(struct cf_platform_data)))
-- goto fail;
--
-- if (at32_init_ide_or_cf(pdev, data->cs, extint))
-- goto fail;
--
-- if (data->detect_pin != GPIO_PIN_NONE)
-- at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
-- if (data->reset_pin != GPIO_PIN_NONE)
-- at32_select_gpio(data->reset_pin, 0);
-- if (data->vcc_pin != GPIO_PIN_NONE)
-- at32_select_gpio(data->vcc_pin, 0);
-- /* READY is used as extint, so we can't select it as gpio */
--
-- platform_device_add(pdev);
-- return pdev;
--
--fail:
-- platform_device_put(pdev);
-- return NULL;
--}
--
--/* --------------------------------------------------------------------
-- * AC97C
-- * -------------------------------------------------------------------- */
--static struct resource atmel_ac97c0_resource[] __initdata = {
-- PBMEM(0xfff02800),
-- IRQ(29),
--};
--static struct clk atmel_ac97c0_pclk = {
-- .name = "pclk",
-- .parent = &pbb_clk,
-- .mode = pbb_clk_mode,
-- .get_rate = pbb_clk_get_rate,
-- .index = 10,
--};
--
--struct platform_device *__init at32_add_device_ac97c(unsigned int id)
--{
-- struct platform_device *pdev;
--
-- if (id != 0)
-- return NULL;
--
-- pdev = platform_device_alloc("atmel_ac97c", id);
-- if (!pdev)
-- return NULL;
--
-- if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
-- ARRAY_SIZE(atmel_ac97c0_resource)))
-- goto err_add_resources;
--
-- select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
-- select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
-- select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
-- select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
--
-- atmel_ac97c0_pclk.dev = &pdev->dev;
--
-- platform_device_add(pdev);
-- return pdev;
--
--err_add_resources:
-- platform_device_put(pdev);
-- return NULL;
--}
--
--/* --------------------------------------------------------------------
-- * ABDAC
-- * -------------------------------------------------------------------- */
--static struct resource abdac0_resource[] __initdata = {
-- PBMEM(0xfff02000),
-- IRQ(27),
--};
--static struct clk abdac0_pclk = {
-- .name = "pclk",
-- .parent = &pbb_clk,
-- .mode = pbb_clk_mode,
-- .get_rate = pbb_clk_get_rate,
-- .index = 8,
--};
--static struct clk abdac0_sample_clk = {
-- .name = "sample_clk",
-- .mode = genclk_mode,
-- .get_rate = genclk_get_rate,
-- .set_rate = genclk_set_rate,
-- .set_parent = genclk_set_parent,
-- .index = 6,
--};
--
--struct platform_device *__init at32_add_device_abdac(unsigned int id)
--{
-- struct platform_device *pdev;
--
-- if (id != 0)
-- return NULL;
--
-- pdev = platform_device_alloc("abdac", id);
-- if (!pdev)
-- return NULL;
--
-- if (platform_device_add_resources(pdev, abdac0_resource,
-- ARRAY_SIZE(abdac0_resource)))
-- goto err_add_resources;
--
-- select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
-- select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
-- select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
-- select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
--
-- abdac0_pclk.dev = &pdev->dev;
-- abdac0_sample_clk.dev = &pdev->dev;
--
-- platform_device_add(pdev);
-- return pdev;
--
--err_add_resources:
-- platform_device_put(pdev);
-- return NULL;
--}
--
--/* --------------------------------------------------------------------
-- * GCLK
-- * -------------------------------------------------------------------- */
--static struct clk gclk0 = {
-- .name = "gclk0",
-- .mode = genclk_mode,
-- .get_rate = genclk_get_rate,
-- .set_rate = genclk_set_rate,
-- .set_parent = genclk_set_parent,
-- .index = 0,
--};
--static struct clk gclk1 = {
-- .name = "gclk1",
-- .mode = genclk_mode,
-- .get_rate = genclk_get_rate,
-- .set_rate = genclk_set_rate,
-- .set_parent = genclk_set_parent,
-- .index = 1,
--};
--static struct clk gclk2 = {
-- .name = "gclk2",
-- .mode = genclk_mode,
-- .get_rate = genclk_get_rate,
-- .set_rate = genclk_set_rate,
-- .set_parent = genclk_set_parent,
-- .index = 2,
--};
--static struct clk gclk3 = {
-- .name = "gclk3",
-- .mode = genclk_mode,
-- .get_rate = genclk_get_rate,
-- .set_rate = genclk_set_rate,
-- .set_parent = genclk_set_parent,
-- .index = 3,
--};
--static struct clk gclk4 = {
-- .name = "gclk4",
-- .mode = genclk_mode,
-- .get_rate = genclk_get_rate,
-- .set_rate = genclk_set_rate,
-- .set_parent = genclk_set_parent,
-- .index = 4,
--};
--
--struct clk *at32_clock_list[] = {
-- &osc32k,
-- &osc0,
-- &osc1,
-- &pll0,
-- &pll1,
-- &cpu_clk,
-- &hsb_clk,
-- &pba_clk,
-- &pbb_clk,
-- &at32_pm_pclk,
-- &at32_intc0_pclk,
-- &hmatrix_clk,
-- &ebi_clk,
-- &hramc_clk,
-- &smc0_pclk,
-- &smc0_mck,
-- &pdc_hclk,
-- &pdc_pclk,
-- &dmaca0_hclk,
-- &pico_clk,
-- &pio0_mck,
-- &pio1_mck,
-- &pio2_mck,
-- &pio3_mck,
-- &pio4_mck,
-- &at32_systc0_pclk,
-- &atmel_usart0_usart,
-- &atmel_usart1_usart,
-- &atmel_usart2_usart,
-- &atmel_usart3_usart,
-- &macb0_hclk,
-- &macb0_pclk,
-- &macb1_hclk,
-- &macb1_pclk,
-- &atmel_spi0_spi_clk,
-- &atmel_spi1_spi_clk,
-- &atmel_twi0_pclk,
-- &atmel_mci0_pclk,
-- &atmel_lcdfb0_hck1,
-- &atmel_lcdfb0_pixclk,
-- &ssc0_pclk,
-- &ssc1_pclk,
-- &ssc2_pclk,
-- &usba0_hclk,
-- &usba0_pclk,
-- &atmel_ac97c0_pclk,
-- &abdac0_pclk,
-- &abdac0_sample_clk,
-- &gclk0,
-- &gclk1,
-- &gclk2,
-- &gclk3,
-- &gclk4,
--};
--unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
--
--void __init at32_portmux_init(void)
--{
-- at32_init_pio(&pio0_device);
-- at32_init_pio(&pio1_device);
-- at32_init_pio(&pio2_device);
-- at32_init_pio(&pio3_device);
-- at32_init_pio(&pio4_device);
--}
--
--void __init at32_clock_init(void)
--{
-- u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
-- int i;
--
-- if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
-- main_clock = &pll0;
-- cpu_clk.parent = &pll0;
-- } else {
-- main_clock = &osc0;
-- cpu_clk.parent = &osc0;
-- }
--
-- if (pm_readl(PLL0) & PM_BIT(PLLOSC))
-- pll0.parent = &osc1;
-- if (pm_readl(PLL1) & PM_BIT(PLLOSC))
-- pll1.parent = &osc1;
--
-- genclk_init_parent(&gclk0);
-- genclk_init_parent(&gclk1);
-- genclk_init_parent(&gclk2);
-- genclk_init_parent(&gclk3);
-- genclk_init_parent(&gclk4);
-- genclk_init_parent(&atmel_lcdfb0_pixclk);
-- genclk_init_parent(&abdac0_sample_clk);
--
-- /*
-- * Turn on all clocks that have at least one user already, and
-- * turn off everything else. We only do this for module
-- * clocks, and even though it isn't particularly pretty to
-- * check the address of the mode function, it should do the
-- * trick...
-- */
-- for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
-- struct clk *clk = at32_clock_list[i];
--
-- if (clk->users == 0)
-- continue;
--
-- if (clk->mode == &cpu_clk_mode)
-- cpu_mask |= 1 << clk->index;
-- else if (clk->mode == &hsb_clk_mode)
-- hsb_mask |= 1 << clk->index;
-- else if (clk->mode == &pba_clk_mode)
-- pba_mask |= 1 << clk->index;
-- else if (clk->mode == &pbb_clk_mode)
-- pbb_mask |= 1 << clk->index;
-- }
--
-- pm_writel(CPU_MASK, cpu_mask);
-- pm_writel(HSB_MASK, hsb_mask);
-- pm_writel(PBA_MASK, pba_mask);
-- pm_writel(PBB_MASK, pbb_mask);
--}
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/at32ap700x.c
-@@ -0,0 +1,1944 @@
-+/*
-+ * Copyright (C) 2005-2006 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <linux/clk.h>
-+#include <linux/fb.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/spi/spi.h>
-+#include <linux/usb/atmel_usba_udc.h>
-+
-+#include <asm/io.h>
-+#include <asm/irq.h>
-+
-+#include <asm/arch/at32ap700x.h>
-+#include <asm/arch/board.h>
-+#include <asm/arch/portmux.h>
-+
-+#include <video/atmel_lcdc.h>
-+
-+#include "clock.h"
-+#include "hmatrix.h"
-+#include "pio.h"
-+#include "pm.h"
-+
-+
-+#define PBMEM(base) \
-+ { \
-+ .start = base, \
-+ .end = base + 0x3ff, \
-+ .flags = IORESOURCE_MEM, \
-+ }
-+#define IRQ(num) \
-+ { \
-+ .start = num, \
-+ .end = num, \
-+ .flags = IORESOURCE_IRQ, \
-+ }
-+#define NAMED_IRQ(num, _name) \
-+ { \
-+ .start = num, \
-+ .end = num, \
-+ .name = _name, \
-+ .flags = IORESOURCE_IRQ, \
-+ }
-+
-+/* REVISIT these assume *every* device supports DMA, but several
-+ * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
-+ */
-+#define DEFINE_DEV(_name, _id) \
-+static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
-+static struct platform_device _name##_id##_device = { \
-+ .name = #_name, \
-+ .id = _id, \
-+ .dev = { \
-+ .dma_mask = &_name##_id##_dma_mask, \
-+ .coherent_dma_mask = DMA_32BIT_MASK, \
-+ }, \
-+ .resource = _name##_id##_resource, \
-+ .num_resources = ARRAY_SIZE(_name##_id##_resource), \
-+}
-+#define DEFINE_DEV_DATA(_name, _id) \
-+static u64 _name##_id##_dma_mask = DMA_32BIT_MASK; \
-+static struct platform_device _name##_id##_device = { \
-+ .name = #_name, \
-+ .id = _id, \
-+ .dev = { \
-+ .dma_mask = &_name##_id##_dma_mask, \
-+ .platform_data = &_name##_id##_data, \
-+ .coherent_dma_mask = DMA_32BIT_MASK, \
-+ }, \
-+ .resource = _name##_id##_resource, \
-+ .num_resources = ARRAY_SIZE(_name##_id##_resource), \
-+}
-+
-+#define select_peripheral(pin, periph, flags) \
-+ at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
-+
-+#define DEV_CLK(_name, devname, bus, _index) \
-+static struct clk devname##_##_name = { \
-+ .name = #_name, \
-+ .dev = &devname##_device.dev, \
-+ .parent = &bus##_clk, \
-+ .mode = bus##_clk_mode, \
-+ .get_rate = bus##_clk_get_rate, \
-+ .index = _index, \
-+}
-+
-+static DEFINE_SPINLOCK(pm_lock);
-+
-+unsigned long at32ap7000_osc_rates[3] = {
-+ [0] = 32768,
-+ /* FIXME: these are ATSTK1002-specific */
-+ [1] = 20000000,
-+ [2] = 12000000,
-+};
-+
-+static unsigned long osc_get_rate(struct clk *clk)
-+{
-+ return at32ap7000_osc_rates[clk->index];
-+}
-+
-+static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
-+{
-+ unsigned long div, mul, rate;
-+
-+ if (!(control & PM_BIT(PLLEN)))
-+ return 0;
-+
-+ div = PM_BFEXT(PLLDIV, control) + 1;
-+ mul = PM_BFEXT(PLLMUL, control) + 1;
-+
-+ rate = clk->parent->get_rate(clk->parent);
-+ rate = (rate + div / 2) / div;
-+ rate *= mul;
-+
-+ return rate;
-+}
-+
-+static unsigned long pll0_get_rate(struct clk *clk)
-+{
-+ u32 control;
-+
-+ control = pm_readl(PLL0);
-+
-+ return pll_get_rate(clk, control);
-+}
-+
-+static unsigned long pll1_get_rate(struct clk *clk)
-+{
-+ u32 control;
-+
-+ control = pm_readl(PLL1);
-+
-+ return pll_get_rate(clk, control);
-+}
-+
-+/*
-+ * The AT32AP7000 has five primary clock sources: One 32kHz
-+ * oscillator, two crystal oscillators and two PLLs.
-+ */
-+static struct clk osc32k = {
-+ .name = "osc32k",
-+ .get_rate = osc_get_rate,
-+ .users = 1,
-+ .index = 0,
-+};
-+static struct clk osc0 = {
-+ .name = "osc0",
-+ .get_rate = osc_get_rate,
-+ .users = 1,
-+ .index = 1,
-+};
-+static struct clk osc1 = {
-+ .name = "osc1",
-+ .get_rate = osc_get_rate,
-+ .index = 2,
-+};
-+static struct clk pll0 = {
-+ .name = "pll0",
-+ .get_rate = pll0_get_rate,
-+ .parent = &osc0,
-+};
-+static struct clk pll1 = {
-+ .name = "pll1",
-+ .get_rate = pll1_get_rate,
-+ .parent = &osc0,
-+};
-+
-+/*
-+ * The main clock can be either osc0 or pll0. The boot loader may
-+ * have chosen one for us, so we don't really know which one until we
-+ * have a look at the SM.
-+ */
-+static struct clk *main_clock;
-+
-+/*
-+ * Synchronous clocks are generated from the main clock. The clocks
-+ * must satisfy the constraint
-+ * fCPU >= fHSB >= fPB
-+ * i.e. each clock must not be faster than its parent.
-+ */
-+static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
-+{
-+ return main_clock->get_rate(main_clock) >> shift;
-+};
-+
-+static void cpu_clk_mode(struct clk *clk, int enabled)
-+{
-+ unsigned long flags;
-+ u32 mask;
-+
-+ spin_lock_irqsave(&pm_lock, flags);
-+ mask = pm_readl(CPU_MASK);
-+ if (enabled)
-+ mask |= 1 << clk->index;
-+ else
-+ mask &= ~(1 << clk->index);
-+ pm_writel(CPU_MASK, mask);
-+ spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long cpu_clk_get_rate(struct clk *clk)
-+{
-+ unsigned long cksel, shift = 0;
-+
-+ cksel = pm_readl(CKSEL);
-+ if (cksel & PM_BIT(CPUDIV))
-+ shift = PM_BFEXT(CPUSEL, cksel) + 1;
-+
-+ return bus_clk_get_rate(clk, shift);
-+}
-+
-+static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
-+{
-+ u32 control;
-+ unsigned long parent_rate, child_div, actual_rate, div;
-+
-+ parent_rate = clk->parent->get_rate(clk->parent);
-+ control = pm_readl(CKSEL);
-+
-+ if (control & PM_BIT(HSBDIV))
-+ child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
-+ else
-+ child_div = 1;
-+
-+ if (rate > 3 * (parent_rate / 4) || child_div == 1) {
-+ actual_rate = parent_rate;
-+ control &= ~PM_BIT(CPUDIV);
-+ } else {
-+ unsigned int cpusel;
-+ div = (parent_rate + rate / 2) / rate;
-+ if (div > child_div)
-+ div = child_div;
-+ cpusel = (div > 1) ? (fls(div) - 2) : 0;
-+ control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
-+ actual_rate = parent_rate / (1 << (cpusel + 1));
-+ }
-+
-+ pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
-+ clk->name, rate, actual_rate);
-+
-+ if (apply)
-+ pm_writel(CKSEL, control);
-+
-+ return actual_rate;
-+}
-+
-+static void hsb_clk_mode(struct clk *clk, int enabled)
-+{
-+ unsigned long flags;
-+ u32 mask;
-+
-+ spin_lock_irqsave(&pm_lock, flags);
-+ mask = pm_readl(HSB_MASK);
-+ if (enabled)
-+ mask |= 1 << clk->index;
-+ else
-+ mask &= ~(1 << clk->index);
-+ pm_writel(HSB_MASK, mask);
-+ spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long hsb_clk_get_rate(struct clk *clk)
-+{
-+ unsigned long cksel, shift = 0;
-+
-+ cksel = pm_readl(CKSEL);
-+ if (cksel & PM_BIT(HSBDIV))
-+ shift = PM_BFEXT(HSBSEL, cksel) + 1;
-+
-+ return bus_clk_get_rate(clk, shift);
-+}
-+
-+static void pba_clk_mode(struct clk *clk, int enabled)
-+{
-+ unsigned long flags;
-+ u32 mask;
-+
-+ spin_lock_irqsave(&pm_lock, flags);
-+ mask = pm_readl(PBA_MASK);
-+ if (enabled)
-+ mask |= 1 << clk->index;
-+ else
-+ mask &= ~(1 << clk->index);
-+ pm_writel(PBA_MASK, mask);
-+ spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long pba_clk_get_rate(struct clk *clk)
-+{
-+ unsigned long cksel, shift = 0;
-+
-+ cksel = pm_readl(CKSEL);
-+ if (cksel & PM_BIT(PBADIV))
-+ shift = PM_BFEXT(PBASEL, cksel) + 1;
-+
-+ return bus_clk_get_rate(clk, shift);
-+}
-+
-+static void pbb_clk_mode(struct clk *clk, int enabled)
-+{
-+ unsigned long flags;
-+ u32 mask;
-+
-+ spin_lock_irqsave(&pm_lock, flags);
-+ mask = pm_readl(PBB_MASK);
-+ if (enabled)
-+ mask |= 1 << clk->index;
-+ else
-+ mask &= ~(1 << clk->index);
-+ pm_writel(PBB_MASK, mask);
-+ spin_unlock_irqrestore(&pm_lock, flags);
-+}
-+
-+static unsigned long pbb_clk_get_rate(struct clk *clk)
-+{
-+ unsigned long cksel, shift = 0;
-+
-+ cksel = pm_readl(CKSEL);
-+ if (cksel & PM_BIT(PBBDIV))
-+ shift = PM_BFEXT(PBBSEL, cksel) + 1;
-+
-+ return bus_clk_get_rate(clk, shift);
-+}
-+
-+static struct clk cpu_clk = {
-+ .name = "cpu",
-+ .get_rate = cpu_clk_get_rate,
-+ .set_rate = cpu_clk_set_rate,
-+ .users = 1,
-+};
-+static struct clk hsb_clk = {
-+ .name = "hsb",
-+ .parent = &cpu_clk,
-+ .get_rate = hsb_clk_get_rate,
-+};
-+static struct clk pba_clk = {
-+ .name = "pba",
-+ .parent = &hsb_clk,
-+ .mode = hsb_clk_mode,
-+ .get_rate = pba_clk_get_rate,
-+ .index = 1,
-+};
-+static struct clk pbb_clk = {
-+ .name = "pbb",
-+ .parent = &hsb_clk,
-+ .mode = hsb_clk_mode,
-+ .get_rate = pbb_clk_get_rate,
-+ .users = 1,
-+ .index = 2,
-+};
-+
-+/* --------------------------------------------------------------------
-+ * Generic Clock operations
-+ * -------------------------------------------------------------------- */
-+
-+static void genclk_mode(struct clk *clk, int enabled)
-+{
-+ u32 control;
-+
-+ control = pm_readl(GCCTRL(clk->index));
-+ if (enabled)
-+ control |= PM_BIT(CEN);
-+ else
-+ control &= ~PM_BIT(CEN);
-+ pm_writel(GCCTRL(clk->index), control);
-+}
-+
-+static unsigned long genclk_get_rate(struct clk *clk)
-+{
-+ u32 control;
-+ unsigned long div = 1;
-+
-+ control = pm_readl(GCCTRL(clk->index));
-+ if (control & PM_BIT(DIVEN))
-+ div = 2 * (PM_BFEXT(DIV, control) + 1);
-+
-+ return clk->parent->get_rate(clk->parent) / div;
-+}
-+
-+static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
-+{
-+ u32 control;
-+ unsigned long parent_rate, actual_rate, div;
-+
-+ parent_rate = clk->parent->get_rate(clk->parent);
-+ control = pm_readl(GCCTRL(clk->index));
-+
-+ if (rate > 3 * parent_rate / 4) {
-+ actual_rate = parent_rate;
-+ control &= ~PM_BIT(DIVEN);
-+ } else {
-+ div = (parent_rate + rate) / (2 * rate) - 1;
-+ control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
-+ actual_rate = parent_rate / (2 * (div + 1));
-+ }
-+
-+ dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
-+ clk->name, rate, actual_rate);
-+
-+ if (apply)
-+ pm_writel(GCCTRL(clk->index), control);
-+
-+ return actual_rate;
-+}
-+
-+int genclk_set_parent(struct clk *clk, struct clk *parent)
-+{
-+ u32 control;
-+
-+ dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
-+ clk->name, parent->name, clk->parent->name);
-+
-+ control = pm_readl(GCCTRL(clk->index));
-+
-+ if (parent == &osc1 || parent == &pll1)
-+ control |= PM_BIT(OSCSEL);
-+ else if (parent == &osc0 || parent == &pll0)
-+ control &= ~PM_BIT(OSCSEL);
-+ else
-+ return -EINVAL;
-+
-+ if (parent == &pll0 || parent == &pll1)
-+ control |= PM_BIT(PLLSEL);
-+ else
-+ control &= ~PM_BIT(PLLSEL);
-+
-+ pm_writel(GCCTRL(clk->index), control);
-+ clk->parent = parent;
-+
-+ return 0;
-+}
-+
-+static void __init genclk_init_parent(struct clk *clk)
-+{
-+ u32 control;
-+ struct clk *parent;
-+
-+ BUG_ON(clk->index > 7);
-+
-+ control = pm_readl(GCCTRL(clk->index));
-+ if (control & PM_BIT(OSCSEL))
-+ parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
-+ else
-+ parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
-+
-+ clk->parent = parent;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * System peripherals
-+ * -------------------------------------------------------------------- */
-+static struct resource at32_pm0_resource[] = {
-+ {
-+ .start = 0xfff00000,
-+ .end = 0xfff0007f,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ IRQ(20),
-+};
-+
-+static struct resource at32ap700x_rtc0_resource[] = {
-+ {
-+ .start = 0xfff00080,
-+ .end = 0xfff000af,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ IRQ(21),
-+};
-+
-+static struct resource at32_wdt0_resource[] = {
-+ {
-+ .start = 0xfff000b0,
-+ .end = 0xfff000cf,
-+ .flags = IORESOURCE_MEM,
-+ },
-+};
-+
-+static struct resource at32_eic0_resource[] = {
-+ {
-+ .start = 0xfff00100,
-+ .end = 0xfff0013f,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ IRQ(19),
-+};
-+
-+DEFINE_DEV(at32_pm, 0);
-+DEFINE_DEV(at32ap700x_rtc, 0);
-+DEFINE_DEV(at32_wdt, 0);
-+DEFINE_DEV(at32_eic, 0);
-+
-+/*
-+ * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
-+ * is always running.
-+ */
-+static struct clk at32_pm_pclk = {
-+ .name = "pclk",
-+ .dev = &at32_pm0_device.dev,
-+ .parent = &pbb_clk,
-+ .mode = pbb_clk_mode,
-+ .get_rate = pbb_clk_get_rate,
-+ .users = 1,
-+ .index = 0,
-+};
-+
-+static struct resource intc0_resource[] = {
-+ PBMEM(0xfff00400),
-+};
-+struct platform_device at32_intc0_device = {
-+ .name = "intc",
-+ .id = 0,
-+ .resource = intc0_resource,
-+ .num_resources = ARRAY_SIZE(intc0_resource),
-+};
-+DEV_CLK(pclk, at32_intc0, pbb, 1);
-+
-+static struct clk ebi_clk = {
-+ .name = "ebi",
-+ .parent = &hsb_clk,
-+ .mode = hsb_clk_mode,
-+ .get_rate = hsb_clk_get_rate,
-+ .users = 1,
-+};
-+static struct clk hramc_clk = {
-+ .name = "hramc",
-+ .parent = &hsb_clk,
-+ .mode = hsb_clk_mode,
-+ .get_rate = hsb_clk_get_rate,
-+ .users = 1,
-+ .index = 3,
-+};
-+
-+static struct resource smc0_resource[] = {
-+ PBMEM(0xfff03400),
-+};
-+DEFINE_DEV(smc, 0);
-+DEV_CLK(pclk, smc0, pbb, 13);
-+DEV_CLK(mck, smc0, hsb, 0);
-+
-+static struct platform_device pdc_device = {
-+ .name = "pdc",
-+ .id = 0,
-+};
-+DEV_CLK(hclk, pdc, hsb, 4);
-+DEV_CLK(pclk, pdc, pba, 16);
-+
-+static struct clk pico_clk = {
-+ .name = "pico",
-+ .parent = &cpu_clk,
-+ .mode = cpu_clk_mode,
-+ .get_rate = cpu_clk_get_rate,
-+ .users = 1,
-+};
-+
-+static struct resource dmaca0_resource[] = {
-+ {
-+ .start = 0xff200000,
-+ .end = 0xff20ffff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ IRQ(2),
-+};
-+DEFINE_DEV(dmaca, 0);
-+DEV_CLK(hclk, dmaca0, hsb, 10);
-+
-+/* --------------------------------------------------------------------
-+ * HMATRIX
-+ * -------------------------------------------------------------------- */
-+
-+static struct clk hmatrix_clk = {
-+ .name = "hmatrix_clk",
-+ .parent = &pbb_clk,
-+ .mode = pbb_clk_mode,
-+ .get_rate = pbb_clk_get_rate,
-+ .index = 2,
-+ .users = 1,
-+};
-+#define HMATRIX_BASE ((void __iomem *)0xfff00800)
-+
-+#define hmatrix_readl(reg) \
-+ __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
-+#define hmatrix_writel(reg,value) \
-+ __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
-+
-+/*
-+ * Set bits in the HMATRIX Special Function Register (SFR) used by the
-+ * External Bus Interface (EBI). This can be used to enable special
-+ * features like CompactFlash support, NAND Flash support, etc. on
-+ * certain chipselects.
-+ */
-+static inline void set_ebi_sfr_bits(u32 mask)
-+{
-+ u32 sfr;
-+
-+ clk_enable(&hmatrix_clk);
-+ sfr = hmatrix_readl(SFR4);
-+ sfr |= mask;
-+ hmatrix_writel(SFR4, sfr);
-+ clk_disable(&hmatrix_clk);
-+}
-+
-+/* --------------------------------------------------------------------
-+ * Timer/Counter (TC)
-+ * -------------------------------------------------------------------- */
-+
-+static struct resource at32_tcb0_resource[] = {
-+ PBMEM(0xfff00c00),
-+ IRQ(22),
-+};
-+static struct platform_device at32_tcb0_device = {
-+ .name = "atmel_tcb",
-+ .id = 0,
-+ .resource = at32_tcb0_resource,
-+ .num_resources = ARRAY_SIZE(at32_tcb0_resource),
-+};
-+DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
-+
-+static struct resource at32_tcb1_resource[] = {
-+ PBMEM(0xfff01000),
-+ IRQ(23),
-+};
-+static struct platform_device at32_tcb1_device = {
-+ .name = "atmel_tcb",
-+ .id = 1,
-+ .resource = at32_tcb1_resource,
-+ .num_resources = ARRAY_SIZE(at32_tcb1_resource),
-+};
-+DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
-+
-+/* --------------------------------------------------------------------
-+ * PIO
-+ * -------------------------------------------------------------------- */
-+
-+static struct resource pio0_resource[] = {
-+ PBMEM(0xffe02800),
-+ IRQ(13),
-+};
-+DEFINE_DEV(pio, 0);
-+DEV_CLK(mck, pio0, pba, 10);
-+
-+static struct resource pio1_resource[] = {
-+ PBMEM(0xffe02c00),
-+ IRQ(14),
-+};
-+DEFINE_DEV(pio, 1);
-+DEV_CLK(mck, pio1, pba, 11);
-+
-+static struct resource pio2_resource[] = {
-+ PBMEM(0xffe03000),
-+ IRQ(15),
-+};
-+DEFINE_DEV(pio, 2);
-+DEV_CLK(mck, pio2, pba, 12);
-+
-+static struct resource pio3_resource[] = {
-+ PBMEM(0xffe03400),
-+ IRQ(16),
-+};
-+DEFINE_DEV(pio, 3);
-+DEV_CLK(mck, pio3, pba, 13);
-+
-+static struct resource pio4_resource[] = {
-+ PBMEM(0xffe03800),
-+ IRQ(17),
-+};
-+DEFINE_DEV(pio, 4);
-+DEV_CLK(mck, pio4, pba, 14);
-+
-+void __init at32_add_system_devices(void)
-+{
-+ platform_device_register(&at32_pm0_device);
-+ platform_device_register(&at32_intc0_device);
-+ platform_device_register(&at32ap700x_rtc0_device);
-+ platform_device_register(&at32_wdt0_device);
-+ platform_device_register(&at32_eic0_device);
-+ platform_device_register(&smc0_device);
-+ platform_device_register(&pdc_device);
-+ platform_device_register(&dmaca0_device);
-+
-+ platform_device_register(&at32_tcb0_device);
-+ platform_device_register(&at32_tcb1_device);
-+
-+ platform_device_register(&pio0_device);
-+ platform_device_register(&pio1_device);
-+ platform_device_register(&pio2_device);
-+ platform_device_register(&pio3_device);
-+ platform_device_register(&pio4_device);
-+}
-+
-+/* --------------------------------------------------------------------
-+ * PSIF
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_psif0_resource[] __initdata = {
-+ {
-+ .start = 0xffe03c00,
-+ .end = 0xffe03cff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ IRQ(18),
-+};
-+static struct clk atmel_psif0_pclk = {
-+ .name = "pclk",
-+ .parent = &pba_clk,
-+ .mode = pba_clk_mode,
-+ .get_rate = pba_clk_get_rate,
-+ .index = 15,
-+};
-+
-+static struct resource atmel_psif1_resource[] __initdata = {
-+ {
-+ .start = 0xffe03d00,
-+ .end = 0xffe03dff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ IRQ(18),
-+};
-+static struct clk atmel_psif1_pclk = {
-+ .name = "pclk",
-+ .parent = &pba_clk,
-+ .mode = pba_clk_mode,
-+ .get_rate = pba_clk_get_rate,
-+ .index = 15,
-+};
-+
-+struct platform_device *__init at32_add_device_psif(unsigned int id)
-+{
-+ struct platform_device *pdev;
-+
-+ if (!(id == 0 || id == 1))
-+ return NULL;
-+
-+ pdev = platform_device_alloc("atmel_psif", id);
-+ if (!pdev)
-+ return NULL;
-+
-+ switch (id) {
-+ case 0:
-+ if (platform_device_add_resources(pdev, atmel_psif0_resource,
-+ ARRAY_SIZE(atmel_psif0_resource)))
-+ goto err_add_resources;
-+ atmel_psif0_pclk.dev = &pdev->dev;
-+ select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
-+ select_peripheral(PA(9), PERIPH_A, 0); /* DATA */
-+ break;
-+ case 1:
-+ if (platform_device_add_resources(pdev, atmel_psif1_resource,
-+ ARRAY_SIZE(atmel_psif1_resource)))
-+ goto err_add_resources;
-+ atmel_psif1_pclk.dev = &pdev->dev;
-+ select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
-+ select_peripheral(PB(12), PERIPH_A, 0); /* DATA */
-+ break;
-+ default:
-+ return NULL;
-+ }
-+
-+ platform_device_add(pdev);
-+ return pdev;
-+
-+err_add_resources:
-+ platform_device_put(pdev);
-+ return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * USART
-+ * -------------------------------------------------------------------- */
-+
-+static struct atmel_uart_data atmel_usart0_data = {
-+ .use_dma_tx = 1,
-+ .use_dma_rx = 1,
-+};
-+static struct resource atmel_usart0_resource[] = {
-+ PBMEM(0xffe00c00),
-+ IRQ(6),
-+};
-+DEFINE_DEV_DATA(atmel_usart, 0);
-+DEV_CLK(usart, atmel_usart0, pba, 3);
-+
-+static struct atmel_uart_data atmel_usart1_data = {
-+ .use_dma_tx = 1,
-+ .use_dma_rx = 1,
-+};
-+static struct resource atmel_usart1_resource[] = {
-+ PBMEM(0xffe01000),
-+ IRQ(7),
-+};
-+DEFINE_DEV_DATA(atmel_usart, 1);
-+DEV_CLK(usart, atmel_usart1, pba, 4);
-+
-+static struct atmel_uart_data atmel_usart2_data = {
-+ .use_dma_tx = 1,
-+ .use_dma_rx = 1,
-+};
-+static struct resource atmel_usart2_resource[] = {
-+ PBMEM(0xffe01400),
-+ IRQ(8),
-+};
-+DEFINE_DEV_DATA(atmel_usart, 2);
-+DEV_CLK(usart, atmel_usart2, pba, 5);
-+
-+static struct atmel_uart_data atmel_usart3_data = {
-+ .use_dma_tx = 1,
-+ .use_dma_rx = 1,
-+};
-+static struct resource atmel_usart3_resource[] = {
-+ PBMEM(0xffe01800),
-+ IRQ(9),
-+};
-+DEFINE_DEV_DATA(atmel_usart, 3);
-+DEV_CLK(usart, atmel_usart3, pba, 6);
-+
-+static inline void configure_usart0_pins(void)
-+{
-+ select_peripheral(PA(8), PERIPH_B, 0); /* RXD */
-+ select_peripheral(PA(9), PERIPH_B, 0); /* TXD */
-+}
-+
-+static inline void configure_usart1_pins(void)
-+{
-+ select_peripheral(PA(17), PERIPH_A, 0); /* RXD */
-+ select_peripheral(PA(18), PERIPH_A, 0); /* TXD */
-+}
-+
-+static inline void configure_usart2_pins(void)
-+{
-+ select_peripheral(PB(26), PERIPH_B, 0); /* RXD */
-+ select_peripheral(PB(27), PERIPH_B, 0); /* TXD */
-+}
-+
-+static inline void configure_usart3_pins(void)
-+{
-+ select_peripheral(PB(18), PERIPH_B, 0); /* RXD */
-+ select_peripheral(PB(17), PERIPH_B, 0); /* TXD */
-+}
-+
-+static struct platform_device *__initdata at32_usarts[4];
-+
-+void __init at32_map_usart(unsigned int hw_id, unsigned int line)
-+{
-+ struct platform_device *pdev;
-+
-+ switch (hw_id) {
-+ case 0:
-+ pdev = &atmel_usart0_device;
-+ configure_usart0_pins();
-+ break;
-+ case 1:
-+ pdev = &atmel_usart1_device;
-+ configure_usart1_pins();
-+ break;
-+ case 2:
-+ pdev = &atmel_usart2_device;
-+ configure_usart2_pins();
-+ break;
-+ case 3:
-+ pdev = &atmel_usart3_device;
-+ configure_usart3_pins();
-+ break;
-+ default:
-+ return;
-+ }
-+
-+ if (PXSEG(pdev->resource[0].start) == P4SEG) {
-+ /* Addresses in the P4 segment are permanently mapped 1:1 */
-+ struct atmel_uart_data *data = pdev->dev.platform_data;
-+ data->regs = (void __iomem *)pdev->resource[0].start;
-+ }
-+
-+ pdev->id = line;
-+ at32_usarts[line] = pdev;
-+}
-+
-+struct platform_device *__init at32_add_device_usart(unsigned int id)
-+{
-+ platform_device_register(at32_usarts[id]);
-+ return at32_usarts[id];
-+}
-+
-+struct platform_device *atmel_default_console_device;
-+
-+void __init at32_setup_serial_console(unsigned int usart_id)
-+{
-+ atmel_default_console_device = at32_usarts[usart_id];
-+}
-+
-+/* --------------------------------------------------------------------
-+ * Ethernet
-+ * -------------------------------------------------------------------- */
-+
-+#ifdef CONFIG_CPU_AT32AP7000
-+static struct eth_platform_data macb0_data;
-+static struct resource macb0_resource[] = {
-+ PBMEM(0xfff01800),
-+ IRQ(25),
-+};
-+DEFINE_DEV_DATA(macb, 0);
-+DEV_CLK(hclk, macb0, hsb, 8);
-+DEV_CLK(pclk, macb0, pbb, 6);
-+
-+static struct eth_platform_data macb1_data;
-+static struct resource macb1_resource[] = {
-+ PBMEM(0xfff01c00),
-+ IRQ(26),
-+};
-+DEFINE_DEV_DATA(macb, 1);
-+DEV_CLK(hclk, macb1, hsb, 9);
-+DEV_CLK(pclk, macb1, pbb, 7);
-+
-+struct platform_device *__init
-+at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
-+{
-+ struct platform_device *pdev;
-+
-+ switch (id) {
-+ case 0:
-+ pdev = &macb0_device;
-+
-+ select_peripheral(PC(3), PERIPH_A, 0); /* TXD0 */
-+ select_peripheral(PC(4), PERIPH_A, 0); /* TXD1 */
-+ select_peripheral(PC(7), PERIPH_A, 0); /* TXEN */
-+ select_peripheral(PC(8), PERIPH_A, 0); /* TXCK */
-+ select_peripheral(PC(9), PERIPH_A, 0); /* RXD0 */
-+ select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
-+ select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
-+ select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
-+ select_peripheral(PC(16), PERIPH_A, 0); /* MDC */
-+ select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
-+
-+ if (!data->is_rmii) {
-+ select_peripheral(PC(0), PERIPH_A, 0); /* COL */
-+ select_peripheral(PC(1), PERIPH_A, 0); /* CRS */
-+ select_peripheral(PC(2), PERIPH_A, 0); /* TXER */
-+ select_peripheral(PC(5), PERIPH_A, 0); /* TXD2 */
-+ select_peripheral(PC(6), PERIPH_A, 0); /* TXD3 */
-+ select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
-+ select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
-+ select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
-+ select_peripheral(PC(18), PERIPH_A, 0); /* SPD */
-+ }
-+ break;
-+
-+ case 1:
-+ pdev = &macb1_device;
-+
-+ select_peripheral(PD(13), PERIPH_B, 0); /* TXD0 */
-+ select_peripheral(PD(14), PERIPH_B, 0); /* TXD1 */
-+ select_peripheral(PD(11), PERIPH_B, 0); /* TXEN */
-+ select_peripheral(PD(12), PERIPH_B, 0); /* TXCK */
-+ select_peripheral(PD(10), PERIPH_B, 0); /* RXD0 */
-+ select_peripheral(PD(6), PERIPH_B, 0); /* RXD1 */
-+ select_peripheral(PD(5), PERIPH_B, 0); /* RXER */
-+ select_peripheral(PD(4), PERIPH_B, 0); /* RXDV */
-+ select_peripheral(PD(3), PERIPH_B, 0); /* MDC */
-+ select_peripheral(PD(2), PERIPH_B, 0); /* MDIO */
-+
-+ if (!data->is_rmii) {
-+ select_peripheral(PC(19), PERIPH_B, 0); /* COL */
-+ select_peripheral(PC(23), PERIPH_B, 0); /* CRS */
-+ select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
-+ select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
-+ select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
-+ select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
-+ select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
-+ select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
-+ select_peripheral(PD(15), PERIPH_B, 0); /* SPD */
-+ }
-+ break;
-+
-+ default:
-+ return NULL;
-+ }
-+
-+ memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
-+ platform_device_register(pdev);
-+
-+ return pdev;
-+}
-+#endif
-+
-+/* --------------------------------------------------------------------
-+ * SPI
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_spi0_resource[] = {
-+ PBMEM(0xffe00000),
-+ IRQ(3),
-+};
-+DEFINE_DEV(atmel_spi, 0);
-+DEV_CLK(spi_clk, atmel_spi0, pba, 0);
-+
-+static struct resource atmel_spi1_resource[] = {
-+ PBMEM(0xffe00400),
-+ IRQ(4),
-+};
-+DEFINE_DEV(atmel_spi, 1);
-+DEV_CLK(spi_clk, atmel_spi1, pba, 1);
-+
-+static void __init
-+at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
-+ unsigned int n, const u8 *pins)
-+{
-+ unsigned int pin, mode;
-+
-+ for (; n; n--, b++) {
-+ b->bus_num = bus_num;
-+ if (b->chip_select >= 4)
-+ continue;
-+ pin = (unsigned)b->controller_data;
-+ if (!pin) {
-+ pin = pins[b->chip_select];
-+ b->controller_data = (void *)pin;
-+ }
-+ mode = AT32_GPIOF_OUTPUT;
-+ if (!(b->mode & SPI_CS_HIGH))
-+ mode |= AT32_GPIOF_HIGH;
-+ at32_select_gpio(pin, mode);
-+ }
-+}
-+
-+struct platform_device *__init
-+at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
-+{
-+ /*
-+ * Manage the chipselects as GPIOs, normally using the same pins
-+ * the SPI controller expects; but boards can use other pins.
-+ */
-+ static u8 __initdata spi0_pins[] =
-+ { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
-+ GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
-+ static u8 __initdata spi1_pins[] =
-+ { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
-+ GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
-+ struct platform_device *pdev;
-+
-+ switch (id) {
-+ case 0:
-+ pdev = &atmel_spi0_device;
-+ select_peripheral(PA(0), PERIPH_A, 0); /* MISO */
-+ select_peripheral(PA(1), PERIPH_A, 0); /* MOSI */
-+ select_peripheral(PA(2), PERIPH_A, 0); /* SCK */
-+ at32_spi_setup_slaves(0, b, n, spi0_pins);
-+ break;
-+
-+ case 1:
-+ pdev = &atmel_spi1_device;
-+ select_peripheral(PB(0), PERIPH_B, 0); /* MISO */
-+ select_peripheral(PB(1), PERIPH_B, 0); /* MOSI */
-+ select_peripheral(PB(5), PERIPH_B, 0); /* SCK */
-+ at32_spi_setup_slaves(1, b, n, spi1_pins);
-+ break;
-+
-+ default:
-+ return NULL;
-+ }
-+
-+ spi_register_board_info(b, n);
-+ platform_device_register(pdev);
-+ return pdev;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * TWI
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_twi0_resource[] __initdata = {
-+ PBMEM(0xffe00800),
-+ IRQ(5),
-+};
-+static struct clk atmel_twi0_pclk = {
-+ .name = "twi_pclk",
-+ .parent = &pba_clk,
-+ .mode = pba_clk_mode,
-+ .get_rate = pba_clk_get_rate,
-+ .index = 2,
-+};
-+
-+struct platform_device *__init at32_add_device_twi(unsigned int id,
-+ struct i2c_board_info *b,
-+ unsigned int n)
-+{
-+ struct platform_device *pdev;
-+
-+ if (id != 0)
-+ return NULL;
-+
-+ pdev = platform_device_alloc("atmel_twi", id);
-+ if (!pdev)
-+ return NULL;
-+
-+ if (platform_device_add_resources(pdev, atmel_twi0_resource,
-+ ARRAY_SIZE(atmel_twi0_resource)))
-+ goto err_add_resources;
-+
-+ select_peripheral(PA(6), PERIPH_A, 0); /* SDA */
-+ select_peripheral(PA(7), PERIPH_A, 0); /* SDL */
-+
-+ atmel_twi0_pclk.dev = &pdev->dev;
-+
-+ if (b)
-+ i2c_register_board_info(id, b, n);
-+
-+ platform_device_add(pdev);
-+ return pdev;
-+
-+err_add_resources:
-+ platform_device_put(pdev);
-+ return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * MMC
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_mci0_resource[] __initdata = {
-+ PBMEM(0xfff02400),
-+ IRQ(28),
-+};
-+static struct clk atmel_mci0_pclk = {
-+ .name = "mci_clk",
-+ .parent = &pbb_clk,
-+ .mode = pbb_clk_mode,
-+ .get_rate = pbb_clk_get_rate,
-+ .index = 9,
-+};
-+
-+struct platform_device *__init
-+at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
-+{
-+ struct platform_device *pdev;
-+
-+ if (id != 0)
-+ return NULL;
-+
-+ pdev = platform_device_alloc("atmel_mci", id);
-+ if (!pdev)
-+ goto fail;
-+
-+ if (platform_device_add_resources(pdev, atmel_mci0_resource,
-+ ARRAY_SIZE(atmel_mci0_resource)))
-+ goto fail;
-+
-+ if (data && platform_device_add_data(pdev, data,
-+ sizeof(struct mci_platform_data)))
-+ goto fail;
-+
-+ select_peripheral(PA(10), PERIPH_A, 0); /* CLK */
-+ select_peripheral(PA(11), PERIPH_A, 0); /* CMD */
-+ select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
-+ select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
-+ select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
-+ select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
-+
-+ if (data) {
-+ if (data->detect_pin != GPIO_PIN_NONE)
-+ at32_select_gpio(data->detect_pin, 0);
-+ if (data->wp_pin != GPIO_PIN_NONE)
-+ at32_select_gpio(data->wp_pin, 0);
-+ }
-+
-+ atmel_mci0_pclk.dev = &pdev->dev;
-+
-+ platform_device_add(pdev);
-+ return pdev;
-+
-+fail:
-+ platform_device_put(pdev);
-+ return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * LCDC
-+ * -------------------------------------------------------------------- */
-+#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
-+static struct atmel_lcdfb_info atmel_lcdfb0_data;
-+static struct resource atmel_lcdfb0_resource[] = {
-+ {
-+ .start = 0xff000000,
-+ .end = 0xff000fff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ IRQ(1),
-+ {
-+ /* Placeholder for pre-allocated fb memory */
-+ .start = 0x00000000,
-+ .end = 0x00000000,
-+ .flags = 0,
-+ },
-+};
-+DEFINE_DEV_DATA(atmel_lcdfb, 0);
-+DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
-+static struct clk atmel_lcdfb0_pixclk = {
-+ .name = "lcdc_clk",
-+ .dev = &atmel_lcdfb0_device.dev,
-+ .mode = genclk_mode,
-+ .get_rate = genclk_get_rate,
-+ .set_rate = genclk_set_rate,
-+ .set_parent = genclk_set_parent,
-+ .index = 7,
-+};
-+
-+struct platform_device *__init
-+at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
-+ unsigned long fbmem_start, unsigned long fbmem_len)
-+{
-+ struct platform_device *pdev;
-+ struct atmel_lcdfb_info *info;
-+ struct fb_monspecs *monspecs;
-+ struct fb_videomode *modedb;
-+ unsigned int modedb_size;
-+
-+ /*
-+ * Do a deep copy of the fb data, monspecs and modedb. Make
-+ * sure all allocations are done before setting up the
-+ * portmux.
-+ */
-+ monspecs = kmemdup(data->default_monspecs,
-+ sizeof(struct fb_monspecs), GFP_KERNEL);
-+ if (!monspecs)
-+ return NULL;
-+
-+ modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
-+ modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
-+ if (!modedb)
-+ goto err_dup_modedb;
-+ monspecs->modedb = modedb;
-+
-+ switch (id) {
-+ case 0:
-+ pdev = &atmel_lcdfb0_device;
-+ select_peripheral(PC(19), PERIPH_A, 0); /* CC */
-+ select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC */
-+ select_peripheral(PC(21), PERIPH_A, 0); /* PCLK */
-+ select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC */
-+ select_peripheral(PC(23), PERIPH_A, 0); /* DVAL */
-+ select_peripheral(PC(24), PERIPH_A, 0); /* MODE */
-+ select_peripheral(PC(25), PERIPH_A, 0); /* PWR */
-+ select_peripheral(PC(26), PERIPH_A, 0); /* DATA0 */
-+ select_peripheral(PC(27), PERIPH_A, 0); /* DATA1 */
-+ select_peripheral(PC(28), PERIPH_A, 0); /* DATA2 */
-+ select_peripheral(PC(29), PERIPH_A, 0); /* DATA3 */
-+ select_peripheral(PC(30), PERIPH_A, 0); /* DATA4 */
-+ select_peripheral(PC(31), PERIPH_A, 0); /* DATA5 */
-+ select_peripheral(PD(0), PERIPH_A, 0); /* DATA6 */
-+ select_peripheral(PD(1), PERIPH_A, 0); /* DATA7 */
-+ select_peripheral(PD(2), PERIPH_A, 0); /* DATA8 */
-+ select_peripheral(PD(3), PERIPH_A, 0); /* DATA9 */
-+ select_peripheral(PD(4), PERIPH_A, 0); /* DATA10 */
-+ select_peripheral(PD(5), PERIPH_A, 0); /* DATA11 */
-+ select_peripheral(PD(6), PERIPH_A, 0); /* DATA12 */
-+ select_peripheral(PD(7), PERIPH_A, 0); /* DATA13 */
-+ select_peripheral(PD(8), PERIPH_A, 0); /* DATA14 */
-+ select_peripheral(PD(9), PERIPH_A, 0); /* DATA15 */
-+ select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
-+ select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
-+ select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
-+ select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
-+ select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
-+ select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
-+ select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
-+ select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
-+
-+ clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
-+ clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
-+ break;
-+
-+ default:
-+ goto err_invalid_id;
-+ }
-+
-+ if (fbmem_len) {
-+ pdev->resource[2].start = fbmem_start;
-+ pdev->resource[2].end = fbmem_start + fbmem_len - 1;
-+ pdev->resource[2].flags = IORESOURCE_MEM;
-+ }
-+
-+ info = pdev->dev.platform_data;
-+ memcpy(info, data, sizeof(struct atmel_lcdfb_info));
-+ info->default_monspecs = monspecs;
-+
-+ platform_device_register(pdev);
-+ return pdev;
-+
-+err_invalid_id:
-+ kfree(modedb);
-+err_dup_modedb:
-+ kfree(monspecs);
-+ return NULL;
-+}
-+#endif
-+
-+/* --------------------------------------------------------------------
-+ * PWM
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_pwm0_resource[] __initdata = {
-+ PBMEM(0xfff01400),
-+ IRQ(24),
-+};
-+static struct clk atmel_pwm0_mck = {
-+ .name = "mck",
-+ .parent = &pbb_clk,
-+ .mode = pbb_clk_mode,
-+ .get_rate = pbb_clk_get_rate,
-+ .index = 5,
-+};
-+
-+struct platform_device *__init at32_add_device_pwm(u32 mask)
-+{
-+ struct platform_device *pdev;
-+
-+ if (!mask)
-+ return NULL;
-+
-+ pdev = platform_device_alloc("atmel_pwm", 0);
-+ if (!pdev)
-+ return NULL;
-+
-+ if (platform_device_add_resources(pdev, atmel_pwm0_resource,
-+ ARRAY_SIZE(atmel_pwm0_resource)))
-+ goto out_free_pdev;
-+
-+ if (platform_device_add_data(pdev, &mask, sizeof(mask)))
-+ goto out_free_pdev;
-+
-+ if (mask & (1 << 0))
-+ select_peripheral(PA(28), PERIPH_A, 0);
-+ if (mask & (1 << 1))
-+ select_peripheral(PA(29), PERIPH_A, 0);
-+ if (mask & (1 << 2))
-+ select_peripheral(PA(21), PERIPH_B, 0);
-+ if (mask & (1 << 3))
-+ select_peripheral(PA(22), PERIPH_B, 0);
-+
-+ atmel_pwm0_mck.dev = &pdev->dev;
-+
-+ platform_device_add(pdev);
-+
-+ return pdev;
-+
-+out_free_pdev:
-+ platform_device_put(pdev);
-+ return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * SSC
-+ * -------------------------------------------------------------------- */
-+static struct resource ssc0_resource[] = {
-+ PBMEM(0xffe01c00),
-+ IRQ(10),
-+};
-+DEFINE_DEV(ssc, 0);
-+DEV_CLK(pclk, ssc0, pba, 7);
-+
-+static struct resource ssc1_resource[] = {
-+ PBMEM(0xffe02000),
-+ IRQ(11),
-+};
-+DEFINE_DEV(ssc, 1);
-+DEV_CLK(pclk, ssc1, pba, 8);
-+
-+static struct resource ssc2_resource[] = {
-+ PBMEM(0xffe02400),
-+ IRQ(12),
-+};
-+DEFINE_DEV(ssc, 2);
-+DEV_CLK(pclk, ssc2, pba, 9);
-+
-+struct platform_device *__init
-+at32_add_device_ssc(unsigned int id, unsigned int flags)
-+{
-+ struct platform_device *pdev;
-+
-+ switch (id) {
-+ case 0:
-+ pdev = &ssc0_device;
-+ if (flags & ATMEL_SSC_RF)
-+ select_peripheral(PA(21), PERIPH_A, 0); /* RF */
-+ if (flags & ATMEL_SSC_RK)
-+ select_peripheral(PA(22), PERIPH_A, 0); /* RK */
-+ if (flags & ATMEL_SSC_TK)
-+ select_peripheral(PA(23), PERIPH_A, 0); /* TK */
-+ if (flags & ATMEL_SSC_TF)
-+ select_peripheral(PA(24), PERIPH_A, 0); /* TF */
-+ if (flags & ATMEL_SSC_TD)
-+ select_peripheral(PA(25), PERIPH_A, 0); /* TD */
-+ if (flags & ATMEL_SSC_RD)
-+ select_peripheral(PA(26), PERIPH_A, 0); /* RD */
-+ break;
-+ case 1:
-+ pdev = &ssc1_device;
-+ if (flags & ATMEL_SSC_RF)
-+ select_peripheral(PA(0), PERIPH_B, 0); /* RF */
-+ if (flags & ATMEL_SSC_RK)
-+ select_peripheral(PA(1), PERIPH_B, 0); /* RK */
-+ if (flags & ATMEL_SSC_TK)
-+ select_peripheral(PA(2), PERIPH_B, 0); /* TK */
-+ if (flags & ATMEL_SSC_TF)
-+ select_peripheral(PA(3), PERIPH_B, 0); /* TF */
-+ if (flags & ATMEL_SSC_TD)
-+ select_peripheral(PA(4), PERIPH_B, 0); /* TD */
-+ if (flags & ATMEL_SSC_RD)
-+ select_peripheral(PA(5), PERIPH_B, 0); /* RD */
-+ break;
-+ case 2:
-+ pdev = &ssc2_device;
-+ if (flags & ATMEL_SSC_TD)
-+ select_peripheral(PB(13), PERIPH_A, 0); /* TD */
-+ if (flags & ATMEL_SSC_RD)
-+ select_peripheral(PB(14), PERIPH_A, 0); /* RD */
-+ if (flags & ATMEL_SSC_TK)
-+ select_peripheral(PB(15), PERIPH_A, 0); /* TK */
-+ if (flags & ATMEL_SSC_TF)
-+ select_peripheral(PB(16), PERIPH_A, 0); /* TF */
-+ if (flags & ATMEL_SSC_RF)
-+ select_peripheral(PB(17), PERIPH_A, 0); /* RF */
-+ if (flags & ATMEL_SSC_RK)
-+ select_peripheral(PB(18), PERIPH_A, 0); /* RK */
-+ break;
-+ default:
-+ return NULL;
-+ }
-+
-+ platform_device_register(pdev);
-+ return pdev;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * USB Device Controller
-+ * -------------------------------------------------------------------- */
-+static struct resource usba0_resource[] __initdata = {
-+ {
-+ .start = 0xff300000,
-+ .end = 0xff3fffff,
-+ .flags = IORESOURCE_MEM,
-+ }, {
-+ .start = 0xfff03000,
-+ .end = 0xfff033ff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ IRQ(31),
-+};
-+static struct clk usba0_pclk = {
-+ .name = "pclk",
-+ .parent = &pbb_clk,
-+ .mode = pbb_clk_mode,
-+ .get_rate = pbb_clk_get_rate,
-+ .index = 12,
-+};
-+static struct clk usba0_hclk = {
-+ .name = "hclk",
-+ .parent = &hsb_clk,
-+ .mode = hsb_clk_mode,
-+ .get_rate = hsb_clk_get_rate,
-+ .index = 6,
-+};
-+
-+#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
-+ [idx] = { \
-+ .name = nam, \
-+ .index = idx, \
-+ .fifo_size = maxpkt, \
-+ .nr_banks = maxbk, \
-+ .can_dma = dma, \
-+ .can_isoc = isoc, \
-+ }
-+
-+static struct usba_ep_data at32_usba_ep[] __initdata = {
-+ EP("ep0", 0, 64, 1, 0, 0),
-+ EP("ep1", 1, 512, 2, 1, 1),
-+ EP("ep2", 2, 512, 2, 1, 1),
-+ EP("ep3-int", 3, 64, 3, 1, 0),
-+ EP("ep4-int", 4, 64, 3, 1, 0),
-+ EP("ep5", 5, 1024, 3, 1, 1),
-+ EP("ep6", 6, 1024, 3, 1, 1),
-+};
-+
-+#undef EP
-+
-+struct platform_device *__init
-+at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
-+{
-+ /*
-+ * pdata doesn't have room for any endpoints, so we need to
-+ * append room for the ones we need right after it.
-+ */
-+ struct {
-+ struct usba_platform_data pdata;
-+ struct usba_ep_data ep[7];
-+ } usba_data;
-+ struct platform_device *pdev;
-+
-+ if (id != 0)
-+ return NULL;
-+
-+ pdev = platform_device_alloc("atmel_usba_udc", 0);
-+ if (!pdev)
-+ return NULL;
-+
-+ if (platform_device_add_resources(pdev, usba0_resource,
-+ ARRAY_SIZE(usba0_resource)))
-+ goto out_free_pdev;
-+
-+ if (data)
-+ usba_data.pdata.vbus_pin = data->vbus_pin;
-+ else
-+ usba_data.pdata.vbus_pin = -EINVAL;
-+
-+ data = &usba_data.pdata;
-+ data->num_ep = ARRAY_SIZE(at32_usba_ep);
-+ memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
-+
-+ if (platform_device_add_data(pdev, data, sizeof(usba_data)))
-+ goto out_free_pdev;
-+
-+ if (data->vbus_pin >= 0)
-+ at32_select_gpio(data->vbus_pin, 0);
-+
-+ usba0_pclk.dev = &pdev->dev;
-+ usba0_hclk.dev = &pdev->dev;
-+
-+ platform_device_add(pdev);
-+
-+ return pdev;
-+
-+out_free_pdev:
-+ platform_device_put(pdev);
-+ return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * IDE / CompactFlash
-+ * -------------------------------------------------------------------- */
-+#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
-+static struct resource at32_smc_cs4_resource[] __initdata = {
-+ {
-+ .start = 0x04000000,
-+ .end = 0x07ffffff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ IRQ(~0UL), /* Magic IRQ will be overridden */
-+};
-+static struct resource at32_smc_cs5_resource[] __initdata = {
-+ {
-+ .start = 0x20000000,
-+ .end = 0x23ffffff,
-+ .flags = IORESOURCE_MEM,
-+ },
-+ IRQ(~0UL), /* Magic IRQ will be overridden */
-+};
-+
-+static int __init at32_init_ide_or_cf(struct platform_device *pdev,
-+ unsigned int cs, unsigned int extint)
-+{
-+ static unsigned int extint_pin_map[4] __initdata = {
-+ GPIO_PIN_PB(25),
-+ GPIO_PIN_PB(26),
-+ GPIO_PIN_PB(27),
-+ GPIO_PIN_PB(28),
-+ };
-+ static bool common_pins_initialized __initdata = false;
-+ unsigned int extint_pin;
-+ int ret;
-+
-+ if (extint >= ARRAY_SIZE(extint_pin_map))
-+ return -EINVAL;
-+ extint_pin = extint_pin_map[extint];
-+
-+ switch (cs) {
-+ case 4:
-+ ret = platform_device_add_resources(pdev,
-+ at32_smc_cs4_resource,
-+ ARRAY_SIZE(at32_smc_cs4_resource));
-+ if (ret)
-+ return ret;
-+
-+ select_peripheral(PE(21), PERIPH_A, 0); /* NCS4 -> OE_N */
-+ set_ebi_sfr_bits(HMATRIX_BIT(CS4A));
-+ break;
-+ case 5:
-+ ret = platform_device_add_resources(pdev,
-+ at32_smc_cs5_resource,
-+ ARRAY_SIZE(at32_smc_cs5_resource));
-+ if (ret)
-+ return ret;
-+
-+ select_peripheral(PE(22), PERIPH_A, 0); /* NCS5 -> OE_N */
-+ set_ebi_sfr_bits(HMATRIX_BIT(CS5A));
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ if (!common_pins_initialized) {
-+ select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1 -> CS0_N */
-+ select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2 -> CS1_N */
-+ select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW -> DIR */
-+ select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT <- IORDY */
-+ common_pins_initialized = true;
-+ }
-+
-+ at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
-+
-+ pdev->resource[1].start = EIM_IRQ_BASE + extint;
-+ pdev->resource[1].end = pdev->resource[1].start;
-+
-+ return 0;
-+}
-+
-+struct platform_device *__init
-+at32_add_device_ide(unsigned int id, unsigned int extint,
-+ struct ide_platform_data *data)
-+{
-+ struct platform_device *pdev;
-+
-+ pdev = platform_device_alloc("at32_ide", id);
-+ if (!pdev)
-+ goto fail;
-+
-+ if (platform_device_add_data(pdev, data,
-+ sizeof(struct ide_platform_data)))
-+ goto fail;
-+
-+ if (at32_init_ide_or_cf(pdev, data->cs, extint))
-+ goto fail;
-+
-+ platform_device_add(pdev);
-+ return pdev;
-+
-+fail:
-+ platform_device_put(pdev);
-+ return NULL;
-+}
-+
-+struct platform_device *__init
-+at32_add_device_cf(unsigned int id, unsigned int extint,
-+ struct cf_platform_data *data)
-+{
-+ struct platform_device *pdev;
-+
-+ pdev = platform_device_alloc("at32_cf", id);
-+ if (!pdev)
-+ goto fail;
-+
-+ if (platform_device_add_data(pdev, data,
-+ sizeof(struct cf_platform_data)))
-+ goto fail;
-+
-+ if (at32_init_ide_or_cf(pdev, data->cs, extint))
-+ goto fail;
-+
-+ if (data->detect_pin != GPIO_PIN_NONE)
-+ at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
-+ if (data->reset_pin != GPIO_PIN_NONE)
-+ at32_select_gpio(data->reset_pin, 0);
-+ if (data->vcc_pin != GPIO_PIN_NONE)
-+ at32_select_gpio(data->vcc_pin, 0);
-+ /* READY is used as extint, so we can't select it as gpio */
-+
-+ platform_device_add(pdev);
-+ return pdev;
-+
-+fail:
-+ platform_device_put(pdev);
-+ return NULL;
-+}
-+#endif
-+
-+/* --------------------------------------------------------------------
-+ * AC97C
-+ * -------------------------------------------------------------------- */
-+static struct resource atmel_ac97c0_resource[] __initdata = {
-+ PBMEM(0xfff02800),
-+ IRQ(29),
-+};
-+static struct clk atmel_ac97c0_pclk = {
-+ .name = "pclk",
-+ .parent = &pbb_clk,
-+ .mode = pbb_clk_mode,
-+ .get_rate = pbb_clk_get_rate,
-+ .index = 10,
-+};
-+
-+struct platform_device *__init at32_add_device_ac97c(unsigned int id)
-+{
-+ struct platform_device *pdev;
-+
-+ if (id != 0)
-+ return NULL;
-+
-+ pdev = platform_device_alloc("atmel_ac97c", id);
-+ if (!pdev)
-+ return NULL;
-+
-+ if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
-+ ARRAY_SIZE(atmel_ac97c0_resource)))
-+ goto err_add_resources;
-+
-+ select_peripheral(PB(20), PERIPH_B, 0); /* SYNC */
-+ select_peripheral(PB(21), PERIPH_B, 0); /* SDO */
-+ select_peripheral(PB(22), PERIPH_B, 0); /* SDI */
-+ select_peripheral(PB(23), PERIPH_B, 0); /* SCLK */
-+
-+ atmel_ac97c0_pclk.dev = &pdev->dev;
-+
-+ platform_device_add(pdev);
-+ return pdev;
-+
-+err_add_resources:
-+ platform_device_put(pdev);
-+ return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * ABDAC
-+ * -------------------------------------------------------------------- */
-+static struct resource abdac0_resource[] __initdata = {
-+ PBMEM(0xfff02000),
-+ IRQ(27),
-+};
-+static struct clk abdac0_pclk = {
-+ .name = "pclk",
-+ .parent = &pbb_clk,
-+ .mode = pbb_clk_mode,
-+ .get_rate = pbb_clk_get_rate,
-+ .index = 8,
-+};
-+static struct clk abdac0_sample_clk = {
-+ .name = "sample_clk",
-+ .mode = genclk_mode,
-+ .get_rate = genclk_get_rate,
-+ .set_rate = genclk_set_rate,
-+ .set_parent = genclk_set_parent,
-+ .index = 6,
-+};
-+
-+struct platform_device *__init at32_add_device_abdac(unsigned int id)
-+{
-+ struct platform_device *pdev;
-+
-+ if (id != 0)
-+ return NULL;
-+
-+ pdev = platform_device_alloc("abdac", id);
-+ if (!pdev)
-+ return NULL;
-+
-+ if (platform_device_add_resources(pdev, abdac0_resource,
-+ ARRAY_SIZE(abdac0_resource)))
-+ goto err_add_resources;
-+
-+ select_peripheral(PB(20), PERIPH_A, 0); /* DATA1 */
-+ select_peripheral(PB(21), PERIPH_A, 0); /* DATA0 */
-+ select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1 */
-+ select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0 */
-+
-+ abdac0_pclk.dev = &pdev->dev;
-+ abdac0_sample_clk.dev = &pdev->dev;
-+
-+ platform_device_add(pdev);
-+ return pdev;
-+
-+err_add_resources:
-+ platform_device_put(pdev);
-+ return NULL;
-+}
-+
-+/* --------------------------------------------------------------------
-+ * GCLK
-+ * -------------------------------------------------------------------- */
-+static struct clk gclk0 = {
-+ .name = "gclk0",
-+ .mode = genclk_mode,
-+ .get_rate = genclk_get_rate,
-+ .set_rate = genclk_set_rate,
-+ .set_parent = genclk_set_parent,
-+ .index = 0,
-+};
-+static struct clk gclk1 = {
-+ .name = "gclk1",
-+ .mode = genclk_mode,
-+ .get_rate = genclk_get_rate,
-+ .set_rate = genclk_set_rate,
-+ .set_parent = genclk_set_parent,
-+ .index = 1,
-+};
-+static struct clk gclk2 = {
-+ .name = "gclk2",
-+ .mode = genclk_mode,
-+ .get_rate = genclk_get_rate,
-+ .set_rate = genclk_set_rate,
-+ .set_parent = genclk_set_parent,
-+ .index = 2,
-+};
-+static struct clk gclk3 = {
-+ .name = "gclk3",
-+ .mode = genclk_mode,
-+ .get_rate = genclk_get_rate,
-+ .set_rate = genclk_set_rate,
-+ .set_parent = genclk_set_parent,
-+ .index = 3,
-+};
-+static struct clk gclk4 = {
-+ .name = "gclk4",
-+ .mode = genclk_mode,
-+ .get_rate = genclk_get_rate,
-+ .set_rate = genclk_set_rate,
-+ .set_parent = genclk_set_parent,
-+ .index = 4,
-+};
-+
-+struct clk *at32_clock_list[] = {
-+ &osc32k,
-+ &osc0,
-+ &osc1,
-+ &pll0,
-+ &pll1,
-+ &cpu_clk,
-+ &hsb_clk,
-+ &pba_clk,
-+ &pbb_clk,
-+ &at32_pm_pclk,
-+ &at32_intc0_pclk,
-+ &hmatrix_clk,
-+ &ebi_clk,
-+ &hramc_clk,
-+ &smc0_pclk,
-+ &smc0_mck,
-+ &pdc_hclk,
-+ &pdc_pclk,
-+ &dmaca0_hclk,
-+ &pico_clk,
-+ &pio0_mck,
-+ &pio1_mck,
-+ &pio2_mck,
-+ &pio3_mck,
-+ &pio4_mck,
-+ &at32_tcb0_t0_clk,
-+ &at32_tcb1_t0_clk,
-+ &atmel_psif0_pclk,
-+ &atmel_psif1_pclk,
-+ &atmel_usart0_usart,
-+ &atmel_usart1_usart,
-+ &atmel_usart2_usart,
-+ &atmel_usart3_usart,
-+ &atmel_pwm0_mck,
-+#if defined(CONFIG_CPU_AT32AP7000)
-+ &macb0_hclk,
-+ &macb0_pclk,
-+ &macb1_hclk,
-+ &macb1_pclk,
-+#endif
-+ &atmel_spi0_spi_clk,
-+ &atmel_spi1_spi_clk,
-+ &atmel_twi0_pclk,
-+ &atmel_mci0_pclk,
-+#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
-+ &atmel_lcdfb0_hck1,
-+ &atmel_lcdfb0_pixclk,
-+#endif
-+ &ssc0_pclk,
-+ &ssc1_pclk,
-+ &ssc2_pclk,
-+ &usba0_hclk,
-+ &usba0_pclk,
-+ &atmel_ac97c0_pclk,
-+ &abdac0_pclk,
-+ &abdac0_sample_clk,
-+ &gclk0,
-+ &gclk1,
-+ &gclk2,
-+ &gclk3,
-+ &gclk4,
-+};
-+unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
-+
-+void __init at32_portmux_init(void)
-+{
-+ at32_init_pio(&pio0_device);
-+ at32_init_pio(&pio1_device);
-+ at32_init_pio(&pio2_device);
-+ at32_init_pio(&pio3_device);
-+ at32_init_pio(&pio4_device);
-+}
-+
-+void __init at32_clock_init(void)
-+{
-+ u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
-+ int i;
-+
-+ if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
-+ main_clock = &pll0;
-+ cpu_clk.parent = &pll0;
-+ } else {
-+ main_clock = &osc0;
-+ cpu_clk.parent = &osc0;
-+ }
-+
-+ if (pm_readl(PLL0) & PM_BIT(PLLOSC))
-+ pll0.parent = &osc1;
-+ if (pm_readl(PLL1) & PM_BIT(PLLOSC))
-+ pll1.parent = &osc1;
-+
-+ genclk_init_parent(&gclk0);
-+ genclk_init_parent(&gclk1);
-+ genclk_init_parent(&gclk2);
-+ genclk_init_parent(&gclk3);
-+ genclk_init_parent(&gclk4);
-+#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
-+ genclk_init_parent(&atmel_lcdfb0_pixclk);
-+#endif
-+ genclk_init_parent(&abdac0_sample_clk);
-+
-+ /*
-+ * Turn on all clocks that have at least one user already, and
-+ * turn off everything else. We only do this for module
-+ * clocks, and even though it isn't particularly pretty to
-+ * check the address of the mode function, it should do the
-+ * trick...
-+ */
-+ for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
-+ struct clk *clk = at32_clock_list[i];
-+
-+ if (clk->users == 0)
-+ continue;
-+
-+ if (clk->mode == &cpu_clk_mode)
-+ cpu_mask |= 1 << clk->index;
-+ else if (clk->mode == &hsb_clk_mode)
-+ hsb_mask |= 1 << clk->index;
-+ else if (clk->mode == &pba_clk_mode)
-+ pba_mask |= 1 << clk->index;
-+ else if (clk->mode == &pbb_clk_mode)
-+ pbb_mask |= 1 << clk->index;
-+ }
-+
-+ pm_writel(CPU_MASK, cpu_mask);
-+ pm_writel(HSB_MASK, hsb_mask);
-+ pm_writel(PBA_MASK, pba_mask);
-+ pm_writel(PBB_MASK, pbb_mask);
-+}
---- a/arch/avr32/mach-at32ap/extint.c
-+++ b/arch/avr32/mach-at32ap/extint.c
-@@ -26,16 +26,10 @@
- #define EIC_MODE 0x0014
- #define EIC_EDGE 0x0018
- #define EIC_LEVEL 0x001c
--#define EIC_TEST 0x0020
- #define EIC_NMIC 0x0024
-
--/* Bitfields in TEST */
--#define EIC_TESTEN_OFFSET 31
--#define EIC_TESTEN_SIZE 1
--
- /* Bitfields in NMIC */
--#define EIC_EN_OFFSET 0
--#define EIC_EN_SIZE 1
-+#define EIC_NMIC_ENABLE (1 << 0)
-
- /* Bit manipulation macros */
- #define EIC_BIT(name) \
-@@ -63,6 +57,9 @@
- unsigned int first_irq;
- };
-
-+static struct eic *nmi_eic;
-+static bool nmi_enabled;
-+
- static void eic_ack_irq(unsigned int irq)
- {
- struct eic *eic = get_irq_chip_data(irq);
-@@ -133,8 +130,11 @@
- eic_writel(eic, EDGE, edge);
- eic_writel(eic, LEVEL, level);
-
-- if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-+ if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
- flow_type |= IRQ_LEVEL;
-+ __set_irq_handler_unlocked(irq, handle_level_irq);
-+ } else
-+ __set_irq_handler_unlocked(irq, handle_edge_irq);
- desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
- desc->status |= flow_type;
- }
-@@ -154,9 +154,8 @@
- static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
- {
- struct eic *eic = desc->handler_data;
-- struct irq_desc *ext_desc;
- unsigned long status, pending;
-- unsigned int i, ext_irq;
-+ unsigned int i;
-
- status = eic_readl(eic, ISR);
- pending = status & eic_readl(eic, IMR);
-@@ -165,15 +164,28 @@
- i = fls(pending) - 1;
- pending &= ~(1 << i);
-
-- ext_irq = i + eic->first_irq;
-- ext_desc = irq_desc + ext_irq;
-- if (ext_desc->status & IRQ_LEVEL)
-- handle_level_irq(ext_irq, ext_desc);
-- else
-- handle_edge_irq(ext_irq, ext_desc);
-+ generic_handle_irq(i + eic->first_irq);
- }
- }
-
-+int nmi_enable(void)
-+{
-+ nmi_enabled = true;
-+
-+ if (nmi_eic)
-+ eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
-+
-+ return 0;
-+}
-+
-+void nmi_disable(void)
-+{
-+ if (nmi_eic)
-+ eic_writel(nmi_eic, NMIC, 0);
-+
-+ nmi_enabled = false;
-+}
-+
- static int __init eic_probe(struct platform_device *pdev)
- {
- struct eic *eic;
-@@ -214,14 +226,13 @@
- pattern = eic_readl(eic, MODE);
- nr_irqs = fls(pattern);
-
-- /* Trigger on falling edge unless overridden by driver */
-- eic_writel(eic, MODE, 0UL);
-+ /* Trigger on low level unless overridden by driver */
- eic_writel(eic, EDGE, 0UL);
-+ eic_writel(eic, LEVEL, 0UL);
-
- eic->chip = &eic_chip;
-
- for (i = 0; i < nr_irqs; i++) {
-- /* NOTE the handler we set here is ignored by the demux */
- set_irq_chip_and_handler(eic->first_irq + i, &eic_chip,
- handle_level_irq);
- set_irq_chip_data(eic->first_irq + i, eic);
-@@ -230,6 +241,16 @@
- set_irq_chained_handler(int_irq, demux_eic_irq);
- set_irq_data(int_irq, eic);
-
-+ if (pdev->id == 0) {
-+ nmi_eic = eic;
-+ if (nmi_enabled)
-+ /*
-+ * Someone tried to enable NMI before we were
-+ * ready. Do it now.
-+ */
-+ nmi_enable();
-+ }
-+
- dev_info(&pdev->dev,
- "External Interrupt Controller at 0x%p, IRQ %u\n",
- eic->regs, int_irq);
+-arch_initcall(at32_cpufreq_init);
++late_initcall(at32_cpufreq_init);
--- /dev/null
+++ b/arch/avr32/mach-at32ap/gpio-dev.c
@@ -0,0 +1,573 @@
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
-+#include <linux/poll.h>
-+#include <linux/uaccess.h>
-+#include <linux/wait.h>
-+
-+#include <asm/gpio.h>
-+#include <asm/arch/portmux.h>
-+
-+#define GPIO_DEV_MAX 8
-+
-+static struct class *gpio_dev_class;
-+static dev_t gpio_devt;
-+
-+struct gpio_item {
-+ spinlock_t lock;
-+
-+ int enabled;
-+ int initialized;
-+ int port;
-+ u32 pin_mask;
-+ u32 oe_mask;
-+
-+ /* Pin state last time we read it (for blocking reads) */
-+ u32 pin_state;
-+ int changed;
-+
-+ wait_queue_head_t change_wq;
-+ struct fasync_struct *async_queue;
-+
-+ int id;
-+ struct class_device *gpio_dev;
-+ struct cdev char_dev;
-+ struct config_item item;
-+};
-+
-+struct gpio_attribute {
-+ struct configfs_attribute attr;
-+ ssize_t (*show)(struct gpio_item *, char *);
-+ ssize_t (*store)(struct gpio_item *, const char *, size_t);
-+};
-+
-+static irqreturn_t gpio_dev_interrupt(int irq, void *dev_id)
-+{
-+ struct gpio_item *gpio = dev_id;
-+ u32 old_state, new_state;
-+
-+ old_state = gpio->pin_state;
-+ new_state = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
-+ gpio->pin_state = new_state;
-+
-+ if (new_state != old_state) {
-+ gpio->changed = 1;
-+ wake_up_interruptible(&gpio->change_wq);
-+
-+ if (gpio->async_queue)
-+ kill_fasync(&gpio->async_queue, SIGIO, POLL_IN);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int gpio_dev_open(struct inode *inode, struct file *file)
-+{
-+ struct gpio_item *gpio = container_of(inode->i_cdev,
-+ struct gpio_item,
-+ char_dev);
-+ unsigned int irq;
-+ unsigned int i;
-+ int ret;
-+
-+ nonseekable_open(inode, file);
-+ config_item_get(&gpio->item);
-+ file->private_data = gpio;
-+
-+ gpio->pin_state = at32_gpio_get_value_multiple(gpio->port,
-+ gpio->pin_mask);
-+ gpio->changed = 1;
-+
-+ for (i = 0; i < 32; i++) {
-+ if (gpio->pin_mask & (1 << i)) {
-+ irq = gpio_to_irq(32 * gpio->port + i);
-+ ret = request_irq(irq, gpio_dev_interrupt, 0,
-+ "gpio-dev", gpio);
-+ if (ret)
-+ goto err_irq;
-+ }
-+ }
-+
-+ return 0;
-+
-+err_irq:
-+ while (i--) {
-+ if (gpio->pin_mask & (1 << i)) {
-+ irq = gpio_to_irq(32 * gpio->port + i);
-+ free_irq(irq, gpio);
-+ }
-+ }
-+
-+ config_item_put(&gpio->item);
-+
-+ return ret;
-+}
-+
-+static int gpio_dev_fasync(int fd, struct file *file, int mode)
-+{
-+ struct gpio_item *gpio = file->private_data;
-+
-+ return fasync_helper(fd, file, mode, &gpio->async_queue);
-+}
-+
-+static int gpio_dev_release(struct inode *inode, struct file *file)
-+{
-+ struct gpio_item *gpio = file->private_data;
-+ unsigned int irq;
-+ unsigned int i;
-+
-+ gpio_dev_fasync(-1, file, 0);
-+
-+ for (i = 0; i < 32; i++) {
-+ if (gpio->pin_mask & (1 << i)) {
-+ irq = gpio_to_irq(32 * gpio->port + i);
-+ free_irq(irq, gpio);
-+ }
-+ }
-+
-+ config_item_put(&gpio->item);
-+
-+ return 0;
-+}
-+
-+static unsigned int gpio_dev_poll(struct file *file, poll_table *wait)
-+{
-+ struct gpio_item *gpio = file->private_data;
-+ unsigned int mask = 0;
-+
-+ poll_wait(file, &gpio->change_wq, wait);
-+ if (gpio->changed)
-+ mask |= POLLIN | POLLRDNORM;
-+
-+ return mask;
-+}
-+
-+static ssize_t gpio_dev_read(struct file *file, char __user *buf,
-+ size_t count, loff_t *offset)
-+{
-+ struct gpio_item *gpio = file->private_data;
-+ u32 value;
-+
-+ spin_lock_irq(&gpio->lock);
-+ while (!gpio->changed) {
-+ spin_unlock_irq(&gpio->lock);
-+
-+ if (file->f_flags & O_NONBLOCK)
-+ return -EAGAIN;
-+
-+ if (wait_event_interruptible(gpio->change_wq, gpio->changed))
-+ return -ERESTARTSYS;
-+
-+ spin_lock_irq(&gpio->lock);
-+ }
-+
-+ gpio->changed = 0;
-+ value = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
-+
-+ spin_unlock_irq(&gpio->lock);
-+
-+ count = min(count, (size_t)4);
-+ if (copy_to_user(buf, &value, count))
-+ return -EFAULT;
-+
-+ return count;
-+}
-+
-+static ssize_t gpio_dev_write(struct file *file, const char __user *buf,
-+ size_t count, loff_t *offset)
-+{
-+ struct gpio_item *gpio = file->private_data;
-+ u32 value = 0;
-+ u32 mask = ~0UL;
-+
-+ count = min(count, (size_t)4);
-+ if (copy_from_user(&value, buf, count))
-+ return -EFAULT;
-+
-+ /* Assuming big endian */
-+ mask <<= (4 - count) * 8;
-+ mask &= gpio->pin_mask;
-+
-+ at32_gpio_set_value_multiple(gpio->port, value, mask);
-+
-+ return count;
-+}
-+
-+static struct file_operations gpio_dev_fops = {
-+ .owner = THIS_MODULE,
-+ .llseek = no_llseek,
-+ .open = gpio_dev_open,
-+ .release = gpio_dev_release,
-+ .fasync = gpio_dev_fasync,
-+ .poll = gpio_dev_poll,
-+ .read = gpio_dev_read,
-+ .write = gpio_dev_write,
-+};
-+
-+static struct gpio_item *to_gpio_item(struct config_item *item)
-+{
-+ return item ? container_of(item, struct gpio_item, item) : NULL;
-+}
-+
-+static ssize_t gpio_show_gpio_id(struct gpio_item *gpio, char *page)
-+{
-+ return sprintf(page, "%d\n", gpio->port);
-+}
-+
-+static ssize_t gpio_store_gpio_id(struct gpio_item *gpio,
-+ const char *page, size_t count)
-+{
-+ unsigned long id;
-+ char *p = (char *)page;
-+ ssize_t ret = -EINVAL;
-+
-+ id = simple_strtoul(p, &p, 0);
-+ if (!p || (*p && (*p != '\n')))
-+ return -EINVAL;
-+
-+ /* Switching PIO is not allowed when live... */
-+ spin_lock(&gpio->lock);
-+ if (!gpio->enabled) {
-+ ret = -ENXIO;
-+ if (at32_gpio_port_is_valid(id)) {
-+ gpio->port = id;
-+ ret = count;
-+ }
-+ }
-+ spin_unlock(&gpio->lock);
++#include <linux/poll.h>
++#include <linux/uaccess.h>
++#include <linux/wait.h>
+
-+ return ret;
-+}
++#include <asm/gpio.h>
++#include <asm/arch/portmux.h>
+
-+static ssize_t gpio_show_pin_mask(struct gpio_item *gpio, char *page)
-+{
-+ return sprintf(page, "0x%08x\n", gpio->pin_mask);
-+}
++#define GPIO_DEV_MAX 8
+
-+static ssize_t gpio_store_pin_mask(struct gpio_item *gpio,
-+ const char *page, size_t count)
-+{
-+ u32 new_mask;
-+ char *p = (char *)page;
-+ ssize_t ret = -EINVAL;
++static struct class *gpio_dev_class;
++static dev_t gpio_devt;
+
-+ new_mask = simple_strtoul(p, &p, 0);
-+ if (!p || (*p && (*p != '\n')))
-+ return -EINVAL;
++struct gpio_item {
++ spinlock_t lock;
+
-+ /* Can't update the pin mask while live. */
-+ spin_lock(&gpio->lock);
-+ if (!gpio->enabled) {
-+ gpio->oe_mask &= new_mask;
-+ gpio->pin_mask = new_mask;
-+ ret = count;
-+ }
-+ spin_unlock(&gpio->lock);
++ int enabled;
++ int initialized;
++ int port;
++ u32 pin_mask;
++ u32 oe_mask;
+
-+ return ret;
-+}
++ /* Pin state last time we read it (for blocking reads) */
++ u32 pin_state;
++ int changed;
+
-+static ssize_t gpio_show_oe_mask(struct gpio_item *gpio, char *page)
-+{
-+ return sprintf(page, "0x%08x\n", gpio->oe_mask);
-+}
++ wait_queue_head_t change_wq;
++ struct fasync_struct *async_queue;
+
-+static ssize_t gpio_store_oe_mask(struct gpio_item *gpio,
-+ const char *page, size_t count)
++ int id;
++ struct class_device *gpio_dev;
++ struct cdev char_dev;
++ struct config_item item;
++};
++
++struct gpio_attribute {
++ struct configfs_attribute attr;
++ ssize_t (*show)(struct gpio_item *, char *);
++ ssize_t (*store)(struct gpio_item *, const char *, size_t);
++};
++
++static irqreturn_t gpio_dev_interrupt(int irq, void *dev_id)
+{
-+ u32 mask;
-+ char *p = (char *)page;
-+ ssize_t ret = -EINVAL;
++ struct gpio_item *gpio = dev_id;
++ u32 old_state, new_state;
+
-+ mask = simple_strtoul(p, &p, 0);
-+ if (!p || (*p && (*p != '\n')))
-+ return -EINVAL;
++ old_state = gpio->pin_state;
++ new_state = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
++ gpio->pin_state = new_state;
+
-+ spin_lock(&gpio->lock);
-+ if (!gpio->enabled) {
-+ gpio->oe_mask = mask & gpio->pin_mask;
-+ ret = count;
-+ }
-+ spin_unlock(&gpio->lock);
++ if (new_state != old_state) {
++ gpio->changed = 1;
++ wake_up_interruptible(&gpio->change_wq);
+
-+ return ret;
-+}
++ if (gpio->async_queue)
++ kill_fasync(&gpio->async_queue, SIGIO, POLL_IN);
++ }
+
-+static ssize_t gpio_show_enabled(struct gpio_item *gpio, char *page)
-+{
-+ return sprintf(page, "%d\n", gpio->enabled);
++ return IRQ_HANDLED;
+}
+
-+static ssize_t gpio_store_enabled(struct gpio_item *gpio,
-+ const char *page, size_t count)
++static int gpio_dev_open(struct inode *inode, struct file *file)
+{
-+ char *p = (char *)page;
-+ int enabled;
++ struct gpio_item *gpio = container_of(inode->i_cdev,
++ struct gpio_item,
++ char_dev);
++ unsigned int irq;
++ unsigned int i;
+ int ret;
+
-+ enabled = simple_strtoul(p, &p, 0);
-+ if (!p || (*p && (*p != '\n')))
-+ return -EINVAL;
-+
-+ /* make it a boolean value */
-+ enabled = !!enabled;
-+
-+ if (gpio->enabled == enabled)
-+ /* No change; do nothing. */
-+ return count;
++ nonseekable_open(inode, file);
++ config_item_get(&gpio->item);
++ file->private_data = gpio;
+
-+ BUG_ON(gpio->id >= GPIO_DEV_MAX);
++ gpio->pin_state = at32_gpio_get_value_multiple(gpio->port,
++ gpio->pin_mask);
++ gpio->changed = 1;
+
-+ if (!enabled) {
-+ class_device_unregister(gpio->gpio_dev);
-+ cdev_del(&gpio->char_dev);
-+ at32_deselect_pins(gpio->port, gpio->pin_mask);
-+ gpio->initialized = 0;
-+ } else {
-+ if (gpio->port < 0 || !gpio->pin_mask)
-+ return -ENODEV;
++ for (i = 0; i < 32; i++) {
++ if (gpio->pin_mask & (1 << i)) {
++ irq = gpio_to_irq(32 * gpio->port + i);
++ ret = request_irq(irq, gpio_dev_interrupt, 0,
++ "gpio-dev", gpio);
++ if (ret)
++ goto err_irq;
++ }
+ }
+
-+ /* Disallow any updates to gpio_id or pin_mask */
-+ spin_lock(&gpio->lock);
-+ gpio->enabled = enabled;
-+ spin_unlock(&gpio->lock);
-+
-+ if (!enabled)
-+ return count;
-+
-+ /* Now, try to allocate the pins */
-+ ret = at32_select_gpio_pins(gpio->port, gpio->pin_mask, gpio->oe_mask);
-+ if (ret)
-+ goto err_alloc_pins;
-+
-+ gpio->initialized = 1;
++ return 0;
+
-+ cdev_init(&gpio->char_dev, &gpio_dev_fops);
-+ gpio->char_dev.owner = THIS_MODULE;
-+ ret = cdev_add(&gpio->char_dev, MKDEV(MAJOR(gpio_devt), gpio->id), 1);
-+ if (ret < 0)
-+ goto err_cdev_add;
-+ gpio->gpio_dev = class_device_create(gpio_dev_class, NULL,
-+ MKDEV(MAJOR(gpio_devt), gpio->id),
-+ NULL,
-+ "gpio%d", gpio->id);
-+ if (IS_ERR(gpio->gpio_dev)) {
-+ printk(KERN_ERR "failed to create gpio%d\n", gpio->id);
-+ ret = PTR_ERR(gpio->gpio_dev);
-+ goto err_class_dev;
++err_irq:
++ while (i--) {
++ if (gpio->pin_mask & (1 << i)) {
++ irq = gpio_to_irq(32 * gpio->port + i);
++ free_irq(irq, gpio);
++ }
+ }
+
-+ printk(KERN_INFO "created gpio%d (port%d/0x%08x) as (%d:%d)\n",
-+ gpio->id, gpio->port, gpio->pin_mask,
-+ MAJOR(gpio->gpio_dev->devt), MINOR(gpio->gpio_dev->devt));
-+
-+ return 0;
-+
-+err_class_dev:
-+ cdev_del(&gpio->char_dev);
-+err_cdev_add:
-+ at32_deselect_pins(gpio->port, gpio->pin_mask);
-+ gpio->initialized = 0;
-+err_alloc_pins:
-+ spin_lock(&gpio->lock);
-+ gpio->enabled = 0;
-+ spin_unlock(&gpio->lock);
++ config_item_put(&gpio->item);
+
+ return ret;
+}
+
-+static struct gpio_attribute gpio_item_attr_gpio_id = {
-+ .attr = {
-+ .ca_owner = THIS_MODULE,
-+ .ca_name = "gpio_id",
-+ .ca_mode = S_IRUGO | S_IWUSR,
-+ },
-+ .show = gpio_show_gpio_id,
-+ .store = gpio_store_gpio_id,
-+};
-+static struct gpio_attribute gpio_item_attr_pin_mask = {
-+ .attr = {
-+ .ca_owner = THIS_MODULE,
-+ .ca_name = "pin_mask",
-+ .ca_mode = S_IRUGO | S_IWUSR,
-+ },
-+ .show = gpio_show_pin_mask,
-+ .store = gpio_store_pin_mask,
-+};
-+static struct gpio_attribute gpio_item_attr_oe_mask = {
-+ .attr = {
-+ .ca_owner = THIS_MODULE,
-+ .ca_name = "oe_mask",
-+ .ca_mode = S_IRUGO | S_IWUSR,
-+ },
-+ .show = gpio_show_oe_mask,
-+ .store = gpio_store_oe_mask,
-+};
-+static struct gpio_attribute gpio_item_attr_enabled = {
-+ .attr = {
-+ .ca_owner = THIS_MODULE,
-+ .ca_name = "enabled",
-+ .ca_mode = S_IRUGO | S_IWUSR,
-+ },
-+ .show = gpio_show_enabled,
-+ .store = gpio_store_enabled,
-+};
++static int gpio_dev_fasync(int fd, struct file *file, int mode)
++{
++ struct gpio_item *gpio = file->private_data;
+
-+static struct configfs_attribute *gpio_item_attrs[] = {
-+ &gpio_item_attr_gpio_id.attr,
-+ &gpio_item_attr_pin_mask.attr,
-+ &gpio_item_attr_oe_mask.attr,
-+ &gpio_item_attr_enabled.attr,
-+ NULL,
-+};
++ return fasync_helper(fd, file, mode, &gpio->async_queue);
++}
+
-+static ssize_t gpio_show_attr(struct config_item *item,
-+ struct configfs_attribute *attr,
-+ char *page)
++static int gpio_dev_release(struct inode *inode, struct file *file)
+{
-+ struct gpio_item *gpio_item = to_gpio_item(item);
-+ struct gpio_attribute *gpio_attr
-+ = container_of(attr, struct gpio_attribute, attr);
-+ ssize_t ret = 0;
++ struct gpio_item *gpio = file->private_data;
++ unsigned int irq;
++ unsigned int i;
++
++ gpio_dev_fasync(-1, file, 0);
++
++ for (i = 0; i < 32; i++) {
++ if (gpio->pin_mask & (1 << i)) {
++ irq = gpio_to_irq(32 * gpio->port + i);
++ free_irq(irq, gpio);
++ }
++ }
++
++ config_item_put(&gpio->item);
+
-+ if (gpio_attr->show)
-+ ret = gpio_attr->show(gpio_item, page);
-+ return ret;
++ return 0;
+}
+
-+static ssize_t gpio_store_attr(struct config_item *item,
-+ struct configfs_attribute *attr,
-+ const char *page, size_t count)
++static unsigned int gpio_dev_poll(struct file *file, poll_table *wait)
+{
-+ struct gpio_item *gpio_item = to_gpio_item(item);
-+ struct gpio_attribute *gpio_attr
-+ = container_of(attr, struct gpio_attribute, attr);
-+ ssize_t ret = -EINVAL;
++ struct gpio_item *gpio = file->private_data;
++ unsigned int mask = 0;
+
-+ if (gpio_attr->store)
-+ ret = gpio_attr->store(gpio_item, page, count);
-+ return ret;
++ poll_wait(file, &gpio->change_wq, wait);
++ if (gpio->changed)
++ mask |= POLLIN | POLLRDNORM;
++
++ return mask;
+}
+
-+static void gpio_release(struct config_item *item)
++static ssize_t gpio_dev_read(struct file *file, char __user *buf,
++ size_t count, loff_t *offset)
+{
-+ kfree(to_gpio_item(item));
-+}
++ struct gpio_item *gpio = file->private_data;
++ u32 value;
+
-+static struct configfs_item_operations gpio_item_ops = {
-+ .release = gpio_release,
-+ .show_attribute = gpio_show_attr,
-+ .store_attribute = gpio_store_attr,
-+};
++ spin_lock_irq(&gpio->lock);
++ while (!gpio->changed) {
++ spin_unlock_irq(&gpio->lock);
+
-+static struct config_item_type gpio_item_type = {
-+ .ct_item_ops = &gpio_item_ops,
-+ .ct_attrs = gpio_item_attrs,
-+ .ct_owner = THIS_MODULE,
-+};
++ if (file->f_flags & O_NONBLOCK)
++ return -EAGAIN;
+
-+static struct config_item *gpio_make_item(struct config_group *group,
-+ const char *name)
-+{
-+ static int next_id;
-+ struct gpio_item *gpio;
++ if (wait_event_interruptible(gpio->change_wq, gpio->changed))
++ return -ERESTARTSYS;
+
-+ if (next_id >= GPIO_DEV_MAX)
-+ return NULL;
++ spin_lock_irq(&gpio->lock);
++ }
+
-+ gpio = kzalloc(sizeof(struct gpio_item), GFP_KERNEL);
-+ if (!gpio)
-+ return NULL;
++ gpio->changed = 0;
++ value = at32_gpio_get_value_multiple(gpio->port, gpio->pin_mask);
+
-+ gpio->id = next_id++;
-+ config_item_init_type_name(&gpio->item, name, &gpio_item_type);
-+ spin_lock_init(&gpio->lock);
-+ init_waitqueue_head(&gpio->change_wq);
++ spin_unlock_irq(&gpio->lock);
+
-+ return &gpio->item;
++ count = min(count, (size_t)4);
++ if (copy_to_user(buf, &value, count))
++ return -EFAULT;
++
++ return count;
+}
+
-+static void gpio_drop_item(struct config_group *group,
-+ struct config_item *item)
++static ssize_t gpio_dev_write(struct file *file, const char __user *buf,
++ size_t count, loff_t *offset)
+{
-+ struct gpio_item *gpio = to_gpio_item(item);
++ struct gpio_item *gpio = file->private_data;
++ u32 value = 0;
++ u32 mask = ~0UL;
+
-+ spin_lock(&gpio->lock);
-+ if (gpio->enabled) {
-+ class_device_unregister(gpio->gpio_dev);
-+ cdev_del(&gpio->char_dev);
-+ }
++ count = min(count, (size_t)4);
++ if (copy_from_user(&value, buf, count))
++ return -EFAULT;
+
-+ if (gpio->initialized) {
-+ at32_deselect_pins(gpio->port, gpio->pin_mask);
-+ gpio->initialized = 0;
-+ gpio->enabled = 0;
-+ }
-+ spin_unlock(&gpio->lock);
++ /* Assuming big endian */
++ mask <<= (4 - count) * 8;
++ mask &= gpio->pin_mask;
++
++ at32_gpio_set_value_multiple(gpio->port, value, mask);
++
++ return count;
+}
+
-+static struct configfs_group_operations gpio_group_ops = {
-+ .make_item = gpio_make_item,
-+ .drop_item = gpio_drop_item,
++static struct file_operations gpio_dev_fops = {
++ .owner = THIS_MODULE,
++ .llseek = no_llseek,
++ .open = gpio_dev_open,
++ .release = gpio_dev_release,
++ .fasync = gpio_dev_fasync,
++ .poll = gpio_dev_poll,
++ .read = gpio_dev_read,
++ .write = gpio_dev_write,
+};
+
-+static struct config_item_type gpio_group_type = {
-+ .ct_group_ops = &gpio_group_ops,
-+ .ct_owner = THIS_MODULE,
-+};
++static struct gpio_item *to_gpio_item(struct config_item *item)
++{
++ return item ? container_of(item, struct gpio_item, item) : NULL;
++}
+
-+static struct configfs_subsystem gpio_subsys = {
-+ .su_group = {
-+ .cg_item = {
-+ .ci_namebuf = "gpio",
-+ .ci_type = &gpio_group_type,
-+ },
-+ },
-+};
++static ssize_t gpio_show_gpio_id(struct gpio_item *gpio, char *page)
++{
++ return sprintf(page, "%d\n", gpio->port);
++}
+
-+static int __init gpio_dev_init(void)
++static ssize_t gpio_store_gpio_id(struct gpio_item *gpio,
++ const char *page, size_t count)
+{
-+ int err;
++ unsigned long id;
++ char *p = (char *)page;
++ ssize_t ret = -EINVAL;
+
-+ gpio_dev_class = class_create(THIS_MODULE, "gpio-dev");
-+ if (IS_ERR(gpio_dev_class)) {
-+ err = PTR_ERR(gpio_dev_class);
-+ goto err_class_create;
++ id = simple_strtoul(p, &p, 0);
++ if (!p || (*p && (*p != '\n')))
++ return -EINVAL;
++
++ /* Switching PIO is not allowed when live... */
++ spin_lock(&gpio->lock);
++ if (!gpio->enabled) {
++ ret = -ENXIO;
++ if (at32_gpio_port_is_valid(id)) {
++ gpio->port = id;
++ ret = count;
++ }
+ }
++ spin_unlock(&gpio->lock);
+
-+ err = alloc_chrdev_region(&gpio_devt, 0, GPIO_DEV_MAX, "gpio");
-+ if (err < 0)
-+ goto err_alloc_chrdev;
++ return ret;
++}
+
-+ /* Configfs initialization */
-+ config_group_init(&gpio_subsys.su_group);
-+ mutex_init(&gpio_subsys.su_mutex);
-+ err = configfs_register_subsystem(&gpio_subsys);
-+ if (err)
-+ goto err_register_subsys;
++static ssize_t gpio_show_pin_mask(struct gpio_item *gpio, char *page)
++{
++ return sprintf(page, "0x%08x\n", gpio->pin_mask);
++}
+
-+ return 0;
++static ssize_t gpio_store_pin_mask(struct gpio_item *gpio,
++ const char *page, size_t count)
++{
++ u32 new_mask;
++ char *p = (char *)page;
++ ssize_t ret = -EINVAL;
+
-+err_register_subsys:
-+ unregister_chrdev_region(gpio_devt, GPIO_DEV_MAX);
-+err_alloc_chrdev:
-+ class_destroy(gpio_dev_class);
-+err_class_create:
-+ printk(KERN_WARNING "Failed to initialize gpio /dev interface\n");
-+ return err;
++ new_mask = simple_strtoul(p, &p, 0);
++ if (!p || (*p && (*p != '\n')))
++ return -EINVAL;
++
++ /* Can't update the pin mask while live. */
++ spin_lock(&gpio->lock);
++ if (!gpio->enabled) {
++ gpio->oe_mask &= new_mask;
++ gpio->pin_mask = new_mask;
++ ret = count;
++ }
++ spin_unlock(&gpio->lock);
++
++ return ret;
+}
-+late_initcall(gpio_dev_init);
---- a/arch/avr32/mach-at32ap/intc.c
-+++ b/arch/avr32/mach-at32ap/intc.c
-@@ -13,7 +13,6 @@
- #include <linux/irq.h>
- #include <linux/platform_device.h>
-
--#include <asm/intc.h>
- #include <asm/io.h>
-
- #include "intc.h"
---- a/arch/avr32/mach-at32ap/Kconfig
-+++ b/arch/avr32/mach-at32ap/Kconfig
-@@ -3,9 +3,9 @@
- menu "Atmel AVR32 AP options"
-
- choice
-- prompt "AT32AP7000 static memory bus width"
-- depends on CPU_AT32AP7000
-- default AP7000_16_BIT_SMC
-+ prompt "AT32AP700x static memory bus width"
-+ depends on CPU_AT32AP700X
-+ default AP700X_16_BIT_SMC
- help
- Define the width of the AP7000 external static memory interface.
- This is used to determine how to mangle the address and/or data
-@@ -15,17 +15,24 @@
- width for all chip selects, excluding the flash (which is using
- raw access and is thus not affected by any of this.)
-
--config AP7000_32_BIT_SMC
-+config AP700X_32_BIT_SMC
- bool "32 bit"
-
--config AP7000_16_BIT_SMC
-+config AP700X_16_BIT_SMC
- bool "16 bit"
-
--config AP7000_8_BIT_SMC
-+config AP700X_8_BIT_SMC
- bool "8 bit"
-
- endchoice
-
-+config GPIO_DEV
-+ bool "GPIO /dev interface"
-+ select CONFIGFS_FS
-+ default n
-+ help
-+ Say `Y' to enable a /dev interface to the GPIO pins.
+
- endmenu
-
- endif # PLATFORM_AT32AP
---- a/arch/avr32/mach-at32ap/Makefile
-+++ b/arch/avr32/mach-at32ap/Makefile
-@@ -1,4 +1,4 @@
- obj-y += at32ap.o clock.o intc.o extint.o pio.o hsmc.o
--obj-$(CONFIG_CPU_AT32AP7000) += at32ap7000.o
--obj-$(CONFIG_CPU_AT32AP7000) += time-tc.o
-+obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
- obj-$(CONFIG_CPU_FREQ_AT32AP) += cpufreq.o
-+obj-$(CONFIG_GPIO_DEV) += gpio-dev.o
---- a/arch/avr32/mach-at32ap/pio.c
-+++ b/arch/avr32/mach-at32ap/pio.c
-@@ -162,6 +162,82 @@
- dump_stack();
- }
-
-+#ifdef CONFIG_GPIO_DEV
++static ssize_t gpio_show_oe_mask(struct gpio_item *gpio, char *page)
++{
++ return sprintf(page, "0x%08x\n", gpio->oe_mask);
++}
++
++static ssize_t gpio_store_oe_mask(struct gpio_item *gpio,
++ const char *page, size_t count)
++{
++ u32 mask;
++ char *p = (char *)page;
++ ssize_t ret = -EINVAL;
++
++ mask = simple_strtoul(p, &p, 0);
++ if (!p || (*p && (*p != '\n')))
++ return -EINVAL;
+
-+/* Gang allocators and accessors; used by the GPIO /dev driver */
-+int at32_gpio_port_is_valid(unsigned int port)
++ spin_lock(&gpio->lock);
++ if (!gpio->enabled) {
++ gpio->oe_mask = mask & gpio->pin_mask;
++ ret = count;
++ }
++ spin_unlock(&gpio->lock);
++
++ return ret;
++}
++
++static ssize_t gpio_show_enabled(struct gpio_item *gpio, char *page)
+{
-+ return port < MAX_NR_PIO_DEVICES && pio_dev[port].regs != NULL;
++ return sprintf(page, "%d\n", gpio->enabled);
+}
+
-+int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask)
++static ssize_t gpio_store_enabled(struct gpio_item *gpio,
++ const char *page, size_t count)
+{
-+ struct pio_device *pio;
-+ u32 old, new;
++ char *p = (char *)page;
++ int enabled;
++ int ret;
+
-+ pio = &pio_dev[port];
-+ BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs || (oe_mask & ~pins));
++ enabled = simple_strtoul(p, &p, 0);
++ if (!p || (*p && (*p != '\n')))
++ return -EINVAL;
+
-+ /* Try to allocate the pins */
-+ do {
-+ old = pio->pinmux_mask;
-+ if (old & pins)
-+ return -EBUSY;
++ /* make it a boolean value */
++ enabled = !!enabled;
+
-+ new = old | pins;
-+ } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
++ if (gpio->enabled == enabled)
++ /* No change; do nothing. */
++ return count;
+
-+ /* That went well, now configure the port */
-+ pio_writel(pio, OER, oe_mask);
-+ pio_writel(pio, PER, pins);
++ BUG_ON(gpio->id >= GPIO_DEV_MAX);
+
-+ return 0;
-+}
++ if (!enabled) {
++ class_device_unregister(gpio->gpio_dev);
++ cdev_del(&gpio->char_dev);
++ at32_deselect_pins(gpio->port, gpio->pin_mask);
++ gpio->initialized = 0;
++ } else {
++ if (gpio->port < 0 || !gpio->pin_mask)
++ return -ENODEV;
++ }
+
-+void at32_deselect_pins(unsigned int port, u32 pins)
-+{
-+ struct pio_device *pio;
-+ u32 old, new;
++ /* Disallow any updates to gpio_id or pin_mask */
++ spin_lock(&gpio->lock);
++ gpio->enabled = enabled;
++ spin_unlock(&gpio->lock);
+
-+ pio = &pio_dev[port];
-+ BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
++ if (!enabled)
++ return count;
+
-+ /* Return to a "safe" mux configuration */
-+ pio_writel(pio, PUER, pins);
-+ pio_writel(pio, ODR, pins);
++ /* Now, try to allocate the pins */
++ ret = at32_select_gpio_pins(gpio->port, gpio->pin_mask, gpio->oe_mask);
++ if (ret)
++ goto err_alloc_pins;
+
-+ /* Deallocate the pins */
-+ do {
-+ old = pio->pinmux_mask;
-+ new = old & ~pins;
-+ } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
-+}
++ gpio->initialized = 1;
+
-+u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins)
-+{
-+ struct pio_device *pio;
++ cdev_init(&gpio->char_dev, &gpio_dev_fops);
++ gpio->char_dev.owner = THIS_MODULE;
++ ret = cdev_add(&gpio->char_dev, MKDEV(MAJOR(gpio_devt), gpio->id), 1);
++ if (ret < 0)
++ goto err_cdev_add;
++ gpio->gpio_dev = class_device_create(gpio_dev_class, NULL,
++ MKDEV(MAJOR(gpio_devt), gpio->id),
++ NULL,
++ "gpio%d", gpio->id);
++ if (IS_ERR(gpio->gpio_dev)) {
++ printk(KERN_ERR "failed to create gpio%d\n", gpio->id);
++ ret = PTR_ERR(gpio->gpio_dev);
++ goto err_class_dev;
++ }
+
-+ pio = &pio_dev[port];
-+ BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
++ printk(KERN_INFO "created gpio%d (port%d/0x%08x) as (%d:%d)\n",
++ gpio->id, gpio->port, gpio->pin_mask,
++ MAJOR(gpio->gpio_dev->devt), MINOR(gpio->gpio_dev->devt));
+
-+ return pio_readl(pio, PDSR) & pins;
++ return 0;
++
++err_class_dev:
++ cdev_del(&gpio->char_dev);
++err_cdev_add:
++ at32_deselect_pins(gpio->port, gpio->pin_mask);
++ gpio->initialized = 0;
++err_alloc_pins:
++ spin_lock(&gpio->lock);
++ gpio->enabled = 0;
++ spin_unlock(&gpio->lock);
++
++ return ret;
+}
+
-+void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask)
-+{
-+ struct pio_device *pio;
++static struct gpio_attribute gpio_item_attr_gpio_id = {
++ .attr = {
++ .ca_owner = THIS_MODULE,
++ .ca_name = "gpio_id",
++ .ca_mode = S_IRUGO | S_IWUSR,
++ },
++ .show = gpio_show_gpio_id,
++ .store = gpio_store_gpio_id,
++};
++static struct gpio_attribute gpio_item_attr_pin_mask = {
++ .attr = {
++ .ca_owner = THIS_MODULE,
++ .ca_name = "pin_mask",
++ .ca_mode = S_IRUGO | S_IWUSR,
++ },
++ .show = gpio_show_pin_mask,
++ .store = gpio_store_pin_mask,
++};
++static struct gpio_attribute gpio_item_attr_oe_mask = {
++ .attr = {
++ .ca_owner = THIS_MODULE,
++ .ca_name = "oe_mask",
++ .ca_mode = S_IRUGO | S_IWUSR,
++ },
++ .show = gpio_show_oe_mask,
++ .store = gpio_store_oe_mask,
++};
++static struct gpio_attribute gpio_item_attr_enabled = {
++ .attr = {
++ .ca_owner = THIS_MODULE,
++ .ca_name = "enabled",
++ .ca_mode = S_IRUGO | S_IWUSR,
++ },
++ .show = gpio_show_enabled,
++ .store = gpio_store_enabled,
++};
+
-+ pio = &pio_dev[port];
-+ BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
++static struct configfs_attribute *gpio_item_attrs[] = {
++ &gpio_item_attr_gpio_id.attr,
++ &gpio_item_attr_pin_mask.attr,
++ &gpio_item_attr_oe_mask.attr,
++ &gpio_item_attr_enabled.attr,
++ NULL,
++};
+
-+ /* No atomic updates for now... */
-+ pio_writel(pio, CODR, ~value & mask);
-+ pio_writel(pio, SODR, value & mask);
-+}
++static ssize_t gpio_show_attr(struct config_item *item,
++ struct configfs_attribute *attr,
++ char *page)
++{
++ struct gpio_item *gpio_item = to_gpio_item(item);
++ struct gpio_attribute *gpio_attr
++ = container_of(attr, struct gpio_attribute, attr);
++ ssize_t ret = 0;
+
-+#endif /* CONFIG_GPIO_DEV */
++ if (gpio_attr->show)
++ ret = gpio_attr->show(gpio_item, page);
++ return ret;
++}
+
++static ssize_t gpio_store_attr(struct config_item *item,
++ struct configfs_attribute *attr,
++ const char *page, size_t count)
++{
++ struct gpio_item *gpio_item = to_gpio_item(item);
++ struct gpio_attribute *gpio_attr
++ = container_of(attr, struct gpio_attribute, attr);
++ ssize_t ret = -EINVAL;
+
- /*--------------------------------------------------------------------------*/
-
- /* GPIO API */
---- /dev/null
-+++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
-@@ -0,0 +1,66 @@
-+/*
-+ * Low-level Power Management code.
-+ *
-+ * Copyright (C) 2008 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#include <asm/asm.h>
-+#include <asm/asm-offsets.h>
-+#include <asm/thread_info.h>
-+#include <asm/arch/pm.h>
++ if (gpio_attr->store)
++ ret = gpio_attr->store(gpio_item, page, count);
++ return ret;
++}
+
-+ .section .bss, "wa", @nobits
-+ .global disable_idle_sleep
-+ .type disable_idle_sleep, @object
-+disable_idle_sleep:
-+ .int 4
-+ .size disable_idle_sleep, . - disable_idle_sleep
++static void gpio_release(struct config_item *item)
++{
++ kfree(to_gpio_item(item));
++}
+
-+ /* Keep this close to the irq handlers */
-+ .section .irq.text, "ax", @progbits
++static struct configfs_item_operations gpio_item_ops = {
++ .release = gpio_release,
++ .show_attribute = gpio_show_attr,
++ .store_attribute = gpio_store_attr,
++};
+
-+ /*
-+ * void cpu_enter_idle(void)
-+ *
-+ * Put the CPU into "idle" mode, in which it will consume
-+ * significantly less power.
-+ *
-+ * If an interrupt comes along in the window between
-+ * unmask_interrupts and the sleep instruction below, the
-+ * interrupt code will adjust the return address so that we
-+ * never execute the sleep instruction. This is required
-+ * because the AP7000 doesn't unmask interrupts when entering
-+ * sleep modes; later CPUs may not need this workaround.
-+ */
-+ .global cpu_enter_idle
-+ .type cpu_enter_idle, @function
-+cpu_enter_idle:
-+ mask_interrupts
-+ get_thread_info r8
-+ ld.w r9, r8[TI_flags]
-+ bld r9, TIF_NEED_RESCHED
-+ brcs .Lret_from_sleep
-+ sbr r9, TIF_CPU_GOING_TO_SLEEP
-+ st.w r8[TI_flags], r9
-+ unmask_interrupts
-+ sleep CPU_SLEEP_IDLE
-+ .size cpu_idle_sleep, . - cpu_idle_sleep
++static struct config_item_type gpio_item_type = {
++ .ct_item_ops = &gpio_item_ops,
++ .ct_attrs = gpio_item_attrs,
++ .ct_owner = THIS_MODULE,
++};
+
-+ /*
-+ * Common return path for PM functions that don't run from
-+ * SRAM.
-+ */
-+ .global cpu_idle_skip_sleep
-+ .type cpu_idle_skip_sleep, @function
-+cpu_idle_skip_sleep:
-+ mask_interrupts
-+ ld.w r9, r8[TI_flags]
-+ cbr r9, TIF_CPU_GOING_TO_SLEEP
-+ st.w r8[TI_flags], r9
-+.Lret_from_sleep:
-+ unmask_interrupts
-+ retal r12
-+ .size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
---- a/arch/avr32/mach-at32ap/time-tc.c
-+++ /dev/null
-@@ -1,218 +0,0 @@
--/*
-- * Copyright (C) 2004-2007 Atmel Corporation
-- *
-- * Based on MIPS implementation arch/mips/kernel/time.c
-- * Copyright 2001 MontaVista Software Inc.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--
--#include <linux/clk.h>
--#include <linux/clocksource.h>
--#include <linux/time.h>
--#include <linux/module.h>
--#include <linux/interrupt.h>
--#include <linux/irq.h>
--#include <linux/kernel_stat.h>
--#include <linux/errno.h>
--#include <linux/init.h>
--#include <linux/profile.h>
--#include <linux/sysdev.h>
--#include <linux/err.h>
--
--#include <asm/div64.h>
--#include <asm/sysreg.h>
--#include <asm/io.h>
--#include <asm/sections.h>
--
--#include <asm/arch/time.h>
--
--/* how many counter cycles in a jiffy? */
--static u32 cycles_per_jiffy;
--
--/* the count value for the next timer interrupt */
--static u32 expirelo;
--
--/* the I/O registers of the TC module */
--static void __iomem *ioregs;
--
--cycle_t read_cycle_count(void)
--{
-- return (cycle_t)timer_read(ioregs, 0, CV);
--}
--
--struct clocksource clocksource_avr32 = {
-- .name = "avr32",
-- .rating = 342,
-- .read = read_cycle_count,
-- .mask = CLOCKSOURCE_MASK(16),
-- .shift = 16,
-- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
--};
--
--static void avr32_timer_ack(void)
--{
-- u16 count = expirelo;
--
-- /* Ack this timer interrupt and set the next one, use a u16
-- * variable so it will wrap around correctly */
-- count += cycles_per_jiffy;
-- expirelo = count;
-- timer_write(ioregs, 0, RC, expirelo);
--
-- /* Check to see if we have missed any timer interrupts */
-- count = timer_read(ioregs, 0, CV);
-- if ((count - expirelo) < 0x7fff) {
-- expirelo = count + cycles_per_jiffy;
-- timer_write(ioregs, 0, RC, expirelo);
-- }
--}
--
--u32 avr32_hpt_read(void)
--{
-- return timer_read(ioregs, 0, CV);
--}
--
--static int avr32_timer_calc_div_and_set_jiffies(struct clk *pclk)
--{
-- unsigned int cycles_max = (clocksource_avr32.mask + 1) / 2;
-- unsigned int divs[] = { 4, 8, 16, 32 };
-- int divs_size = ARRAY_SIZE(divs);
-- int i = 0;
-- unsigned long count_hz;
-- unsigned long shift;
-- unsigned long mult;
-- int clock_div = -1;
-- u64 tmp;
--
-- shift = clocksource_avr32.shift;
--
-- do {
-- count_hz = clk_get_rate(pclk) / divs[i];
-- mult = clocksource_hz2mult(count_hz, shift);
-- clocksource_avr32.mult = mult;
--
-- tmp = TICK_NSEC;
-- tmp <<= shift;
-- tmp += mult / 2;
-- do_div(tmp, mult);
--
-- cycles_per_jiffy = tmp;
-- } while (cycles_per_jiffy > cycles_max && ++i < divs_size);
--
-- clock_div = i + 1;
--
-- if (clock_div > divs_size) {
-- pr_debug("timer: could not calculate clock divider\n");
-- return -EFAULT;
-- }
--
-- /* Set the clock divider */
-- timer_write(ioregs, 0, CMR, TIMER_BF(CMR_TCCLKS, clock_div));
--
-- return 0;
--}
--
--int avr32_hpt_init(unsigned int count)
--{
-- struct resource *regs;
-- struct clk *pclk;
-- int irq = -1;
-- int ret = 0;
--
-- ret = -ENXIO;
--
-- irq = platform_get_irq(&at32_systc0_device, 0);
-- if (irq < 0) {
-- pr_debug("timer: could not get irq\n");
-- goto out_error;
-- }
--
-- pclk = clk_get(&at32_systc0_device.dev, "pclk");
-- if (IS_ERR(pclk)) {
-- pr_debug("timer: could not get clk: %ld\n", PTR_ERR(pclk));
-- goto out_error;
-- }
-- clk_enable(pclk);
--
-- regs = platform_get_resource(&at32_systc0_device, IORESOURCE_MEM, 0);
-- if (!regs) {
-- pr_debug("timer: could not get resource\n");
-- goto out_error_clk;
-- }
--
-- ioregs = ioremap(regs->start, regs->end - regs->start + 1);
-- if (!ioregs) {
-- pr_debug("timer: could not get ioregs\n");
-- goto out_error_clk;
-- }
--
-- ret = avr32_timer_calc_div_and_set_jiffies(pclk);
-- if (ret)
-- goto out_error_io;
--
-- ret = setup_irq(irq, &timer_irqaction);
-- if (ret) {
-- pr_debug("timer: could not request irq %d: %d\n",
-- irq, ret);
-- goto out_error_io;
-- }
--
-- expirelo = (timer_read(ioregs, 0, CV) / cycles_per_jiffy + 1)
-- * cycles_per_jiffy;
--
-- /* Enable clock and interrupts on RC compare */
-- timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_CLKEN));
-- timer_write(ioregs, 0, IER, TIMER_BIT(IER_CPCS));
-- /* Set cycles to first interrupt */
-- timer_write(ioregs, 0, RC, expirelo);
--
-- printk(KERN_INFO "timer: AT32AP system timer/counter at 0x%p irq %d\n",
-- ioregs, irq);
--
-- return 0;
--
--out_error_io:
-- iounmap(ioregs);
--out_error_clk:
-- clk_put(pclk);
--out_error:
-- return ret;
--}
--
--int avr32_hpt_start(void)
--{
-- timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_SWTRG));
-- return 0;
--}
--
--irqreturn_t timer_interrupt(int irq, void *dev_id)
--{
-- unsigned int sr = timer_read(ioregs, 0, SR);
--
-- if (sr & TIMER_BIT(SR_CPCS)) {
-- /* ack timer interrupt and try to set next interrupt */
-- avr32_timer_ack();
--
-- /*
-- * Call the generic timer interrupt handler
-- */
-- write_seqlock(&xtime_lock);
-- do_timer(1);
-- write_sequnlock(&xtime_lock);
--
-- /*
-- * In UP mode, we call local_timer_interrupt() to do profiling
-- * and process accounting.
-- *
-- * SMP is not supported yet.
-- */
-- local_timer_interrupt(irq, dev_id);
--
-- return IRQ_HANDLED;
-- }
--
-- return IRQ_NONE;
--}
---- a/arch/avr32/Makefile
-+++ b/arch/avr32/Makefile
-@@ -16,7 +16,7 @@
- CFLAGS_MODULE += -mno-relax
- LDFLAGS_vmlinux += --relax
++static struct config_item *gpio_make_item(struct config_group *group,
++ const char *name)
++{
++ static int next_id;
++ struct gpio_item *gpio;
++
++ if (next_id >= GPIO_DEV_MAX)
++ return NULL;
++
++ gpio = kzalloc(sizeof(struct gpio_item), GFP_KERNEL);
++ if (!gpio)
++ return NULL;
++
++ gpio->id = next_id++;
++ config_item_init_type_name(&gpio->item, name, &gpio_item_type);
++ spin_lock_init(&gpio->lock);
++ init_waitqueue_head(&gpio->change_wq);
++
++ return &gpio->item;
++}
++
++static void gpio_drop_item(struct config_group *group,
++ struct config_item *item)
++{
++ struct gpio_item *gpio = to_gpio_item(item);
++
++ spin_lock(&gpio->lock);
++ if (gpio->enabled) {
++ class_device_unregister(gpio->gpio_dev);
++ cdev_del(&gpio->char_dev);
++ }
++
++ if (gpio->initialized) {
++ at32_deselect_pins(gpio->port, gpio->pin_mask);
++ gpio->initialized = 0;
++ gpio->enabled = 0;
++ }
++ spin_unlock(&gpio->lock);
++}
++
++static struct configfs_group_operations gpio_group_ops = {
++ .make_item = gpio_make_item,
++ .drop_item = gpio_drop_item,
++};
++
++static struct config_item_type gpio_group_type = {
++ .ct_group_ops = &gpio_group_ops,
++ .ct_owner = THIS_MODULE,
++};
++
++static struct configfs_subsystem gpio_subsys = {
++ .su_group = {
++ .cg_item = {
++ .ci_namebuf = "gpio",
++ .ci_type = &gpio_group_type,
++ },
++ },
++};
++
++static int __init gpio_dev_init(void)
++{
++ int err;
++
++ gpio_dev_class = class_create(THIS_MODULE, "gpio-dev");
++ if (IS_ERR(gpio_dev_class)) {
++ err = PTR_ERR(gpio_dev_class);
++ goto err_class_create;
++ }
++
++ err = alloc_chrdev_region(&gpio_devt, 0, GPIO_DEV_MAX, "gpio");
++ if (err < 0)
++ goto err_alloc_chrdev;
++
++ /* Configfs initialization */
++ config_group_init(&gpio_subsys.su_group);
++ mutex_init(&gpio_subsys.su_mutex);
++ err = configfs_register_subsystem(&gpio_subsys);
++ if (err)
++ goto err_register_subsys;
++
++ return 0;
++
++err_register_subsys:
++ unregister_chrdev_region(gpio_devt, GPIO_DEV_MAX);
++err_alloc_chrdev:
++ class_destroy(gpio_dev_class);
++err_class_create:
++ printk(KERN_WARNING "Failed to initialize gpio /dev interface\n");
++ return err;
++}
++late_initcall(gpio_dev_init);
+--- a/arch/avr32/mach-at32ap/hsmc.c
++++ b/arch/avr32/mach-at32ap/hsmc.c
+@@ -278,4 +278,4 @@
+ {
+ return platform_driver_register(&hsmc_driver);
+ }
+-arch_initcall(hsmc_init);
++core_initcall(hsmc_init);
+--- a/arch/avr32/mach-at32ap/intc.c
++++ b/arch/avr32/mach-at32ap/intc.c
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2006 Atmel Corporation
++ * Copyright (C) 2006, 2008 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -12,15 +12,20 @@
+ #include <linux/interrupt.h>
+ #include <linux/irq.h>
+ #include <linux/platform_device.h>
++#include <linux/sysdev.h>
--cpuflags-$(CONFIG_CPU_AT32AP7000) += -mcpu=ap7000
-+cpuflags-$(CONFIG_PLATFORM_AT32AP) += -march=ap
+-#include <asm/intc.h>
+ #include <asm/io.h>
- KBUILD_CFLAGS += $(cpuflags-y)
- KBUILD_AFLAGS += $(cpuflags-y)
-@@ -31,6 +31,8 @@
- core-$(CONFIG_LOADER_U_BOOT) += arch/avr32/boot/u-boot/
- core-y += arch/avr32/kernel/
- core-y += arch/avr32/mm/
-+drivers-$(CONFIG_OPROFILE) += arch/avr32/oprofile/
-+drivers-y += arch/avr32/drivers/
- libs-y += arch/avr32/lib/
+ #include "intc.h"
- archincdir-$(CONFIG_PLATFORM_AT32AP) := arch-at32ap
---- a/arch/avr32/mm/dma-coherent.c
-+++ b/arch/avr32/mm/dma-coherent.c
-@@ -41,6 +41,13 @@
- struct page *page, *free, *end;
- int order;
-
-+ /* Following is a work-around (a.k.a. hack) to prevent pages
-+ * with __GFP_COMP being passed to split_page() which cannot
-+ * handle them. The real problem is that this flag probably
-+ * should be 0 on AVR32 as it is not supported on this
-+ * platform--see CONFIG_HUGETLB_PAGE. */
-+ gfp &= ~(__GFP_COMP);
-+
- size = PAGE_ALIGN(size);
- order = get_order(size);
-
---- a/arch/avr32/mm/fault.c
-+++ b/arch/avr32/mm/fault.c
-@@ -189,6 +189,8 @@
-
- page = sysreg_read(PTBR);
- printk(KERN_ALERT "ptbr = %08lx", page);
-+ if (address >= TASK_SIZE)
-+ page = (unsigned long)swapper_pg_dir;
- if (page) {
- page = ((unsigned long *)page)[address >> 22];
- printk(" pgd = %08lx", page);
---- a/arch/avr32/mm/tlb.c
-+++ b/arch/avr32/mm/tlb.c
-@@ -348,7 +348,7 @@
- return 0;
+ struct intc {
+- void __iomem *regs;
+- struct irq_chip chip;
++ void __iomem *regs;
++ struct irq_chip chip;
++ struct sys_device sysdev;
++#ifdef CONFIG_PM
++ unsigned long suspend_ipr;
++ unsigned long saved_ipr[64];
++#endif
+ };
+
+ extern struct platform_device at32_intc0_device;
+@@ -137,6 +142,74 @@
+ panic("Interrupt controller initialization failed!\n");
}
--static struct seq_operations tlb_ops = {
-+static const struct seq_operations tlb_ops = {
- .start = tlb_start,
- .next = tlb_next,
- .stop = tlb_stop,
---- /dev/null
-+++ b/arch/avr32/oprofile/Makefile
-@@ -0,0 +1,8 @@
-+obj-$(CONFIG_OPROFILE) += oprofile.o
-+
-+oprofile-y := $(addprefix ../../../drivers/oprofile/, \
-+ oprof.o cpu_buffer.o buffer_sync.o \
-+ event_buffer.o oprofile_files.o \
-+ oprofilefs.o oprofile_stats.o \
-+ timer_int.o)
-+oprofile-y += op_model_avr32.o
++#ifdef CONFIG_PM
++void intc_set_suspend_handler(unsigned long offset)
++{
++ intc0.suspend_ipr = offset;
++}
++
++static int intc_suspend(struct sys_device *sdev, pm_message_t state)
++{
++ struct intc *intc = container_of(sdev, struct intc, sysdev);
++ int i;
++
++ if (unlikely(!irqs_disabled())) {
++ pr_err("intc_suspend: called with interrupts enabled\n");
++ return -EINVAL;
++ }
++
++ if (unlikely(!intc->suspend_ipr)) {
++ pr_err("intc_suspend: suspend_ipr not initialized\n");
++ return -EINVAL;
++ }
++
++ for (i = 0; i < 64; i++) {
++ intc->saved_ipr[i] = intc_readl(intc, INTPR0 + 4 * i);
++ intc_writel(intc, INTPR0 + 4 * i, intc->suspend_ipr);
++ }
++
++ return 0;
++}
++
++static int intc_resume(struct sys_device *sdev)
++{
++ struct intc *intc = container_of(sdev, struct intc, sysdev);
++ int i;
++
++ WARN_ON(!irqs_disabled());
++
++ for (i = 0; i < 64; i++)
++ intc_writel(intc, INTPR0 + 4 * i, intc->saved_ipr[i]);
++
++ return 0;
++}
++#else
++#define intc_suspend NULL
++#define intc_resume NULL
++#endif
++
++static struct sysdev_class intc_class = {
++ .name = "intc",
++ .suspend = intc_suspend,
++ .resume = intc_resume,
++};
++
++static int __init intc_init_sysdev(void)
++{
++ int ret;
++
++ ret = sysdev_class_register(&intc_class);
++ if (ret)
++ return ret;
++
++ intc0.sysdev.id = 0;
++ intc0.sysdev.cls = &intc_class;
++ ret = sysdev_register(&intc0.sysdev);
++
++ return ret;
++}
++device_initcall(intc_init_sysdev);
++
+ unsigned long intc_get_pending(unsigned int group)
+ {
+ return intc_readl(&intc0, INTREQ0 + 4 * group);
--- /dev/null
-+++ b/arch/avr32/oprofile/op_model_avr32.c
-@@ -0,0 +1,234 @@
++++ b/arch/avr32/mach-at32ap/pdc.c
+@@ -0,0 +1,48 @@
+/*
-+ * AVR32 Performance Counter Driver
-+ *
-+ * Copyright (C) 2005-2007 Atmel Corporation
++ * Copyright (C) 2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
-+ *
-+ * Author: Ronny Pedersen
+ */
-+#include <linux/errno.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
-+#include <linux/oprofile.h>
-+#include <linux/sched.h>
-+#include <linux/types.h>
+
-+#include <asm/sysreg.h>
-+#include <asm/system.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
+
-+#define AVR32_PERFCTR_IRQ_GROUP 0
-+#define AVR32_PERFCTR_IRQ_LINE 1
++static int __init pdc_probe(struct platform_device *pdev)
++{
++ struct clk *pclk, *hclk;
+
-+enum { PCCNT, PCNT0, PCNT1, NR_counter };
++ pclk = clk_get(&pdev->dev, "pclk");
++ if (IS_ERR(pclk)) {
++ dev_err(&pdev->dev, "no pclk defined\n");
++ return PTR_ERR(pclk);
++ }
++ hclk = clk_get(&pdev->dev, "hclk");
++ if (IS_ERR(hclk)) {
++ dev_err(&pdev->dev, "no hclk defined\n");
++ clk_put(pclk);
++ return PTR_ERR(hclk);
++ }
+
-+struct avr32_perf_counter {
-+ unsigned long enabled;
-+ unsigned long event;
-+ unsigned long count;
-+ unsigned long unit_mask;
-+ unsigned long kernel;
-+ unsigned long user;
++ clk_enable(pclk);
++ clk_enable(hclk);
+
-+ u32 ie_mask;
-+ u32 flag_mask;
-+};
++ dev_info(&pdev->dev, "Atmel Peripheral DMA Controller enabled\n");
++ return 0;
++}
+
-+static struct avr32_perf_counter counter[NR_counter] = {
-+ {
-+ .ie_mask = SYSREG_BIT(IEC),
-+ .flag_mask = SYSREG_BIT(FC),
-+ }, {
-+ .ie_mask = SYSREG_BIT(IE0),
-+ .flag_mask = SYSREG_BIT(F0),
-+ }, {
-+ .ie_mask = SYSREG_BIT(IE1),
-+ .flag_mask = SYSREG_BIT(F1),
++static struct platform_driver pdc_driver = {
++ .probe = pdc_probe,
++ .driver = {
++ .name = "pdc",
+ },
+};
+
-+static void avr32_perf_counter_reset(void)
++static int __init pdc_init(void)
+{
-+ /* Reset all counter and disable/clear all interrupts */
-+ sysreg_write(PCCR, (SYSREG_BIT(PCCR_R)
-+ | SYSREG_BIT(PCCR_C)
-+ | SYSREG_BIT(FC)
-+ | SYSREG_BIT(F0)
-+ | SYSREG_BIT(F1)));
++ return platform_driver_register(&pdc_driver);
+}
++arch_initcall(pdc_init);
+--- a/arch/avr32/mach-at32ap/pio.c
++++ b/arch/avr32/mach-at32ap/pio.c
+@@ -157,6 +157,82 @@
+ dump_stack();
+ }
+
++#ifdef CONFIG_GPIO_DEV
+
-+static irqreturn_t avr32_perf_counter_interrupt(int irq, void *dev_id)
++/* Gang allocators and accessors; used by the GPIO /dev driver */
++int at32_gpio_port_is_valid(unsigned int port)
+{
-+ struct avr32_perf_counter *ctr = dev_id;
-+ struct pt_regs *regs;
-+ u32 pccr;
-+
-+ if (likely(!(intc_get_pending(AVR32_PERFCTR_IRQ_GROUP)
-+ & (1 << AVR32_PERFCTR_IRQ_LINE))))
-+ return IRQ_NONE;
++ return port < MAX_NR_PIO_DEVICES && pio_dev[port].regs != NULL;
++}
+
-+ regs = get_irq_regs();
-+ pccr = sysreg_read(PCCR);
++int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask)
++{
++ struct pio_device *pio;
++ u32 old, new;
+
-+ /* Clear the interrupt flags we're about to handle */
-+ sysreg_write(PCCR, pccr);
++ pio = &pio_dev[port];
++ BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs || (oe_mask & ~pins));
+
-+ /* PCCNT */
-+ if (ctr->enabled && (pccr & ctr->flag_mask)) {
-+ sysreg_write(PCCNT, -ctr->count);
-+ oprofile_add_sample(regs, PCCNT);
-+ }
-+ ctr++;
-+ /* PCNT0 */
-+ if (ctr->enabled && (pccr & ctr->flag_mask)) {
-+ sysreg_write(PCNT0, -ctr->count);
-+ oprofile_add_sample(regs, PCNT0);
-+ }
-+ ctr++;
-+ /* PCNT1 */
-+ if (ctr->enabled && (pccr & ctr->flag_mask)) {
-+ sysreg_write(PCNT1, -ctr->count);
-+ oprofile_add_sample(regs, PCNT1);
-+ }
++ /* Try to allocate the pins */
++ do {
++ old = pio->pinmux_mask;
++ if (old & pins)
++ return -EBUSY;
+
-+ return IRQ_HANDLED;
-+}
++ new = old | pins;
++ } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
+
-+static int avr32_perf_counter_create_files(struct super_block *sb,
-+ struct dentry *root)
-+{
-+ struct dentry *dir;
-+ unsigned int i;
-+ char filename[4];
-+
-+ for (i = 0; i < NR_counter; i++) {
-+ snprintf(filename, sizeof(filename), "%u", i);
-+ dir = oprofilefs_mkdir(sb, root, filename);
-+
-+ oprofilefs_create_ulong(sb, dir, "enabled",
-+ &counter[i].enabled);
-+ oprofilefs_create_ulong(sb, dir, "event",
-+ &counter[i].event);
-+ oprofilefs_create_ulong(sb, dir, "count",
-+ &counter[i].count);
-+
-+ /* Dummy entries */
-+ oprofilefs_create_ulong(sb, dir, "kernel",
-+ &counter[i].kernel);
-+ oprofilefs_create_ulong(sb, dir, "user",
-+ &counter[i].user);
-+ oprofilefs_create_ulong(sb, dir, "unit_mask",
-+ &counter[i].unit_mask);
-+ }
++ /* That went well, now configure the port */
++ pio_writel(pio, OER, oe_mask);
++ pio_writel(pio, PER, pins);
+
+ return 0;
+}
+
-+static int avr32_perf_counter_setup(void)
++void at32_deselect_pins(unsigned int port, u32 pins)
+{
-+ struct avr32_perf_counter *ctr;
-+ u32 pccr;
-+ int ret;
-+ int i;
-+
-+ pr_debug("avr32_perf_counter_setup\n");
-+
-+ if (sysreg_read(PCCR) & SYSREG_BIT(PCCR_E)) {
-+ printk(KERN_ERR
-+ "oprofile: setup: perf counter already enabled\n");
-+ return -EBUSY;
-+ }
++ struct pio_device *pio;
++ u32 old, new;
+
-+ ret = request_irq(AVR32_PERFCTR_IRQ_GROUP,
-+ avr32_perf_counter_interrupt, IRQF_SHARED,
-+ "oprofile", counter);
-+ if (ret)
-+ return ret;
++ pio = &pio_dev[port];
++ BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
+
-+ avr32_perf_counter_reset();
++ /* Return to a "safe" mux configuration */
++ pio_writel(pio, PUER, pins);
++ pio_writel(pio, ODR, pins);
+
-+ pccr = 0;
-+ for (i = PCCNT; i < NR_counter; i++) {
-+ ctr = &counter[i];
-+ if (!ctr->enabled)
-+ continue;
++ /* Deallocate the pins */
++ do {
++ old = pio->pinmux_mask;
++ new = old & ~pins;
++ } while (cmpxchg(&pio->pinmux_mask, old, new) != old);
++}
+
-+ pr_debug("enabling counter %d...\n", i);
++u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins)
++{
++ struct pio_device *pio;
+
-+ pccr |= ctr->ie_mask;
++ pio = &pio_dev[port];
++ BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
+
-+ switch (i) {
-+ case PCCNT:
-+ /* PCCNT always counts cycles, so no events */
-+ sysreg_write(PCCNT, -ctr->count);
-+ break;
-+ case PCNT0:
-+ pccr |= SYSREG_BF(CONF0, ctr->event);
-+ sysreg_write(PCNT0, -ctr->count);
-+ break;
-+ case PCNT1:
-+ pccr |= SYSREG_BF(CONF1, ctr->event);
-+ sysreg_write(PCNT1, -ctr->count);
-+ break;
-+ }
-+ }
++ return pio_readl(pio, PDSR) & pins;
++}
+
-+ pr_debug("oprofile: writing 0x%x to PCCR...\n", pccr);
++void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask)
++{
++ struct pio_device *pio;
+
-+ sysreg_write(PCCR, pccr);
++ pio = &pio_dev[port];
++ BUG_ON(port > ARRAY_SIZE(pio_dev) || !pio->regs);
+
-+ return 0;
++ /* No atomic updates for now... */
++ pio_writel(pio, CODR, ~value & mask);
++ pio_writel(pio, SODR, value & mask);
+}
+
-+static void avr32_perf_counter_shutdown(void)
-+{
-+ pr_debug("avr32_perf_counter_shutdown\n");
++#endif /* CONFIG_GPIO_DEV */
+
-+ avr32_perf_counter_reset();
-+ free_irq(AVR32_PERFCTR_IRQ_GROUP, counter);
-+}
+
-+static int avr32_perf_counter_start(void)
-+{
-+ pr_debug("avr32_perf_counter_start\n");
+ /*--------------------------------------------------------------------------*/
+
+ /* GPIO API */
+@@ -318,6 +394,8 @@
+ const char *label;
+
+ label = gpiochip_is_requested(chip, i);
++ if (!label && (imr & mask))
++ label = "[irq]";
+ if (!label)
+ continue;
+
+--- a/arch/avr32/mach-at32ap/pio.h
++++ b/arch/avr32/mach-at32ap/pio.h
+@@ -57,7 +57,7 @@
+
+ /* Bitfields in IFDR */
+
+-/* Bitfields in ISFR */
++/* Bitfields in IFSR */
+
+ /* Bitfields in SODR */
+
+--- /dev/null
++++ b/arch/avr32/mach-at32ap/pm-at32ap700x.S
+@@ -0,0 +1,174 @@
++/*
++ * Low-level Power Management code.
++ *
++ * Copyright (C) 2008 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <asm/asm.h>
++#include <asm/asm-offsets.h>
++#include <asm/thread_info.h>
++#include <asm/arch/pm.h>
+
-+ sysreg_write(PCCR, sysreg_read(PCCR) | SYSREG_BIT(PCCR_E));
++#include "pm.h"
++#include "sdramc.h"
+
-+ return 0;
-+}
++/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
++#define PM_BASE -0x100000
+
-+static void avr32_perf_counter_stop(void)
-+{
-+ pr_debug("avr32_perf_counter_stop\n");
++ .section .bss, "wa", @nobits
++ .global disable_idle_sleep
++ .type disable_idle_sleep, @object
++disable_idle_sleep:
++ .int 4
++ .size disable_idle_sleep, . - disable_idle_sleep
+
-+ sysreg_write(PCCR, sysreg_read(PCCR) & ~SYSREG_BIT(PCCR_E));
-+}
++ /* Keep this close to the irq handlers */
++ .section .irq.text, "ax", @progbits
+
-+static struct oprofile_operations avr32_perf_counter_ops __initdata = {
-+ .create_files = avr32_perf_counter_create_files,
-+ .setup = avr32_perf_counter_setup,
-+ .shutdown = avr32_perf_counter_shutdown,
-+ .start = avr32_perf_counter_start,
-+ .stop = avr32_perf_counter_stop,
-+ .cpu_type = "avr32",
-+};
++ /*
++ * void cpu_enter_idle(void)
++ *
++ * Put the CPU into "idle" mode, in which it will consume
++ * significantly less power.
++ *
++ * If an interrupt comes along in the window between
++ * unmask_interrupts and the sleep instruction below, the
++ * interrupt code will adjust the return address so that we
++ * never execute the sleep instruction. This is required
++ * because the AP7000 doesn't unmask interrupts when entering
++ * sleep modes; later CPUs may not need this workaround.
++ */
++ .global cpu_enter_idle
++ .type cpu_enter_idle, @function
++cpu_enter_idle:
++ mask_interrupts
++ get_thread_info r8
++ ld.w r9, r8[TI_flags]
++ bld r9, TIF_NEED_RESCHED
++ brcs .Lret_from_sleep
++ sbr r9, TIF_CPU_GOING_TO_SLEEP
++ st.w r8[TI_flags], r9
++ unmask_interrupts
++ sleep CPU_SLEEP_IDLE
++ .size cpu_idle_sleep, . - cpu_idle_sleep
+
-+int __init oprofile_arch_init(struct oprofile_operations *ops)
-+{
-+ if (!(current_cpu_data.features & AVR32_FEATURE_PCTR))
-+ return -ENODEV;
++ /*
++ * Common return path for PM functions that don't run from
++ * SRAM.
++ */
++ .global cpu_idle_skip_sleep
++ .type cpu_idle_skip_sleep, @function
++cpu_idle_skip_sleep:
++ mask_interrupts
++ ld.w r9, r8[TI_flags]
++ cbr r9, TIF_CPU_GOING_TO_SLEEP
++ st.w r8[TI_flags], r9
++.Lret_from_sleep:
++ unmask_interrupts
++ retal r12
++ .size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
+
-+ memcpy(ops, &avr32_perf_counter_ops,
-+ sizeof(struct oprofile_operations));
++#ifdef CONFIG_PM
++ .section .init.text, "ax", @progbits
+
-+ printk(KERN_INFO "oprofile: using AVR32 performance monitoring.\n");
++ .global pm_exception
++ .type pm_exception, @function
++pm_exception:
++ /*
++ * Exceptions are masked when we switch to this handler, so
++ * we'll only get "unrecoverable" exceptions (offset 0.)
++ */
++ sub r12, pc, . - .Lpanic_msg
++ lddpc pc, .Lpanic_addr
++
++ .align 2
++.Lpanic_addr:
++ .long panic
++.Lpanic_msg:
++ .asciz "Unrecoverable exception during suspend\n"
++ .size pm_exception, . - pm_exception
++
++ .global pm_irq0
++ .type pm_irq0, @function
++pm_irq0:
++ /* Disable interrupts and return after the sleep instruction */
++ mfsr r9, SYSREG_RSR_INT0
++ mtsr SYSREG_RAR_INT0, r8
++ sbr r9, SYSREG_GM_OFFSET
++ mtsr SYSREG_RSR_INT0, r9
++ rete
+
-+ return 0;
-+}
++ /*
++ * void cpu_enter_standby(unsigned long sdramc_base)
++ *
++ * Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
++ * are suspended and interrupts are disabled. Interrupts
++ * marked as 'wakeup' event sources may still come along and
++ * get us out of here.
++ *
++ * The SDRAM will be put into self-refresh mode (which does
++ * not require a clock from the CPU), and the CPU will be put
++ * into "frozen" mode (HSB bus stopped). The SDRAM controller
++ * will automatically bring the SDRAM into normal mode on the
++ * first access, and the power manager will automatically
++ * start the HSB and CPU clocks upon a wakeup event.
++ *
++ * This code uses the same "skip sleep" technique as above.
++ * It is very important that we jump directly to
++ * cpu_after_sleep after the sleep instruction since that's
++ * where we'll end up if the interrupt handler decides that we
++ * need to skip the sleep instruction.
++ */
++ .global pm_standby
++ .type pm_standby, @function
++pm_standby:
++ /*
++ * interrupts are already masked at this point, and EVBA
++ * points to pm_exception above.
++ */
++ ld.w r10, r12[SDRAMC_LPR]
++ sub r8, pc, . - 1f /* return address for irq handler */
++ mov r11, SDRAMC_LPR_LPCB_SELF_RFR
++ bfins r10, r11, 0, 2 /* LPCB <- self Refresh */
++ sync 0 /* flush write buffer */
++ st.w r12[SDRAMC_LPR], r11 /* put SDRAM in self-refresh mode */
++ ld.w r11, r12[SDRAMC_LPR]
++ unmask_interrupts
++ sleep CPU_SLEEP_FROZEN
++1: mask_interrupts
++ retal r12
++ .size pm_standby, . - pm_standby
+
-+void oprofile_arch_exit(void)
-+{
++ .global pm_suspend_to_ram
++ .type pm_suspend_to_ram, @function
++pm_suspend_to_ram:
++ /*
++ * interrupts are already masked at this point, and EVBA
++ * points to pm_exception above.
++ */
++ mov r11, 0
++ cache r11[2], 8 /* clean all dcache lines */
++ sync 0 /* flush write buffer */
++ ld.w r10, r12[SDRAMC_LPR]
++ sub r8, pc, . - 1f /* return address for irq handler */
++ mov r11, SDRAMC_LPR_LPCB_SELF_RFR
++ bfins r10, r11, 0, 2 /* LPCB <- self refresh */
++ st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
++ ld.w r11, r12[SDRAMC_LPR]
+
-+}
---- a/Documentation/kernel-parameters.txt
-+++ b/Documentation/kernel-parameters.txt
-@@ -34,6 +34,7 @@
- ALSA ALSA sound support is enabled.
- APIC APIC support is enabled.
- APM Advanced Power Management support is enabled.
-+ AVR32 AVR32 architecture is enabled.
- AX25 Appropriate AX.25 support is enabled.
- BLACKFIN Blackfin architecture is enabled.
- DRM Direct Rendering Management support is enabled.
-@@ -1124,6 +1125,10 @@
- of returning the full 64-bit number.
- The default is to return 64-bit inode numbers.
-
-+ nmi_debug= [KNL,AVR32] Specify one or more actions to take
-+ when a NMI is triggered.
-+ Format: [state][,regs][,debounce][,die]
-+
- nmi_watchdog= [KNL,BUGS=X86-32] Debugging features for SMP kernels
-
- no387 [BUGS=X86-32] Tells the kernel to use the 387 maths
---- a/drivers/clocksource/Makefile
-+++ b/drivers/clocksource/Makefile
-@@ -1,3 +1,4 @@
-+obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
- obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
- obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
- obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
---- /dev/null
-+++ b/drivers/clocksource/tcb_clksrc.c
-@@ -0,0 +1,305 @@
-+#include <linux/init.h>
-+#include <linux/clocksource.h>
-+#include <linux/clockchips.h>
-+#include <linux/interrupt.h>
-+#include <linux/irq.h>
++ unmask_interrupts
++ sleep CPU_SLEEP_STOP
++1: mask_interrupts
+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/ioport.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+#include <linux/atmel_tc.h>
++ retal r12
++ .size pm_suspend_to_ram, . - pm_suspend_to_ram
+
++ .global pm_sram_end
++ .type pm_sram_end, @function
++pm_sram_end:
++ .size pm_sram_end, 0
+
++#endif /* CONFIG_PM */
+--- /dev/null
++++ b/arch/avr32/mach-at32ap/pm.c
+@@ -0,0 +1,245 @@
+/*
-+ * We're configured to use a specific TC block, one that's not hooked
-+ * up to external hardware, to provide a time solution:
-+ *
-+ * - Two channels combine to create a free-running 32 bit counter
-+ * with a base rate of 5+ MHz, packaged as a clocksource (with
-+ * resolution better than 200 nsec).
-+ *
-+ * - The third channel may be used to provide a 16-bit clockevent
-+ * source, used in either periodic or oneshot mode. This runs
-+ * at 32 KiHZ, and can handle delays of up to two seconds.
++ * AVR32 AP Power Management
+ *
-+ * A boot clocksource and clockevent source are also currently needed,
-+ * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
-+ * this code can be used when init_timers() is called, well before most
-+ * devices are set up. (Some low end AT91 parts, which can run uClinux,
-+ * have only the timers in one TC block... they currently don't support
-+ * the tclib code, because of that initialization issue.)
++ * Copyright (C) 2008 Atmel Corporation
+ *
-+ * REVISIT behavior during system suspend states... we should disable
-+ * all clocks and save the power. Easily done for clockevent devices,
-+ * but clocksources won't necessarily get the needed notifications.
-+ * For deeper system sleep states, this will be mandatory...
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
+ */
++#include <linux/io.h>
++#include <linux/suspend.h>
++#include <linux/vmalloc.h>
+
-+static void __iomem *tcaddr;
++#include <asm/cacheflush.h>
++#include <asm/sysreg.h>
+
-+static cycle_t tc_get_cycles(void)
-+{
-+ unsigned long flags;
-+ u32 lower, upper;
++#include <asm/arch/pm.h>
++#include <asm/arch/sram.h>
+
-+ raw_local_irq_save(flags);
-+ do {
-+ upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
-+ lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
-+ } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
++/* FIXME: This is only valid for AP7000 */
++#define SDRAMC_BASE 0xfff03800
+
-+ raw_local_irq_restore(flags);
-+ return (upper << 16) | lower;
-+}
++#include "sdramc.h"
+
-+static struct clocksource clksrc = {
-+ .name = "tcb_clksrc",
-+ .rating = 200,
-+ .read = tc_get_cycles,
-+ .mask = CLOCKSOURCE_MASK(32),
-+ .shift = 18,
-+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-+};
++#define SRAM_PAGE_FLAGS (SYSREG_BIT(TLBELO_D) | SYSREG_BF(SZ, 1) \
++ | SYSREG_BF(AP, 3) | SYSREG_BIT(G))
+
-+#ifdef CONFIG_GENERIC_CLOCKEVENTS
+
-+struct tc_clkevt_device {
-+ struct clock_event_device clkevt;
-+ struct clk *clk;
-+ void __iomem *regs;
-+};
++static unsigned long pm_sram_start;
++static size_t pm_sram_size;
++static struct vm_struct *pm_sram_area;
+
-+static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
-+{
-+ return container_of(clkevt, struct tc_clkevt_device, clkevt);
-+}
++static void (*avr32_pm_enter_standby)(unsigned long sdramc_base);
++static void (*avr32_pm_enter_str)(unsigned long sdramc_base);
+
-+/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
-+ * because using one of the divided clocks would usually mean the
-+ * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
-+ *
-+ * A divided clock could be good for high resolution timers, since
-+ * 30.5 usec resolution can seem "low".
++/*
++ * Must be called with interrupts disabled. Exceptions will be masked
++ * on return (i.e. all exceptions will be "unrecoverable".)
+ */
-+static u32 timer_clock;
-+
-+static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
++static void *avr32_pm_map_sram(void)
+{
-+ struct tc_clkevt_device *tcd = to_tc_clkevt(d);
-+ void __iomem *regs = tcd->regs;
++ unsigned long vaddr;
++ unsigned long page_addr;
++ u32 tlbehi;
++ u32 mmucr;
+
-+ if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
-+ || tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
-+ __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
-+ __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
-+ clk_disable(tcd->clk);
-+ }
-+
-+ switch (m) {
++ vaddr = (unsigned long)pm_sram_area->addr;
++ page_addr = pm_sram_start & PAGE_MASK;
+
-+ /* By not making the gentime core emulate periodic mode on top
-+ * of oneshot, we get lower overhead and improved accuracy.
++ /*
++ * Mask exceptions and grab the first TLB entry. We won't be
++ * needing it while sleeping.
+ */
-+ case CLOCK_EVT_MODE_PERIODIC:
-+ clk_enable(tcd->clk);
-+
-+ /* slow clock, count up to RC, then irq and restart */
-+ __raw_writel(timer_clock
-+ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
-+ regs + ATMEL_TC_REG(2, CMR));
-+ __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
-+
-+ /* Enable clock and interrupts on RC compare */
-+ __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
-+
-+ /* go go gadget! */
-+ __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
-+ regs + ATMEL_TC_REG(2, CCR));
-+ break;
-+
-+ case CLOCK_EVT_MODE_ONESHOT:
-+ clk_enable(tcd->clk);
-+
-+ /* slow clock, count up to RC, then irq and stop */
-+ __raw_writel(timer_clock | ATMEL_TC_CPCSTOP
-+ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
-+ regs + ATMEL_TC_REG(2, CMR));
-+ __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
++ asm volatile("ssrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
+
-+ /* set_next_event() configures and starts the timer */
-+ break;
++ mmucr = sysreg_read(MMUCR);
++ tlbehi = sysreg_read(TLBEHI);
++ sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
+
-+ default:
-+ break;
-+ }
-+}
++ tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
++ tlbehi |= vaddr & PAGE_MASK;
++ tlbehi |= SYSREG_BIT(TLBEHI_V);
+
-+static int tc_next_event(unsigned long delta, struct clock_event_device *d)
-+{
-+ __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
++ sysreg_write(TLBELO, page_addr | SRAM_PAGE_FLAGS);
++ sysreg_write(TLBEHI, tlbehi);
++ __builtin_tlbw();
+
-+ /* go go gadget! */
-+ __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
-+ tcaddr + ATMEL_TC_REG(2, CCR));
-+ return 0;
++ return (void *)(vaddr + pm_sram_start - page_addr);
+}
+
-+static struct tc_clkevt_device clkevt = {
-+ .clkevt = {
-+ .name = "tc_clkevt",
-+ .features = CLOCK_EVT_FEAT_PERIODIC
-+ | CLOCK_EVT_FEAT_ONESHOT,
-+ .shift = 32,
-+ /* Should be lower than at91rm9200's system timer */
-+ .rating = 125,
-+ .cpumask = CPU_MASK_CPU0,
-+ .set_next_event = tc_next_event,
-+ .set_mode = tc_mode,
-+ },
-+};
-+
-+static irqreturn_t ch2_irq(int irq, void *handle)
++/*
++ * Must be called with interrupts disabled. Exceptions will be
++ * unmasked on return.
++ */
++static void avr32_pm_unmap_sram(void)
+{
-+ struct tc_clkevt_device *dev = handle;
-+ unsigned int sr;
++ u32 mmucr;
++ u32 tlbehi;
++ u32 tlbarlo;
+
-+ sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
-+ if (sr & ATMEL_TC_CPCS) {
-+ dev->clkevt.event_handler(&dev->clkevt);
-+ return IRQ_HANDLED;
-+ }
++ /* Going to update TLB entry at index 0 */
++ mmucr = sysreg_read(MMUCR);
++ tlbehi = sysreg_read(TLBEHI);
++ sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
+
-+ return IRQ_NONE;
++ /* Clear the "valid" bit */
++ tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
++ sysreg_write(TLBEHI, tlbehi);
++
++ /* Mark it as "not accessed" */
++ tlbarlo = sysreg_read(TLBARLO);
++ sysreg_write(TLBARLO, tlbarlo | 0x80000000U);
++
++ /* Update the TLB */
++ __builtin_tlbw();
++
++ /* Unmask exceptions */
++ asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
+}
+
-+static struct irqaction tc_irqaction = {
-+ .name = "tc_clkevt",
-+ .flags = IRQF_TIMER | IRQF_DISABLED,
-+ .handler = ch2_irq,
-+};
++static int avr32_pm_valid_state(suspend_state_t state)
++{
++ switch (state) {
++ case PM_SUSPEND_ON:
++ case PM_SUSPEND_STANDBY:
++ case PM_SUSPEND_MEM:
++ return 1;
++
++ default:
++ return 0;
++ }
++}
+
-+static void __init setup_clkevents(struct atmel_tc *tc,
-+ struct clk *t0_clk, int clk32k_divisor_idx)
++static int avr32_pm_enter(suspend_state_t state)
+{
-+ struct platform_device *pdev = tc->pdev;
-+ struct clk *t2_clk = tc->clk[2];
-+ int irq = tc->irq[2];
++ u32 lpr_saved;
++ u32 evba_saved;
++ void *sram;
+
-+ clkevt.regs = tc->regs;
-+ clkevt.clk = t2_clk;
-+ tc_irqaction.dev_id = &clkevt;
++ switch (state) {
++ case PM_SUSPEND_STANDBY:
++ sram = avr32_pm_map_sram();
+
-+ timer_clock = clk32k_divisor_idx;
++ /* Switch to in-sram exception handlers */
++ evba_saved = sysreg_read(EVBA);
++ sysreg_write(EVBA, (unsigned long)sram);
+
-+ clkevt.clkevt.mult = div_sc(32768, NSEC_PER_SEC, clkevt.clkevt.shift);
-+ clkevt.clkevt.max_delta_ns
-+ = clockevent_delta2ns(0xffff, &clkevt.clkevt);
-+ clkevt.clkevt.min_delta_ns = clockevent_delta2ns(1, &clkevt.clkevt) + 1;
++ /*
++ * Save the LPR register so that we can re-enable
++ * SDRAM Low Power mode on resume.
++ */
++ lpr_saved = sdramc_readl(LPR);
++ pr_debug("%s: Entering standby...\n", __func__);
++ avr32_pm_enter_standby(SDRAMC_BASE);
++ sdramc_writel(LPR, lpr_saved);
+
-+ setup_irq(irq, &tc_irqaction);
++ /* Switch back to regular exception handlers */
++ sysreg_write(EVBA, evba_saved);
+
-+ clockevents_register_device(&clkevt.clkevt);
-+}
++ avr32_pm_unmap_sram();
++ break;
+
-+#else /* !CONFIG_GENERIC_CLOCKEVENTS */
++ case PM_SUSPEND_MEM:
++ sram = avr32_pm_map_sram();
+
-+static void __init setup_clkevents(struct atmel_tc *tc,
-+ struct clk *t0_clk, int clk32k_divisor_idx)
-+{
-+ /* NOTHING */
-+}
++ /* Switch to in-sram exception handlers */
++ evba_saved = sysreg_read(EVBA);
++ sysreg_write(EVBA, (unsigned long)sram);
+
-+#endif
++ /*
++ * Save the LPR register so that we can re-enable
++ * SDRAM Low Power mode on resume.
++ */
++ lpr_saved = sdramc_readl(LPR);
++ pr_debug("%s: Entering suspend-to-ram...\n", __func__);
++ avr32_pm_enter_str(SDRAMC_BASE);
++ sdramc_writel(LPR, lpr_saved);
+
-+static int __init tcb_clksrc_init(void)
-+{
-+ static char bootinfo[] __initdata
-+ = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
++ /* Switch back to regular exception handlers */
++ sysreg_write(EVBA, evba_saved);
+
-+ struct platform_device *pdev;
-+ struct atmel_tc *tc;
-+ struct clk *t0_clk, *t1_clk;
-+ u32 rate, divided_rate = 0;
-+ int best_divisor_idx = -1;
-+ int clk32k_divisor_idx = -1;
-+ int i;
++ avr32_pm_unmap_sram();
++ break;
+
-+ tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
-+ if (!tc) {
-+ pr_debug("can't alloc TC for clocksource\n");
-+ return -ENODEV;
++ case PM_SUSPEND_ON:
++ pr_debug("%s: Entering idle...\n", __func__);
++ cpu_enter_idle();
++ break;
++
++ default:
++ pr_debug("%s: Invalid suspend state %d\n", __func__, state);
++ goto out;
+ }
-+ tcaddr = tc->regs;
-+ pdev = tc->pdev;
+
-+ t0_clk = tc->clk[0];
-+ clk_enable(t0_clk);
++ pr_debug("%s: wakeup\n", __func__);
+
-+ /* How fast will we be counting? Pick something over 5 MHz. */
-+ rate = (u32) clk_get_rate(t0_clk);
-+ for (i = 0; i < 5; i++) {
-+ unsigned divisor = atmel_tc_divisors[i];
-+ unsigned tmp;
++out:
++ return 0;
++}
+
-+ /* remember 32 KiHz clock for later */
-+ if (!divisor) {
-+ clk32k_divisor_idx = i;
-+ continue;
-+ }
++static struct platform_suspend_ops avr32_pm_ops = {
++ .valid = avr32_pm_valid_state,
++ .enter = avr32_pm_enter,
++};
+
-+ tmp = rate / divisor;
-+ pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
-+ if (best_divisor_idx > 0) {
-+ if (tmp < 5 * 1000 * 1000)
-+ continue;
-+ }
-+ divided_rate = tmp;
-+ best_divisor_idx = i;
-+ }
++static unsigned long avr32_pm_offset(void *symbol)
++{
++ extern u8 pm_exception[];
+
-+ clksrc.mult = clocksource_hz2mult(divided_rate, clksrc.shift);
++ return (unsigned long)symbol - (unsigned long)pm_exception;
++}
+
-+ printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
-+ divided_rate / 1000000,
-+ ((divided_rate + 500000) % 1000000) / 1000);
++static int __init avr32_pm_init(void)
++{
++ extern u8 pm_exception[];
++ extern u8 pm_irq0[];
++ extern u8 pm_standby[];
++ extern u8 pm_suspend_to_ram[];
++ extern u8 pm_sram_end[];
++ void *dst;
+
-+ /* tclib will give us three clocks no matter what the
-+ * underlying platform supports.
++ /*
++ * To keep things simple, we depend on not needing more than a
++ * single page.
+ */
-+ clk_enable(tc->clk[1]);
++ pm_sram_size = avr32_pm_offset(pm_sram_end);
++ if (pm_sram_size > PAGE_SIZE)
++ goto err;
+
-+ /* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
-+ __raw_writel(best_divisor_idx /* likely divide-by-8 */
-+ | ATMEL_TC_WAVE
-+ | ATMEL_TC_WAVESEL_UP /* free-run */
-+ | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
-+ | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
-+ tcaddr + ATMEL_TC_REG(0, CMR));
-+ __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
-+ __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
-+ __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
-+ __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
++ pm_sram_start = sram_alloc(pm_sram_size);
++ if (!pm_sram_start)
++ goto err_alloc_sram;
+
-+ /* channel 1: waveform mode, input TIOA0 */
-+ __raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
-+ | ATMEL_TC_WAVE
-+ | ATMEL_TC_WAVESEL_UP, /* free-run */
-+ tcaddr + ATMEL_TC_REG(1, CMR));
-+ __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
-+ __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
++ /* Grab a virtual area we can use later on. */
++ pm_sram_area = get_vm_area(pm_sram_size, VM_IOREMAP);
++ if (!pm_sram_area)
++ goto err_vm_area;
++ pm_sram_area->phys_addr = pm_sram_start;
+
-+ /* chain channel 0 to channel 1, then reset all the timers */
-+ __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
-+ __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
++ local_irq_disable();
++ dst = avr32_pm_map_sram();
++ memcpy(dst, pm_exception, pm_sram_size);
++ flush_dcache_region(dst, pm_sram_size);
++ invalidate_icache_region(dst, pm_sram_size);
++ avr32_pm_unmap_sram();
++ local_irq_enable();
+
-+ /* and away we go! */
-+ clocksource_register(&clksrc);
++ avr32_pm_enter_standby = dst + avr32_pm_offset(pm_standby);
++ avr32_pm_enter_str = dst + avr32_pm_offset(pm_suspend_to_ram);
++ intc_set_suspend_handler(avr32_pm_offset(pm_irq0));
+
-+ /* channel 2: periodic and oneshot timer support */
-+ setup_clkevents(tc, t0_clk, clk32k_divisor_idx);
++ suspend_set_ops(&avr32_pm_ops);
++
++ printk("AVR32 AP Power Management enabled\n");
+
+ return 0;
++
++err_vm_area:
++ sram_free(pm_sram_start, pm_sram_size);
++err_alloc_sram:
++err:
++ pr_err("AVR32 Power Management initialization failed\n");
++ return -ENOMEM;
+}
-+arch_initcall(tcb_clksrc_init);
++arch_initcall(avr32_pm_init);
--- /dev/null
-+++ b/drivers/i2c/busses/i2c-atmeltwi.c
-@@ -0,0 +1,436 @@
++++ b/arch/avr32/mach-at32ap/sdramc.h
+@@ -0,0 +1,76 @@
+/*
-+ * i2c Support for Atmel's Two-Wire Interface (TWI)
-+ *
-+ * Based on the work of Copyright (C) 2004 Rick Bronson
-+ * Converted to 2.6 by Andrew Victor <andrew at sanpeople.com>
-+ * Ported to AVR32 and heavily modified by Espen Krangnes
-+ * <ekrangnes at atmel.com>
-+ *
-+ * Copyright (C) 2006 Atmel Corporation
-+ *
-+ * Borrowed heavily from the original work by:
-+ * Copyright (C) 2000 Philip Edelbrock <phil at stimpy.netroedge.com>
++ * Register definitions for the AT32AP SDRAM Controller
+ *
-+ * Partialy rewriten by Karel Hojdar <cmkaho at seznam.cz>
-+ * bugs removed, interrupt routine markedly rewritten
++ * Copyright (C) 2008 Atmel Corporation
+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
+ */
-+#undef VERBOSE_DEBUG
+
++/* Register offsets */
++#define SDRAMC_MR 0x0000
++#define SDRAMC_TR 0x0004
++#define SDRAMC_CR 0x0008
++#define SDRAMC_HSR 0x000c
++#define SDRAMC_LPR 0x0010
++#define SDRAMC_IER 0x0014
++#define SDRAMC_IDR 0x0018
++#define SDRAMC_IMR 0x001c
++#define SDRAMC_ISR 0x0020
++#define SDRAMC_MDR 0x0024
++
++/* MR - Mode Register */
++#define SDRAMC_MR_MODE_NORMAL ( 0 << 0)
++#define SDRAMC_MR_MODE_NOP ( 1 << 0)
++#define SDRAMC_MR_MODE_BANKS_PRECHARGE ( 2 << 0)
++#define SDRAMC_MR_MODE_LOAD_MODE ( 3 << 0)
++#define SDRAMC_MR_MODE_AUTO_REFRESH ( 4 << 0)
++#define SDRAMC_MR_MODE_EXT_LOAD_MODE ( 5 << 0)
++#define SDRAMC_MR_MODE_POWER_DOWN ( 6 << 0)
++
++/* CR - Configuration Register */
++#define SDRAMC_CR_NC_8_BITS ( 0 << 0)
++#define SDRAMC_CR_NC_9_BITS ( 1 << 0)
++#define SDRAMC_CR_NC_10_BITS ( 2 << 0)
++#define SDRAMC_CR_NC_11_BITS ( 3 << 0)
++#define SDRAMC_CR_NR_11_BITS ( 0 << 2)
++#define SDRAMC_CR_NR_12_BITS ( 1 << 2)
++#define SDRAMC_CR_NR_13_BITS ( 2 << 2)
++#define SDRAMC_CR_NB_2_BANKS ( 0 << 4)
++#define SDRAMC_CR_NB_4_BANKS ( 1 << 4)
++#define SDRAMC_CR_CAS(x) ((x) << 5)
++#define SDRAMC_CR_DBW_32_BITS ( 0 << 7)
++#define SDRAMC_CR_DBW_16_BITS ( 1 << 7)
++#define SDRAMC_CR_TWR(x) ((x) << 8)
++#define SDRAMC_CR_TRC(x) ((x) << 12)
++#define SDRAMC_CR_TRP(x) ((x) << 16)
++#define SDRAMC_CR_TRCD(x) ((x) << 20)
++#define SDRAMC_CR_TRAS(x) ((x) << 24)
++#define SDRAMC_CR_TXSR(x) ((x) << 28)
++
++/* HSR - High Speed Register */
++#define SDRAMC_HSR_DA ( 1 << 0)
++
++/* LPR - Low Power Register */
++#define SDRAMC_LPR_LPCB_INHIBIT ( 0 << 0)
++#define SDRAMC_LPR_LPCB_SELF_RFR ( 1 << 0)
++#define SDRAMC_LPR_LPCB_PDOWN ( 2 << 0)
++#define SDRAMC_LPR_LPCB_DEEP_PDOWN ( 3 << 0)
++#define SDRAMC_LPR_PASR(x) ((x) << 4)
++#define SDRAMC_LPR_TCSR(x) ((x) << 8)
++#define SDRAMC_LPR_DS(x) ((x) << 10)
++#define SDRAMC_LPR_TIMEOUT(x) ((x) << 12)
++
++/* IER/IDR/IMR/ISR - Interrupt Enable/Disable/Mask/Status Register */
++#define SDRAMC_ISR_RES ( 1 << 0)
++
++/* MDR - Memory Device Register */
++#define SDRAMC_MDR_MD_SDRAM ( 0 << 0)
++#define SDRAMC_MDR_MD_LOW_PWR_SDRAM ( 1 << 0)
++
++/* Register access macros */
++#define sdramc_readl(reg) \
++ __raw_readl((void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
++#define sdramc_writel(reg, value) \
++ __raw_writel(value, (void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
+--- a/arch/avr32/mach-at32ap/time-tc.c
++++ /dev/null
+@@ -1,218 +0,0 @@
+-/*
+- * Copyright (C) 2004-2007 Atmel Corporation
+- *
+- * Based on MIPS implementation arch/mips/kernel/time.c
+- * Copyright 2001 MontaVista Software Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- */
+-
+-#include <linux/clk.h>
+-#include <linux/clocksource.h>
+-#include <linux/time.h>
+-#include <linux/module.h>
+-#include <linux/interrupt.h>
+-#include <linux/irq.h>
+-#include <linux/kernel_stat.h>
+-#include <linux/errno.h>
+-#include <linux/init.h>
+-#include <linux/profile.h>
+-#include <linux/sysdev.h>
+-#include <linux/err.h>
+-
+-#include <asm/div64.h>
+-#include <asm/sysreg.h>
+-#include <asm/io.h>
+-#include <asm/sections.h>
+-
+-#include <asm/arch/time.h>
+-
+-/* how many counter cycles in a jiffy? */
+-static u32 cycles_per_jiffy;
+-
+-/* the count value for the next timer interrupt */
+-static u32 expirelo;
+-
+-/* the I/O registers of the TC module */
+-static void __iomem *ioregs;
+-
+-cycle_t read_cycle_count(void)
+-{
+- return (cycle_t)timer_read(ioregs, 0, CV);
+-}
+-
+-struct clocksource clocksource_avr32 = {
+- .name = "avr32",
+- .rating = 342,
+- .read = read_cycle_count,
+- .mask = CLOCKSOURCE_MASK(16),
+- .shift = 16,
+- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+-};
+-
+-static void avr32_timer_ack(void)
+-{
+- u16 count = expirelo;
+-
+- /* Ack this timer interrupt and set the next one, use a u16
+- * variable so it will wrap around correctly */
+- count += cycles_per_jiffy;
+- expirelo = count;
+- timer_write(ioregs, 0, RC, expirelo);
+-
+- /* Check to see if we have missed any timer interrupts */
+- count = timer_read(ioregs, 0, CV);
+- if ((count - expirelo) < 0x7fff) {
+- expirelo = count + cycles_per_jiffy;
+- timer_write(ioregs, 0, RC, expirelo);
+- }
+-}
+-
+-u32 avr32_hpt_read(void)
+-{
+- return timer_read(ioregs, 0, CV);
+-}
+-
+-static int avr32_timer_calc_div_and_set_jiffies(struct clk *pclk)
+-{
+- unsigned int cycles_max = (clocksource_avr32.mask + 1) / 2;
+- unsigned int divs[] = { 4, 8, 16, 32 };
+- int divs_size = ARRAY_SIZE(divs);
+- int i = 0;
+- unsigned long count_hz;
+- unsigned long shift;
+- unsigned long mult;
+- int clock_div = -1;
+- u64 tmp;
+-
+- shift = clocksource_avr32.shift;
+-
+- do {
+- count_hz = clk_get_rate(pclk) / divs[i];
+- mult = clocksource_hz2mult(count_hz, shift);
+- clocksource_avr32.mult = mult;
+-
+- tmp = TICK_NSEC;
+- tmp <<= shift;
+- tmp += mult / 2;
+- do_div(tmp, mult);
+-
+- cycles_per_jiffy = tmp;
+- } while (cycles_per_jiffy > cycles_max && ++i < divs_size);
+-
+- clock_div = i + 1;
+-
+- if (clock_div > divs_size) {
+- pr_debug("timer: could not calculate clock divider\n");
+- return -EFAULT;
+- }
+-
+- /* Set the clock divider */
+- timer_write(ioregs, 0, CMR, TIMER_BF(CMR_TCCLKS, clock_div));
+-
+- return 0;
+-}
+-
+-int avr32_hpt_init(unsigned int count)
+-{
+- struct resource *regs;
+- struct clk *pclk;
+- int irq = -1;
+- int ret = 0;
+-
+- ret = -ENXIO;
+-
+- irq = platform_get_irq(&at32_systc0_device, 0);
+- if (irq < 0) {
+- pr_debug("timer: could not get irq\n");
+- goto out_error;
+- }
+-
+- pclk = clk_get(&at32_systc0_device.dev, "pclk");
+- if (IS_ERR(pclk)) {
+- pr_debug("timer: could not get clk: %ld\n", PTR_ERR(pclk));
+- goto out_error;
+- }
+- clk_enable(pclk);
+-
+- regs = platform_get_resource(&at32_systc0_device, IORESOURCE_MEM, 0);
+- if (!regs) {
+- pr_debug("timer: could not get resource\n");
+- goto out_error_clk;
+- }
+-
+- ioregs = ioremap(regs->start, regs->end - regs->start + 1);
+- if (!ioregs) {
+- pr_debug("timer: could not get ioregs\n");
+- goto out_error_clk;
+- }
+-
+- ret = avr32_timer_calc_div_and_set_jiffies(pclk);
+- if (ret)
+- goto out_error_io;
+-
+- ret = setup_irq(irq, &timer_irqaction);
+- if (ret) {
+- pr_debug("timer: could not request irq %d: %d\n",
+- irq, ret);
+- goto out_error_io;
+- }
+-
+- expirelo = (timer_read(ioregs, 0, CV) / cycles_per_jiffy + 1)
+- * cycles_per_jiffy;
+-
+- /* Enable clock and interrupts on RC compare */
+- timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_CLKEN));
+- timer_write(ioregs, 0, IER, TIMER_BIT(IER_CPCS));
+- /* Set cycles to first interrupt */
+- timer_write(ioregs, 0, RC, expirelo);
+-
+- printk(KERN_INFO "timer: AT32AP system timer/counter at 0x%p irq %d\n",
+- ioregs, irq);
+-
+- return 0;
+-
+-out_error_io:
+- iounmap(ioregs);
+-out_error_clk:
+- clk_put(pclk);
+-out_error:
+- return ret;
+-}
+-
+-int avr32_hpt_start(void)
+-{
+- timer_write(ioregs, 0, CCR, TIMER_BIT(CCR_SWTRG));
+- return 0;
+-}
+-
+-irqreturn_t timer_interrupt(int irq, void *dev_id)
+-{
+- unsigned int sr = timer_read(ioregs, 0, SR);
+-
+- if (sr & TIMER_BIT(SR_CPCS)) {
+- /* ack timer interrupt and try to set next interrupt */
+- avr32_timer_ack();
+-
+- /*
+- * Call the generic timer interrupt handler
+- */
+- write_seqlock(&xtime_lock);
+- do_timer(1);
+- write_sequnlock(&xtime_lock);
+-
+- /*
+- * In UP mode, we call local_timer_interrupt() to do profiling
+- * and process accounting.
+- *
+- * SMP is not supported yet.
+- */
+- local_timer_interrupt(irq, dev_id);
+-
+- return IRQ_HANDLED;
+- }
+-
+- return IRQ_NONE;
+-}
+--- a/arch/avr32/mm/init.c
++++ b/arch/avr32/mm/init.c
+@@ -11,6 +11,7 @@
+ #include <linux/swap.h>
+ #include <linux/init.h>
+ #include <linux/mmzone.h>
+#include <linux/module.h>
-+#include <linux/slab.h>
-+#include <linux/i2c.h>
-+#include <linux/init.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/completion.h>
-+#include <linux/io.h>
-+
-+#include "i2c-atmeltwi.h"
-+
-+static unsigned int baudrate = 100 * 1000;
-+module_param(baudrate, uint, S_IRUGO);
-+MODULE_PARM_DESC(baudrate, "The TWI baudrate");
-+
-+
-+struct atmel_twi {
-+ void __iomem *regs;
-+ struct i2c_adapter adapter;
-+ struct clk *pclk;
-+ struct completion comp;
-+ u32 mask;
-+ u8 *buf;
-+ u16 len;
-+ u16 acks_left;
-+ int status;
-+ unsigned int irq;
-+
-+};
-+#define to_atmel_twi(adap) container_of(adap, struct atmel_twi, adapter)
-+
-+/*
-+ * (Re)Initialize the TWI hardware registers.
-+ */
-+static int twi_hwinit(struct atmel_twi *twi)
-+{
-+ unsigned long cdiv, ckdiv = 0;
+ #include <linux/bootmem.h>
+ #include <linux/pagemap.h>
+ #include <linux/nodemask.h>
+@@ -23,20 +24,20 @@
+ #include <asm/setup.h>
+ #include <asm/sections.h>
+
++#define __page_aligned __attribute__((section(".data.page_aligned")))
+
-+ /* REVISIT: wait till SCL is high before resetting; otherwise,
-+ * some versions will wedge forever.
+ DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
+
+-pgd_t swapper_pg_dir[PTRS_PER_PGD];
++pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned;
+
+ struct page *empty_zero_page;
++EXPORT_SYMBOL(empty_zero_page);
+
+ /*
+ * Cache of MMU context last used.
+ */
+ unsigned long mmu_context_cache = NO_CONTEXT;
+
+-#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
+-#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
+-
+ void show_mem(void)
+ {
+ int total = 0, reserved = 0, cached = 0;
+@@ -109,19 +110,9 @@
+ zero_page = alloc_bootmem_low_pages_node(NODE_DATA(0),
+ PAGE_SIZE);
+
+- {
+- pgd_t *pg_dir;
+- int i;
+-
+- pg_dir = swapper_pg_dir;
+- sysreg_write(PTBR, (unsigned long)pg_dir);
+-
+- for (i = 0; i < PTRS_PER_PGD; i++)
+- pgd_val(pg_dir[i]) = 0;
+-
+- enable_mmu();
+- printk ("CPU: Paging enabled\n");
+- }
++ sysreg_write(PTBR, (unsigned long)swapper_pg_dir);
++ enable_mmu();
++ printk ("CPU: Paging enabled\n");
+
+ for_each_online_node(nid) {
+ pg_data_t *pgdat = NODE_DATA(nid);
+--- a/arch/avr32/mm/tlb.c
++++ b/arch/avr32/mm/tlb.c
+@@ -11,21 +11,21 @@
+
+ #include <asm/mmu_context.h>
+
+-#define _TLBEHI_I 0x100
++/* TODO: Get the correct number from the CONFIG1 system register */
++#define NR_TLB_ENTRIES 32
+
+-void show_dtlb_entry(unsigned int index)
++static void show_dtlb_entry(unsigned int index)
+ {
+- unsigned int tlbehi, tlbehi_save, tlbelo, mmucr, mmucr_save;
++ u32 tlbehi, tlbehi_save, tlbelo, mmucr, mmucr_save;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ mmucr_save = sysreg_read(MMUCR);
+ tlbehi_save = sysreg_read(TLBEHI);
+- mmucr = mmucr_save & 0x13;
+- mmucr |= index << 14;
++ mmucr = SYSREG_BFINS(DRP, index, mmucr_save);
+ sysreg_write(MMUCR, mmucr);
+
+- asm volatile("tlbr" : : : "memory");
++ __builtin_tlbr();
+ cpu_sync_pipeline();
+
+ tlbehi = sysreg_read(TLBEHI);
+@@ -33,15 +33,17 @@
+
+ printk("%2u: %c %c %02x %05x %05x %o %o %c %c %c %c\n",
+ index,
+- (tlbehi & 0x200)?'1':'0',
+- (tlbelo & 0x100)?'1':'0',
+- (tlbehi & 0xff),
+- (tlbehi >> 12), (tlbelo >> 12),
+- (tlbelo >> 4) & 7, (tlbelo >> 2) & 3,
+- (tlbelo & 0x200)?'1':'0',
+- (tlbelo & 0x080)?'1':'0',
+- (tlbelo & 0x001)?'1':'0',
+- (tlbelo & 0x002)?'1':'0');
++ SYSREG_BFEXT(TLBEHI_V, tlbehi) ? '1' : '0',
++ SYSREG_BFEXT(G, tlbelo) ? '1' : '0',
++ SYSREG_BFEXT(ASID, tlbehi),
++ SYSREG_BFEXT(VPN, tlbehi) >> 2,
++ SYSREG_BFEXT(PFN, tlbelo) >> 2,
++ SYSREG_BFEXT(AP, tlbelo),
++ SYSREG_BFEXT(SZ, tlbelo),
++ SYSREG_BFEXT(TLBELO_C, tlbelo) ? 'C' : ' ',
++ SYSREG_BFEXT(B, tlbelo) ? 'B' : ' ',
++ SYSREG_BFEXT(W, tlbelo) ? 'W' : ' ',
++ SYSREG_BFEXT(TLBELO_D, tlbelo) ? 'D' : ' ');
+
+ sysreg_write(MMUCR, mmucr_save);
+ sysreg_write(TLBEHI, tlbehi_save);
+@@ -54,29 +56,33 @@
+ unsigned int i;
+
+ printk("ID V G ASID VPN PFN AP SZ C B W D\n");
+- for (i = 0; i < 32; i++)
++ for (i = 0; i < NR_TLB_ENTRIES; i++)
+ show_dtlb_entry(i);
+ }
+
+-static unsigned long last_mmucr;
+-
+-static inline void set_replacement_pointer(unsigned shift)
++static void update_dtlb(unsigned long address, pte_t pte)
+ {
+- unsigned long mmucr, mmucr_save;
++ u32 tlbehi;
++ u32 mmucr;
+
+- mmucr = mmucr_save = sysreg_read(MMUCR);
++ /*
++ * We're not changing the ASID here, so no need to flush the
++ * pipeline.
+ */
-+
-+ twi_writel(twi, IDR, ~0UL);
-+ twi_writel(twi, CR, TWI_BIT(SWRST)); /*Reset peripheral*/
-+ twi_readl(twi, SR);
-+
-+ cdiv = (clk_get_rate(twi->pclk) / (2 * baudrate)) - 4;
-+
-+ while (cdiv > 255) {
-+ ckdiv++;
-+ cdiv = cdiv >> 1;
-+ }
-+
-+ /* REVISIT: there are various errata to consider re CDIV and CHDIV
-+ * here, at least on at91 parts.
++ tlbehi = sysreg_read(TLBEHI);
++ tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
++ tlbehi |= address & MMU_VPN_MASK;
++ tlbehi |= SYSREG_BIT(TLBEHI_V);
++ sysreg_write(TLBEHI, tlbehi);
+
+ /* Does this mapping already exist? */
+- __asm__ __volatile__(
+- " tlbs\n"
+- " mfsr %0, %1"
+- : "=r"(mmucr)
+- : "i"(SYSREG_MMUCR));
++ __builtin_tlbs();
++ mmucr = sysreg_read(MMUCR);
+
+ if (mmucr & SYSREG_BIT(MMUCR_N)) {
+ /* Not found -- pick a not-recently-accessed entry */
+- unsigned long rp;
+- unsigned long tlbar = sysreg_read(TLBARLO);
++ unsigned int rp;
++ u32 tlbar = sysreg_read(TLBARLO);
+
+ rp = 32 - fls(tlbar);
+ if (rp == 32) {
+@@ -84,30 +90,14 @@
+ sysreg_write(TLBARLO, -1L);
+ }
+
+- mmucr &= 0x13;
+- mmucr |= (rp << shift);
+-
++ mmucr = SYSREG_BFINS(DRP, rp, mmucr);
+ sysreg_write(MMUCR, mmucr);
+ }
+
+- last_mmucr = mmucr;
+-}
+-
+-static void update_dtlb(unsigned long address, pte_t pte, unsigned long asid)
+-{
+- unsigned long vpn;
+-
+- vpn = (address & MMU_VPN_MASK) | _TLBEHI_VALID | asid;
+- sysreg_write(TLBEHI, vpn);
+- cpu_sync_pipeline();
+-
+- set_replacement_pointer(14);
+-
+ sysreg_write(TLBELO, pte_val(pte) & _PAGE_FLAGS_HARDWARE_MASK);
+
+ /* Let's go */
+- asm volatile("nop\n\ttlbw" : : : "memory");
+- cpu_sync_pipeline();
++ __builtin_tlbw();
+ }
+
+ void update_mmu_cache(struct vm_area_struct *vma,
+@@ -120,39 +110,40 @@
+ return;
+
+ local_irq_save(flags);
+- update_dtlb(address, pte, get_asid());
++ update_dtlb(address, pte);
+ local_irq_restore(flags);
+ }
+
+-void __flush_tlb_page(unsigned long asid, unsigned long page)
++static void __flush_tlb_page(unsigned long asid, unsigned long page)
+ {
+- unsigned long mmucr, tlbehi;
++ u32 mmucr, tlbehi;
+
+- page |= asid;
+- sysreg_write(TLBEHI, page);
+- cpu_sync_pipeline();
+- asm volatile("tlbs");
++ /*
++ * Caller is responsible for masking out non-PFN bits in page
++ * and changing the current ASID if necessary. This means that
++ * we don't need to flush the pipeline after writing TLBEHI.
+ */
++ tlbehi = page | asid;
++ sysreg_write(TLBEHI, tlbehi);
++
++ __builtin_tlbs();
+ mmucr = sysreg_read(MMUCR);
+
+ if (!(mmucr & SYSREG_BIT(MMUCR_N))) {
+- unsigned long tlbarlo;
+- unsigned long entry;
++ unsigned int entry;
++ u32 tlbarlo;
+
+ /* Clear the "valid" bit */
+- tlbehi = sysreg_read(TLBEHI);
+- tlbehi &= ~_TLBEHI_VALID;
+ sysreg_write(TLBEHI, tlbehi);
+- cpu_sync_pipeline();
+
+ /* mark the entry as "not accessed" */
+- entry = (mmucr >> 14) & 0x3f;
++ entry = SYSREG_BFEXT(DRP, mmucr);
+ tlbarlo = sysreg_read(TLBARLO);
+- tlbarlo |= (0x80000000 >> entry);
++ tlbarlo |= (0x80000000UL >> entry);
+ sysreg_write(TLBARLO, tlbarlo);
+
+ /* update the entry with valid bit clear */
+- asm volatile("tlbw");
+- cpu_sync_pipeline();
++ __builtin_tlbw();
+ }
+ }
+
+@@ -190,17 +181,22 @@
+
+ local_irq_save(flags);
+ size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+
-+ if (ckdiv > 7)
-+ return -EINVAL;
-+ else
-+ twi_writel(twi, CWGR, TWI_BF(CKDIV, ckdiv)
-+ | TWI_BF(CHDIV, cdiv)
-+ | TWI_BF(CLDIV, cdiv));
-+ return 0;
-+}
-+
-+/*
-+ * Waits for the i2c status register to set the specified bitmask
-+ * Returns 0 if timed out ... ~100ms is much longer than the SMBus
-+ * limit, but I2C has no limit at all.
-+ */
-+static int twi_complete(struct atmel_twi *twi, u32 mask)
-+{
-+ int timeout = msecs_to_jiffies(100);
-+
-+ mask |= TWI_BIT(TXCOMP);
-+ twi->mask = mask | TWI_BIT(NACK) | TWI_BIT(OVRE);
-+ init_completion(&twi->comp);
-+
-+ twi_writel(twi, IER, mask);
+ if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
+ mm->context = NO_CONTEXT;
+ if (mm == current->mm)
+ activate_context(mm);
+ } else {
+- unsigned long asid = mm->context & MMU_CONTEXT_ASID_MASK;
+- unsigned long saved_asid = MMU_NO_ASID;
++ unsigned long asid;
++ unsigned long saved_asid;
++
++ asid = mm->context & MMU_CONTEXT_ASID_MASK;
++ saved_asid = MMU_NO_ASID;
+
+ start &= PAGE_MASK;
+ end += (PAGE_SIZE - 1);
+ end &= PAGE_MASK;
++
+ if (mm != current->mm) {
+ saved_asid = get_asid();
+ set_asid(asid);
+@@ -218,33 +214,34 @@
+ }
+
+ /*
+- * TODO: If this is only called for addresses > TASK_SIZE, we can probably
+- * skip the ASID stuff and just use the Global bit...
++ * This function depends on the pages to be flushed having the G
++ * (global) bit set in their pte. This is true for all
++ * PAGE_KERNEL(_RO) pages.
+ */
+ void flush_tlb_kernel_range(unsigned long start, unsigned long end)
+ {
+ unsigned long flags;
+ int size;
+
+- local_irq_save(flags);
+ size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+ if (size > (MMU_DTLB_ENTRIES / 4)) { /* Too many entries to flush */
+ flush_tlb_all();
+ } else {
+- unsigned long asid = init_mm.context & MMU_CONTEXT_ASID_MASK;
+- unsigned long saved_asid = get_asid();
++ unsigned long asid;
+
-+ if (!wait_for_completion_timeout(&twi->comp, timeout)) {
-+ /* RESET TWI interface */
-+ twi_writel(twi, CR, TWI_BIT(SWRST));
++ local_irq_save(flags);
++ asid = get_asid();
+
+ start &= PAGE_MASK;
+ end += (PAGE_SIZE - 1);
+ end &= PAGE_MASK;
+- set_asid(asid);
+
-+ /* Reinitialize TWI */
-+ twi_hwinit(twi);
+ while (start < end) {
+ __flush_tlb_page(asid, start);
+ start += PAGE_SIZE;
+ }
+- set_asid(saved_asid);
++ local_irq_restore(flags);
+ }
+- local_irq_restore(flags);
+ }
+
+ void flush_tlb_mm(struct mm_struct *mm)
+@@ -280,7 +277,7 @@
+ {
+ static unsigned long tlb_index;
+
+- if (*pos >= 32)
++ if (*pos >= NR_TLB_ENTRIES)
+ return NULL;
+
+ tlb_index = 0;
+@@ -291,7 +288,7 @@
+ {
+ unsigned long *index = v;
+
+- if (*index >= 31)
++ if (*index >= NR_TLB_ENTRIES - 1)
+ return NULL;
+
+ ++*pos;
+@@ -313,16 +310,16 @@
+ if (*index == 0)
+ seq_puts(tlb, "ID V G ASID VPN PFN AP SZ C B W D\n");
+
+- BUG_ON(*index >= 32);
++ BUG_ON(*index >= NR_TLB_ENTRIES);
+
+ local_irq_save(flags);
+ mmucr_save = sysreg_read(MMUCR);
+ tlbehi_save = sysreg_read(TLBEHI);
+- mmucr = mmucr_save & 0x13;
+- mmucr |= *index << 14;
++ mmucr = SYSREG_BFINS(DRP, *index, mmucr_save);
+ sysreg_write(MMUCR, mmucr);
+
+- asm volatile("tlbr" : : : "memory");
++ /* TLBR might change the ASID */
++ __builtin_tlbr();
+ cpu_sync_pipeline();
+
+ tlbehi = sysreg_read(TLBEHI);
+@@ -334,16 +331,18 @@
+ local_irq_restore(flags);
+
+ seq_printf(tlb, "%2lu: %c %c %02x %05x %05x %o %o %c %c %c %c\n",
+- *index,
+- (tlbehi & 0x200)?'1':'0',
+- (tlbelo & 0x100)?'1':'0',
+- (tlbehi & 0xff),
+- (tlbehi >> 12), (tlbelo >> 12),
+- (tlbelo >> 4) & 7, (tlbelo >> 2) & 3,
+- (tlbelo & 0x200)?'1':'0',
+- (tlbelo & 0x080)?'1':'0',
+- (tlbelo & 0x001)?'1':'0',
+- (tlbelo & 0x002)?'1':'0');
++ *index,
++ SYSREG_BFEXT(TLBEHI_V, tlbehi) ? '1' : '0',
++ SYSREG_BFEXT(G, tlbelo) ? '1' : '0',
++ SYSREG_BFEXT(ASID, tlbehi),
++ SYSREG_BFEXT(VPN, tlbehi) >> 2,
++ SYSREG_BFEXT(PFN, tlbelo) >> 2,
++ SYSREG_BFEXT(AP, tlbelo),
++ SYSREG_BFEXT(SZ, tlbelo),
++ SYSREG_BFEXT(TLBELO_C, tlbelo) ? '1' : '0',
++ SYSREG_BFEXT(B, tlbelo) ? '1' : '0',
++ SYSREG_BFEXT(W, tlbelo) ? '1' : '0',
++ SYSREG_BFEXT(TLBELO_D, tlbelo) ? '1' : '0');
+
+ return 0;
+ }
+--- a/arch/avr32/oprofile/op_model_avr32.c
++++ b/arch/avr32/oprofile/op_model_avr32.c
+@@ -16,7 +16,6 @@
+ #include <linux/sched.h>
+ #include <linux/types.h>
+
+-#include <asm/intc.h>
+ #include <asm/sysreg.h>
+ #include <asm/system.h>
+
+--- a/drivers/char/Kconfig
++++ b/drivers/char/Kconfig
+@@ -706,7 +706,7 @@
+
+ config RTC
+ tristate "Enhanced Real Time Clock Support"
+- depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV && !ARM && !SUPERH && !S390
++ depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV && !ARM && !SUPERH && !S390 && !AVR32
+ ---help---
+ If you say Y here and create a character special file /dev/rtc with
+ major number 10 and minor number 135 using mknod ("man mknod"), you
+@@ -776,7 +776,7 @@
+
+ config GEN_RTC
+ tristate "Generic /dev/rtc emulation"
+- depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH
++ depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH && !AVR32
+ ---help---
+ If you say Y here and create a character special file /dev/rtc with
+ major number 10 and minor number 135 using mknod ("man mknod"), you
+--- a/drivers/char/keyboard.c
++++ b/drivers/char/keyboard.c
+@@ -1033,7 +1033,8 @@
+ #if defined(CONFIG_X86) || defined(CONFIG_IA64) || defined(CONFIG_ALPHA) ||\
+ defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_SPARC) ||\
+ defined(CONFIG_PARISC) || defined(CONFIG_SUPERH) ||\
+- (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC))
++ (defined(CONFIG_ARM) && defined(CONFIG_KEYBOARD_ATKBD) && !defined(CONFIG_ARCH_RPC)) ||\
++ defined(CONFIG_AVR32)
+
+ #define HW_RAW(dev) (test_bit(EV_MSC, dev->evbit) && test_bit(MSC_RAW, dev->mscbit) &&\
+ ((dev)->id.bustype == BUS_I8042) && ((dev)->id.vendor == 0x0001) && ((dev)->id.product == 0x0001))
+--- a/drivers/clocksource/Makefile
++++ b/drivers/clocksource/Makefile
+@@ -1,3 +1,4 @@
++obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
+ obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
+ obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
+ obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
+--- /dev/null
++++ b/drivers/clocksource/tcb_clksrc.c
+@@ -0,0 +1,302 @@
++#include <linux/init.h>
++#include <linux/clocksource.h>
++#include <linux/clockchips.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/ioport.h>
++#include <linux/io.h>
++#include <linux/platform_device.h>
++#include <linux/atmel_tc.h>
+
-+ return -ETIMEDOUT;
-+ }
-+ return 0;
-+}
+
+/*
-+ * Generic i2c master transfer entrypoint.
++ * We're configured to use a specific TC block, one that's not hooked
++ * up to external hardware, to provide a time solution:
++ *
++ * - Two channels combine to create a free-running 32 bit counter
++ * with a base rate of 5+ MHz, packaged as a clocksource (with
++ * resolution better than 200 nsec).
++ *
++ * - The third channel may be used to provide a 16-bit clockevent
++ * source, used in either periodic or oneshot mode. This runs
++ * at 32 KiHZ, and can handle delays of up to two seconds.
++ *
++ * A boot clocksource and clockevent source are also currently needed,
++ * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
++ * this code can be used when init_timers() is called, well before most
++ * devices are set up. (Some low end AT91 parts, which can run uClinux,
++ * have only the timers in one TC block... they currently don't support
++ * the tclib code, because of that initialization issue.)
++ *
++ * REVISIT behavior during system suspend states... we should disable
++ * all clocks and save the power. Easily done for clockevent devices,
++ * but clocksources won't necessarily get the needed notifications.
++ * For deeper system sleep states, this will be mandatory...
+ */
-+static int twi_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
-+{
-+ struct atmel_twi *twi = to_atmel_twi(adap);
-+ int i;
-+
-+ dev_dbg(&adap->dev, "twi_xfer: processing %d messages:\n", num);
-+
-+ twi->status = 0;
-+ for (i = 0; i < num; i++, pmsg++) {
-+ twi->len = pmsg->len;
-+ twi->buf = pmsg->buf;
-+ twi->acks_left = pmsg->len;
-+ twi_writel(twi, MMR, TWI_BF(DADR, pmsg->addr) |
-+ (pmsg->flags & I2C_M_RD ? TWI_BIT(MREAD) : 0));
-+ twi_writel(twi, IADR, TWI_BF(IADR, pmsg->addr));
-+
-+ dev_dbg(&adap->dev,
-+ "#%d: %s %d byte%s %s dev 0x%02x\n",
-+ i,
-+ pmsg->flags & I2C_M_RD ? "reading" : "writing",
-+ pmsg->len,
-+ pmsg->len > 1 ? "s" : "",
-+ pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr);
-+
-+ /* enable */
-+ twi_writel(twi, CR, TWI_BIT(MSEN));
-+
-+ if (pmsg->flags & I2C_M_RD) {
-+ /* cleanup after previous RX overruns */
-+ while (twi_readl(twi, SR) & TWI_BIT(RXRDY))
-+ twi_readl(twi, RHR);
-+
-+ if (twi->len == 1)
-+ twi_writel(twi, CR,
-+ TWI_BIT(START) | TWI_BIT(STOP));
-+ else
-+ twi_writel(twi, CR, TWI_BIT(START));
-+
-+ if (twi_complete(twi, TWI_BIT(RXRDY)) == -ETIMEDOUT) {
-+ dev_dbg(&adap->dev, "RX[%d] timeout. "
-+ "Stopped with %d bytes left\n",
-+ i, twi->acks_left);
-+ return -ETIMEDOUT;
-+ }
-+ } else {
-+ twi_writel(twi, THR, twi->buf[0]);
-+ twi->acks_left--;
-+ /* REVISIT: some chips don't start automagically:
-+ * twi_writel(twi, CR, TWI_BIT(START));
-+ */
-+ if (twi_complete(twi, TWI_BIT(TXRDY)) == -ETIMEDOUT) {
-+ dev_dbg(&adap->dev, "TX[%d] timeout. "
-+ "Stopped with %d bytes left\n",
-+ i, twi->acks_left);
-+ return -ETIMEDOUT;
-+ }
-+ /* REVISIT: an erratum workaround may be needed here;
-+ * see sam9261 "STOP not generated" (START either).
-+ */
-+ }
-+
-+ /* Disable TWI interface */
-+ twi_writel(twi, CR, TWI_BIT(MSDIS));
-+
-+ if (twi->status)
-+ return twi->status;
-+
-+ /* WARNING: This driver lies about properly supporting
-+ * repeated start, or it would *ALWAYS* return here. It
-+ * has issued a STOP. Continuing is a false claim -- that
-+ * a second (or third, etc.) message is part of the same
-+ * "combined" (no STOPs between parts) message.
-+ */
-+
-+ } /* end cur msg */
-+
-+ return i;
-+}
+
++static void __iomem *tcaddr;
+
-+static irqreturn_t twi_interrupt(int irq, void *dev_id)
++static cycle_t tc_get_cycles(void)
+{
-+ struct atmel_twi *twi = dev_id;
-+ int status = twi_readl(twi, SR);
-+
-+ /* Save state for later debug prints */
-+ int old_status = status;
-+
-+ if (twi->mask & status) {
-+
-+ status &= twi->mask;
-+
-+ if (status & TWI_BIT(RXRDY)) {
-+ if ((status & TWI_BIT(OVRE)) && twi->acks_left) {
-+ /* Note weakness in fault reporting model:
-+ * we can't say "the first N of these data
-+ * bytes are valid".
-+ */
-+ dev_err(&twi->adapter.dev,
-+ "OVERRUN RX! %04x, lost %d\n",
-+ old_status, twi->acks_left);
-+ twi->acks_left = 0;
-+ twi_writel(twi, CR, TWI_BIT(STOP));
-+ twi->status = -EOVERFLOW;
-+ } else if (twi->acks_left > 0) {
-+ twi->buf[twi->len - twi->acks_left] =
-+ twi_readl(twi, RHR);
-+ twi->acks_left--;
-+ }
-+ if (status & TWI_BIT(TXCOMP))
-+ goto done;
-+ if (twi->acks_left == 1)
-+ twi_writel(twi, CR, TWI_BIT(STOP));
-+
-+ } else if (status & (TWI_BIT(NACK) | TWI_BIT(TXCOMP))) {
-+ goto done;
-+
-+ } else if (status & TWI_BIT(TXRDY)) {
-+ if (twi->acks_left > 0) {
-+ twi_writel(twi, THR,
-+ twi->buf[twi->len - twi->acks_left]);
-+ twi->acks_left--;
-+ } else
-+ twi_writel(twi, CR, TWI_BIT(STOP));
-+ }
-+
-+ if (twi->acks_left == 0)
-+ twi_writel(twi, IDR, ~TWI_BIT(TXCOMP));
-+ }
-+
-+ /* enabling this message helps trigger overruns/underruns ... */
-+ dev_vdbg(&twi->adapter.dev,
-+ "ISR: SR 0x%04X, mask 0x%04X, acks %i\n",
-+ old_status,
-+ twi->acks_left ? twi->mask : TWI_BIT(TXCOMP),
-+ twi->acks_left);
-+
-+ return IRQ_HANDLED;
-+
-+done:
-+ /* Note weak fault reporting model: we can't report how many
-+ * bytes we sent before the NAK, or let upper layers choose
-+ * whether to continue. The I2C stack doesn't allow that...
-+ */
-+ if (status & TWI_BIT(NACK)) {
-+ dev_dbg(&twi->adapter.dev, "NACK received! %d to go\n",
-+ twi->acks_left);
-+ twi->status = -EPIPE;
++ unsigned long flags;
++ u32 lower, upper;
+
-+ /* TX underrun morphs automagically into a premature STOP;
-+ * we'll probably observe UVRE even when it's not documented.
-+ */
-+ } else if (twi->acks_left && (twi->mask & TWI_BIT(TXRDY))) {
-+ dev_err(&twi->adapter.dev, "UNDERRUN TX! %04x, %d to go\n",
-+ old_status, twi->acks_left);
-+ twi->status = -ENOSR;
-+ }
++ raw_local_irq_save(flags);
++ do {
++ upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));
++ lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
++ } while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));
+
-+ twi_writel(twi, IDR, ~0UL);
-+ complete(&twi->comp);
++ raw_local_irq_restore(flags);
++ return (upper << 16) | lower;
++}
+
-+ dev_dbg(&twi->adapter.dev, "ISR: SR 0x%04X, acks %i --> %d\n",
-+ old_status, twi->acks_left, twi->status);
++static struct clocksource clksrc = {
++ .name = "tcb_clksrc",
++ .rating = 200,
++ .read = tc_get_cycles,
++ .mask = CLOCKSOURCE_MASK(32),
++ .shift = 18,
++ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
++};
+
-+ return IRQ_HANDLED;
-+}
++#ifdef CONFIG_GENERIC_CLOCKEVENTS
+
++struct tc_clkevt_device {
++ struct clock_event_device clkevt;
++ struct clk *clk;
++ void __iomem *regs;
++};
+
-+/*
-+ * Return list of supported functionality.
-+ *
-+ * NOTE: see warning above about repeated starts; this driver is falsely
-+ * claiming to support "combined" transfers. The mid-message STOPs mean
-+ * some slaves will never work with this driver. (Use i2c-gpio...)
-+ */
-+static u32 twi_func(struct i2c_adapter *adapter)
++static struct tc_clkevt_device *to_tc_clkevt(struct clock_event_device *clkevt)
+{
-+ return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL)
-+ & ~I2C_FUNC_SMBUS_QUICK;
++ return container_of(clkevt, struct tc_clkevt_device, clkevt);
+}
+
-+static struct i2c_algorithm twi_algorithm = {
-+ .master_xfer = twi_xfer,
-+ .functionality = twi_func,
-+};
-+
-+/*
-+ * Main initialization routine.
++/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
++ * because using one of the divided clocks would usually mean the
++ * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
++ *
++ * A divided clock could be good for high resolution timers, since
++ * 30.5 usec resolution can seem "low".
+ */
-+static int __init twi_probe(struct platform_device *pdev)
-+{
-+ struct atmel_twi *twi;
-+ struct resource *regs;
-+ struct clk *pclk;
-+ struct i2c_adapter *adapter;
-+ int rc, irq;
-+
-+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!regs)
-+ return -ENXIO;
++static u32 timer_clock;
+
-+ pclk = clk_get(&pdev->dev, "twi_pclk");
-+ if (IS_ERR(pclk))
-+ return PTR_ERR(pclk);
-+ clk_enable(pclk);
++static void tc_mode(enum clock_event_mode m, struct clock_event_device *d)
++{
++ struct tc_clkevt_device *tcd = to_tc_clkevt(d);
++ void __iomem *regs = tcd->regs;
+
-+ rc = -ENOMEM;
-+ twi = kzalloc(sizeof(struct atmel_twi), GFP_KERNEL);
-+ if (!twi) {
-+ dev_dbg(&pdev->dev, "can't allocate interface!\n");
-+ goto err_alloc_twi;
++ if (tcd->clkevt.mode == CLOCK_EVT_MODE_PERIODIC
++ || tcd->clkevt.mode == CLOCK_EVT_MODE_ONESHOT) {
++ __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));
++ __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
++ clk_disable(tcd->clk);
+ }
+
-+ twi->pclk = pclk;
-+ twi->regs = ioremap(regs->start, regs->end - regs->start + 1);
-+ if (!twi->regs)
-+ goto err_ioremap;
++ switch (m) {
+
-+ irq = platform_get_irq(pdev, 0);
-+ rc = request_irq(irq, twi_interrupt, 0, "twi", twi);
-+ if (rc) {
-+ dev_dbg(&pdev->dev, "can't bind irq!\n");
-+ goto err_irq;
-+ }
-+ twi->irq = irq;
++ /* By not making the gentime core emulate periodic mode on top
++ * of oneshot, we get lower overhead and improved accuracy.
++ */
++ case CLOCK_EVT_MODE_PERIODIC:
++ clk_enable(tcd->clk);
+
-+ rc = twi_hwinit(twi);
-+ if (rc) {
-+ dev_err(&pdev->dev, "Unable to set baudrate\n");
-+ goto err_hw_init;
-+ }
++ /* slow clock, count up to RC, then irq and restart */
++ __raw_writel(timer_clock
++ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
++ regs + ATMEL_TC_REG(2, CMR));
++ __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
+
-+ adapter = &twi->adapter;
-+ sprintf(adapter->name, "TWI");
-+ adapter->algo = &twi_algorithm;
-+ adapter->class = I2C_CLASS_ALL;
-+ adapter->nr = pdev->id;
-+ adapter->dev.parent = &pdev->dev;
++ /* Enable clock and interrupts on RC compare */
++ __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+
-+ platform_set_drvdata(pdev, twi);
++ /* go go gadget! */
++ __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
++ regs + ATMEL_TC_REG(2, CCR));
++ break;
+
-+ rc = i2c_add_numbered_adapter(adapter);
-+ if (rc) {
-+ dev_dbg(&pdev->dev, "Adapter %s registration failed\n",
-+ adapter->name);
-+ goto err_register;
-+ }
++ case CLOCK_EVT_MODE_ONESHOT:
++ clk_enable(tcd->clk);
+
-+ dev_info(&pdev->dev,
-+ "Atmel TWI/I2C adapter (baudrate %dk) at 0x%08lx.\n",
-+ baudrate/1000, (unsigned long)regs->start);
++ /* slow clock, count up to RC, then irq and stop */
++ __raw_writel(timer_clock | ATMEL_TC_CPCSTOP
++ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
++ regs + ATMEL_TC_REG(2, CMR));
++ __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
+
-+ return 0;
++ /* set_next_event() configures and starts the timer */
++ break;
+
++ default:
++ break;
++ }
++}
+
-+err_register:
-+ platform_set_drvdata(pdev, NULL);
++static int tc_next_event(unsigned long delta, struct clock_event_device *d)
++{
++ __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));
+
-+err_hw_init:
-+ free_irq(irq, twi);
++ /* go go gadget! */
++ __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
++ tcaddr + ATMEL_TC_REG(2, CCR));
++ return 0;
++}
+
-+err_irq:
-+ iounmap(twi->regs);
++static struct tc_clkevt_device clkevt = {
++ .clkevt = {
++ .name = "tc_clkevt",
++ .features = CLOCK_EVT_FEAT_PERIODIC
++ | CLOCK_EVT_FEAT_ONESHOT,
++ .shift = 32,
++ /* Should be lower than at91rm9200's system timer */
++ .rating = 125,
++ .cpumask = CPU_MASK_CPU0,
++ .set_next_event = tc_next_event,
++ .set_mode = tc_mode,
++ },
++};
+
-+err_ioremap:
-+ kfree(twi);
++static irqreturn_t ch2_irq(int irq, void *handle)
++{
++ struct tc_clkevt_device *dev = handle;
++ unsigned int sr;
+
-+err_alloc_twi:
-+ clk_disable(pclk);
-+ clk_put(pclk);
++ sr = __raw_readl(dev->regs + ATMEL_TC_REG(2, SR));
++ if (sr & ATMEL_TC_CPCS) {
++ dev->clkevt.event_handler(&dev->clkevt);
++ return IRQ_HANDLED;
++ }
+
-+ return rc;
++ return IRQ_NONE;
+}
+
-+static int __exit twi_remove(struct platform_device *pdev)
++static struct irqaction tc_irqaction = {
++ .name = "tc_clkevt",
++ .flags = IRQF_TIMER | IRQF_DISABLED,
++ .handler = ch2_irq,
++};
++
++static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
+{
-+ struct atmel_twi *twi = platform_get_drvdata(pdev);
-+ int res;
++ struct clk *t2_clk = tc->clk[2];
++ int irq = tc->irq[2];
+
-+ platform_set_drvdata(pdev, NULL);
-+ res = i2c_del_adapter(&twi->adapter);
-+ twi_writel(twi, CR, TWI_BIT(MSDIS));
-+ iounmap(twi->regs);
-+ clk_disable(twi->pclk);
-+ clk_put(twi->pclk);
-+ free_irq(twi->irq, twi);
-+ kfree(twi);
++ clkevt.regs = tc->regs;
++ clkevt.clk = t2_clk;
++ tc_irqaction.dev_id = &clkevt;
+
-+ return res;
-+}
++ timer_clock = clk32k_divisor_idx;
+
-+static struct platform_driver twi_driver = {
-+ .remove = __exit_p(twi_remove),
-+ .driver = {
-+ .name = "atmel_twi",
-+ .owner = THIS_MODULE,
-+ },
-+};
++ clkevt.clkevt.mult = div_sc(32768, NSEC_PER_SEC, clkevt.clkevt.shift);
++ clkevt.clkevt.max_delta_ns
++ = clockevent_delta2ns(0xffff, &clkevt.clkevt);
++ clkevt.clkevt.min_delta_ns = clockevent_delta2ns(1, &clkevt.clkevt) + 1;
+
-+static int __init atmel_twi_init(void)
-+{
-+ return platform_driver_probe(&twi_driver, twi_probe);
++ setup_irq(irq, &tc_irqaction);
++
++ clockevents_register_device(&clkevt.clkevt);
+}
+
-+static void __exit atmel_twi_exit(void)
++#else /* !CONFIG_GENERIC_CLOCKEVENTS */
++
++static void __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
+{
-+ platform_driver_unregister(&twi_driver);
++ /* NOTHING */
+}
+
-+module_init(atmel_twi_init);
-+module_exit(atmel_twi_exit);
++#endif
+
-+MODULE_AUTHOR("Espen Krangnes");
-+MODULE_DESCRIPTION("I2C driver for Atmel TWI");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/i2c/busses/i2c-atmeltwi.h
-@@ -0,0 +1,117 @@
-+/*
-+ * Register definitions for the Atmel Two-Wire Interface
-+ */
++static int __init tcb_clksrc_init(void)
++{
++ static char bootinfo[] __initdata
++ = KERN_DEBUG "%s: tc%d at %d.%03d MHz\n";
+
-+#ifndef __ATMELTWI_H__
-+#define __ATMELTWI_H__
++ struct platform_device *pdev;
++ struct atmel_tc *tc;
++ struct clk *t0_clk;
++ u32 rate, divided_rate = 0;
++ int best_divisor_idx = -1;
++ int clk32k_divisor_idx = -1;
++ int i;
+
-+/* TWI register offsets */
-+#define TWI_CR 0x0000
-+#define TWI_MMR 0x0004
-+#define TWI_SMR 0x0008
-+#define TWI_IADR 0x000c
-+#define TWI_CWGR 0x0010
-+#define TWI_SR 0x0020
-+#define TWI_IER 0x0024
-+#define TWI_IDR 0x0028
-+#define TWI_IMR 0x002c
-+#define TWI_RHR 0x0030
-+#define TWI_THR 0x0034
++ tc = atmel_tc_alloc(CONFIG_ATMEL_TCB_CLKSRC_BLOCK, clksrc.name);
++ if (!tc) {
++ pr_debug("can't alloc TC for clocksource\n");
++ return -ENODEV;
++ }
++ tcaddr = tc->regs;
++ pdev = tc->pdev;
+
-+/* Bitfields in CR */
-+#define TWI_START_OFFSET 0
-+#define TWI_START_SIZE 1
-+#define TWI_STOP_OFFSET 1
-+#define TWI_STOP_SIZE 1
-+#define TWI_MSEN_OFFSET 2
-+#define TWI_MSEN_SIZE 1
-+#define TWI_MSDIS_OFFSET 3
-+#define TWI_MSDIS_SIZE 1
-+#define TWI_SVEN_OFFSET 4
-+#define TWI_SVEN_SIZE 1
-+#define TWI_SVDIS_OFFSET 5
-+#define TWI_SVDIS_SIZE 1
-+#define TWI_SWRST_OFFSET 7
-+#define TWI_SWRST_SIZE 1
++ t0_clk = tc->clk[0];
++ clk_enable(t0_clk);
+
-+/* Bitfields in MMR */
-+#define TWI_IADRSZ_OFFSET 8
-+#define TWI_IADRSZ_SIZE 2
-+#define TWI_MREAD_OFFSET 12
-+#define TWI_MREAD_SIZE 1
-+#define TWI_DADR_OFFSET 16
-+#define TWI_DADR_SIZE 7
++ /* How fast will we be counting? Pick something over 5 MHz. */
++ rate = (u32) clk_get_rate(t0_clk);
++ for (i = 0; i < 5; i++) {
++ unsigned divisor = atmel_tc_divisors[i];
++ unsigned tmp;
+
-+/* Bitfields in SMR */
-+#define TWI_SADR_OFFSET 16
-+#define TWI_SADR_SIZE 7
++ /* remember 32 KiHz clock for later */
++ if (!divisor) {
++ clk32k_divisor_idx = i;
++ continue;
++ }
+
-+/* Bitfields in IADR */
-+#define TWI_IADR_OFFSET 0
-+#define TWI_IADR_SIZE 24
++ tmp = rate / divisor;
++ pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
++ if (best_divisor_idx > 0) {
++ if (tmp < 5 * 1000 * 1000)
++ continue;
++ }
++ divided_rate = tmp;
++ best_divisor_idx = i;
++ }
+
-+/* Bitfields in CWGR */
-+#define TWI_CLDIV_OFFSET 0
-+#define TWI_CLDIV_SIZE 8
-+#define TWI_CHDIV_OFFSET 8
-+#define TWI_CHDIV_SIZE 8
-+#define TWI_CKDIV_OFFSET 16
-+#define TWI_CKDIV_SIZE 3
++ clksrc.mult = clocksource_hz2mult(divided_rate, clksrc.shift);
+
-+/* Bitfields in SR */
-+#define TWI_TXCOMP_OFFSET 0
-+#define TWI_TXCOMP_SIZE 1
-+#define TWI_RXRDY_OFFSET 1
-+#define TWI_RXRDY_SIZE 1
-+#define TWI_TXRDY_OFFSET 2
-+#define TWI_TXRDY_SIZE 1
-+#define TWI_SVDIR_OFFSET 3
-+#define TWI_SVDIR_SIZE 1
-+#define TWI_SVACC_OFFSET 4
-+#define TWI_SVACC_SIZE 1
-+#define TWI_GCACC_OFFSET 5
-+#define TWI_GCACC_SIZE 1
-+#define TWI_OVRE_OFFSET 6
-+#define TWI_OVRE_SIZE 1
-+#define TWI_UNRE_OFFSET 7
-+#define TWI_UNRE_SIZE 1
-+#define TWI_NACK_OFFSET 8
-+#define TWI_NACK_SIZE 1
-+#define TWI_ARBLST_OFFSET 9
-+#define TWI_ARBLST_SIZE 1
++ printk(bootinfo, clksrc.name, CONFIG_ATMEL_TCB_CLKSRC_BLOCK,
++ divided_rate / 1000000,
++ ((divided_rate + 500000) % 1000000) / 1000);
+
-+/* Bitfields in RHR */
-+#define TWI_RXDATA_OFFSET 0
-+#define TWI_RXDATA_SIZE 8
++ /* tclib will give us three clocks no matter what the
++ * underlying platform supports.
++ */
++ clk_enable(tc->clk[1]);
+
-+/* Bitfields in THR */
-+#define TWI_TXDATA_OFFSET 0
-+#define TWI_TXDATA_SIZE 8
++ /* channel 0: waveform mode, input mclk/8, clock TIOA0 on overflow */
++ __raw_writel(best_divisor_idx /* likely divide-by-8 */
++ | ATMEL_TC_WAVE
++ | ATMEL_TC_WAVESEL_UP /* free-run */
++ | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */
++ | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */
++ tcaddr + ATMEL_TC_REG(0, CMR));
++ __raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));
++ __raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));
++ __raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR)); /* no irqs */
++ __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));
+
-+/* Constants for IADRSZ */
-+#define TWI_IADRSZ_NO_ADDR 0
-+#define TWI_IADRSZ_ONE_BYTE 1
-+#define TWI_IADRSZ_TWO_BYTES 2
-+#define TWI_IADRSZ_THREE_BYTES 3
++ /* channel 1: waveform mode, input TIOA0 */
++ __raw_writel(ATMEL_TC_XC1 /* input: TIOA0 */
++ | ATMEL_TC_WAVE
++ | ATMEL_TC_WAVESEL_UP, /* free-run */
++ tcaddr + ATMEL_TC_REG(1, CMR));
++ __raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR)); /* no irqs */
++ __raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));
+
-+/* Bit manipulation macros */
-+#define TWI_BIT(name) \
-+ (1 << TWI_##name##_OFFSET)
-+#define TWI_BF(name, value) \
-+ (((value) & ((1 << TWI_##name##_SIZE) - 1)) \
-+ << TWI_##name##_OFFSET)
-+#define TWI_BFEXT(name, value) \
-+ (((value) >> TWI_##name##_OFFSET) \
-+ & ((1 << TWI_##name##_SIZE) - 1))
-+#define TWI_BFINS(name, value, old) \
-+ (((old) & ~(((1 << TWI_##name##_SIZE) - 1) \
-+ << TWI_##name##_OFFSET)) \
-+ | TWI_BF(name, (value)))
++ /* chain channel 0 to channel 1, then reset all the timers */
++ __raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);
++ __raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
+
-+/* Register access macros */
-+#define twi_readl(port, reg) \
-+ __raw_readl((port)->regs + TWI_##reg)
-+#define twi_writel(port, reg, value) \
-+ __raw_writel((value), (port)->regs + TWI_##reg)
++ /* and away we go! */
++ clocksource_register(&clksrc);
+
-+#endif /* __ATMELTWI_H__ */
++ /* channel 2: periodic and oneshot timer support */
++ setup_clkevents(tc, clk32k_divisor_idx);
++
++ return 0;
++}
++arch_initcall(tcb_clksrc_init);
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -88,6 +88,14 @@
depends on SOC_AU1550 || SOC_AU1200
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
-@@ -53,6 +53,7 @@
+@@ -52,6 +52,7 @@
obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3.o
obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
EXTRA_CFLAGS += -DDEBUG
--- /dev/null
-+++ b/drivers/input/serio/at32psif.c
-@@ -0,0 +1,351 @@
++++ b/drivers/i2c/busses/i2c-atmeltwi.c
+@@ -0,0 +1,436 @@
+/*
-+ * Copyright (C) 2007 Atmel Corporation
++ * i2c Support for Atmel's Two-Wire Interface (TWI)
+ *
-+ * Driver for the AT32AP700X PS/2 controller (PSIF).
++ * Based on the work of Copyright (C) 2004 Rick Bronson
++ * Converted to 2.6 by Andrew Victor <andrew at sanpeople.com>
++ * Ported to AVR32 and heavily modified by Espen Krangnes
++ * <ekrangnes at atmel.com>
+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
++ * Copyright (C) 2006 Atmel Corporation
++ *
++ * Borrowed heavily from the original work by:
++ * Copyright (C) 2000 Philip Edelbrock <phil at stimpy.netroedge.com>
++ *
++ * Partialy rewriten by Karel Hojdar <cmkaho at seznam.cz>
++ * bugs removed, interrupt routine markedly rewritten
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
+ */
-+#include <linux/kernel.h>
++#undef VERBOSE_DEBUG
++
+#include <linux/module.h>
-+#include <linux/device.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
+#include <linux/init.h>
-+#include <linux/serio.h>
-+#include <linux/timer.h>
-+#include <linux/interrupt.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
+#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
+#include <linux/platform_device.h>
++#include <linux/completion.h>
++#include <linux/io.h>
+
-+#include "at32psif.h"
++#include "i2c-atmeltwi.h"
+
-+#define PSIF_BUF_SIZE 16
++static unsigned int baudrate = 100 * 1000;
++module_param(baudrate, uint, S_IRUGO);
++MODULE_PARM_DESC(baudrate, "The TWI baudrate");
+
-+#define ring_is_empty(_psif) (_psif->head == _psif->tail)
-+#define ring_next_head(_psif) ((_psif->head + 1) & (PSIF_BUF_SIZE - 1))
-+#define ring_next_tail(_psif) ((_psif->tail + 1) & (PSIF_BUF_SIZE - 1))
+
-+struct psif {
-+ struct platform_device *pdev;
-+ struct clk *pclk;
-+ struct serio *io;
-+ struct timer_list tx_timer;
-+ void __iomem *regs;
-+ unsigned int irq;
-+ unsigned int open;
-+ /* Prevent concurrent writes to circular buffer. */
-+ spinlock_t lock;
-+ unsigned int head;
-+ unsigned int tail;
-+ unsigned char buffer[PSIF_BUF_SIZE];
++struct atmel_twi {
++ void __iomem *regs;
++ struct i2c_adapter adapter;
++ struct clk *pclk;
++ struct completion comp;
++ u32 mask;
++ u8 *buf;
++ u16 len;
++ u16 acks_left;
++ int status;
++ unsigned int irq;
++
+};
++#define to_atmel_twi(adap) container_of(adap, struct atmel_twi, adapter)
++
++/*
++ * (Re)Initialize the TWI hardware registers.
++ */
++static int twi_hwinit(struct atmel_twi *twi)
++{
++ unsigned long cdiv, ckdiv = 0;
++
++ /* REVISIT: wait till SCL is high before resetting; otherwise,
++ * some versions will wedge forever.
++ */
++
++ twi_writel(twi, IDR, ~0UL);
++ twi_writel(twi, CR, TWI_BIT(SWRST)); /*Reset peripheral*/
++ twi_readl(twi, SR);
++
++ cdiv = (clk_get_rate(twi->pclk) / (2 * baudrate)) - 4;
++
++ while (cdiv > 255) {
++ ckdiv++;
++ cdiv = cdiv >> 1;
++ }
++
++ /* REVISIT: there are various errata to consider re CDIV and CHDIV
++ * here, at least on at91 parts.
++ */
++
++ if (ckdiv > 7)
++ return -EINVAL;
++ else
++ twi_writel(twi, CWGR, TWI_BF(CKDIV, ckdiv)
++ | TWI_BF(CHDIV, cdiv)
++ | TWI_BF(CLDIV, cdiv));
++ return 0;
++}
+
-+static irqreturn_t psif_interrupt(int irq, void *_ptr)
++/*
++ * Waits for the i2c status register to set the specified bitmask
++ * Returns 0 if timed out ... ~100ms is much longer than the SMBus
++ * limit, but I2C has no limit at all.
++ */
++static int twi_complete(struct atmel_twi *twi, u32 mask)
+{
-+ struct psif *psif = _ptr;
-+ int retval = IRQ_NONE;
-+ unsigned int io_flags = 0;
-+ unsigned long status;
++ int timeout = msecs_to_jiffies(100);
+
-+ status = psif_readl(psif, SR);
++ mask |= TWI_BIT(TXCOMP);
++ twi->mask = mask | TWI_BIT(NACK) | TWI_BIT(OVRE);
++ init_completion(&twi->comp);
+
-+ if (status & PSIF_BIT(RXRDY)) {
-+ unsigned char val = (unsigned char) psif_readl(psif, RHR);
++ twi_writel(twi, IER, mask);
+
-+ if (status & PSIF_BIT(PARITY))
-+ io_flags |= SERIO_PARITY;
-+ if (status & PSIF_BIT(OVRUN))
-+ dev_err(&psif->pdev->dev, "overrun read error\n");
++ if (!wait_for_completion_timeout(&twi->comp, timeout)) {
++ /* RESET TWI interface */
++ twi_writel(twi, CR, TWI_BIT(SWRST));
+
-+ serio_interrupt(psif->io, val, io_flags);
++ /* Reinitialize TWI */
++ twi_hwinit(twi);
+
-+ retval = IRQ_HANDLED;
++ return -ETIMEDOUT;
+ }
++ return 0;
++}
+
-+ spin_lock(&psif->lock);
++/*
++ * Generic i2c master transfer entrypoint.
++ */
++static int twi_xfer(struct i2c_adapter *adap, struct i2c_msg *pmsg, int num)
++{
++ struct atmel_twi *twi = to_atmel_twi(adap);
++ int i;
+
-+ if (status & PSIF_BIT(TXEMPTY)) {
-+ if (status & PSIF_BIT(NACK))
-+ dev_err(&psif->pdev->dev, "NACK error\n");
++ dev_dbg(&adap->dev, "twi_xfer: processing %d messages:\n", num);
+
-+ psif_writel(psif, IDR, PSIF_BIT(TXEMPTY));
++ twi->status = 0;
++ for (i = 0; i < num; i++, pmsg++) {
++ twi->len = pmsg->len;
++ twi->buf = pmsg->buf;
++ twi->acks_left = pmsg->len;
++ twi_writel(twi, MMR, TWI_BF(DADR, pmsg->addr) |
++ (pmsg->flags & I2C_M_RD ? TWI_BIT(MREAD) : 0));
++ twi_writel(twi, IADR, TWI_BF(IADR, pmsg->addr));
+
-+ if (!ring_is_empty(psif))
-+ mod_timer(&psif->tx_timer,
-+ jiffies + msecs_to_jiffies(1));
++ dev_dbg(&adap->dev,
++ "#%d: %s %d byte%s %s dev 0x%02x\n",
++ i,
++ pmsg->flags & I2C_M_RD ? "reading" : "writing",
++ pmsg->len,
++ pmsg->len > 1 ? "s" : "",
++ pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr);
+
-+ retval = IRQ_HANDLED;
-+ }
++ /* enable */
++ twi_writel(twi, CR, TWI_BIT(MSEN));
+
-+ spin_unlock(&psif->lock);
++ if (pmsg->flags & I2C_M_RD) {
++ /* cleanup after previous RX overruns */
++ while (twi_readl(twi, SR) & TWI_BIT(RXRDY))
++ twi_readl(twi, RHR);
+
-+ return retval;
-+}
++ if (twi->len == 1)
++ twi_writel(twi, CR,
++ TWI_BIT(START) | TWI_BIT(STOP));
++ else
++ twi_writel(twi, CR, TWI_BIT(START));
+
-+static void psif_transmit_data(unsigned long data)
-+{
-+ struct psif *psif = (struct psif *)data;
-+ unsigned long flags;
++ if (twi_complete(twi, TWI_BIT(RXRDY)) == -ETIMEDOUT) {
++ dev_dbg(&adap->dev, "RX[%d] timeout. "
++ "Stopped with %d bytes left\n",
++ i, twi->acks_left);
++ return -ETIMEDOUT;
++ }
++ } else {
++ twi_writel(twi, THR, twi->buf[0]);
++ twi->acks_left--;
++ /* REVISIT: some chips don't start automagically:
++ * twi_writel(twi, CR, TWI_BIT(START));
++ */
++ if (twi_complete(twi, TWI_BIT(TXRDY)) == -ETIMEDOUT) {
++ dev_dbg(&adap->dev, "TX[%d] timeout. "
++ "Stopped with %d bytes left\n",
++ i, twi->acks_left);
++ return -ETIMEDOUT;
++ }
++ /* REVISIT: an erratum workaround may be needed here;
++ * see sam9261 "STOP not generated" (START either).
++ */
++ }
+
-+ spin_lock_irqsave(&psif->lock, flags);
++ /* Disable TWI interface */
++ twi_writel(twi, CR, TWI_BIT(MSDIS));
+
-+ psif_writel(psif, THR, psif->buffer[psif->tail]);
-+ psif->tail = ring_next_tail(psif);
++ if (twi->status)
++ return twi->status;
+
-+ if (!ring_is_empty(psif))
-+ psif_writel(psif, IER, PSIF_BIT(TXEMPTY));
++ /* WARNING: This driver lies about properly supporting
++ * repeated start, or it would *ALWAYS* return here. It
++ * has issued a STOP. Continuing is a false claim -- that
++ * a second (or third, etc.) message is part of the same
++ * "combined" (no STOPs between parts) message.
++ */
+
-+ spin_unlock_irqrestore(&psif->lock, flags);
++ } /* end cur msg */
++
++ return i;
+}
+
-+static int psif_write(struct serio *io, unsigned char val)
++
++static irqreturn_t twi_interrupt(int irq, void *dev_id)
+{
-+ struct psif *psif = io->port_data;
-+ unsigned long flags;
-+ unsigned int head;
++ struct atmel_twi *twi = dev_id;
++ int status = twi_readl(twi, SR);
+
-+ spin_lock_irqsave(&psif->lock, flags);
++ /* Save state for later debug prints */
++ int old_status = status;
+
-+ head = ring_next_head(psif);
++ if (twi->mask & status) {
+
-+ if (head != psif->tail) {
-+ psif->buffer[psif->head] = val;
-+ psif->head = head;
-+ } else {
-+ dev_err(&psif->pdev->dev, "underrun write error\n");
-+ }
++ status &= twi->mask;
+
-+ spin_unlock_irqrestore(&psif->lock, flags);
++ if (status & TWI_BIT(RXRDY)) {
++ if ((status & TWI_BIT(OVRE)) && twi->acks_left) {
++ /* Note weakness in fault reporting model:
++ * we can't say "the first N of these data
++ * bytes are valid".
++ */
++ dev_err(&twi->adapter.dev,
++ "OVERRUN RX! %04x, lost %d\n",
++ old_status, twi->acks_left);
++ twi->acks_left = 0;
++ twi_writel(twi, CR, TWI_BIT(STOP));
++ twi->status = -EOVERFLOW;
++ } else if (twi->acks_left > 0) {
++ twi->buf[twi->len - twi->acks_left] =
++ twi_readl(twi, RHR);
++ twi->acks_left--;
++ }
++ if (status & TWI_BIT(TXCOMP))
++ goto done;
++ if (twi->acks_left == 1)
++ twi_writel(twi, CR, TWI_BIT(STOP));
+
-+ /* Make sure TXEMPTY interrupt is enabled. */
-+ psif_writel(psif, IER, PSIF_BIT(TXEMPTY));
++ } else if (status & (TWI_BIT(NACK) | TWI_BIT(TXCOMP))) {
++ goto done;
+
-+ return 0;
-+}
++ } else if (status & TWI_BIT(TXRDY)) {
++ if (twi->acks_left > 0) {
++ twi_writel(twi, THR,
++ twi->buf[twi->len - twi->acks_left]);
++ twi->acks_left--;
++ } else
++ twi_writel(twi, CR, TWI_BIT(STOP));
++ }
+
-+static int psif_open(struct serio *io)
-+{
-+ struct psif *psif = io->port_data;
-+ int retval;
++ if (twi->acks_left == 0)
++ twi_writel(twi, IDR, ~TWI_BIT(TXCOMP));
++ }
+
-+ retval = clk_enable(psif->pclk);
-+ if (retval)
-+ goto out;
++ /* enabling this message helps trigger overruns/underruns ... */
++ dev_vdbg(&twi->adapter.dev,
++ "ISR: SR 0x%04X, mask 0x%04X, acks %i\n",
++ old_status,
++ twi->acks_left ? twi->mask : TWI_BIT(TXCOMP),
++ twi->acks_left);
+
-+ psif_writel(psif, CR, PSIF_BIT(CR_TXEN) | PSIF_BIT(CR_RXEN));
-+ psif_writel(psif, IER, PSIF_BIT(RXRDY));
++ return IRQ_HANDLED;
+
-+ psif->open = 1;
-+out:
-+ return retval;
-+}
++done:
++ /* Note weak fault reporting model: we can't report how many
++ * bytes we sent before the NAK, or let upper layers choose
++ * whether to continue. The I2C stack doesn't allow that...
++ */
++ if (status & TWI_BIT(NACK)) {
++ dev_dbg(&twi->adapter.dev, "NACK received! %d to go\n",
++ twi->acks_left);
++ twi->status = -EPIPE;
+
-+static void psif_close(struct serio *io)
-+{
-+ struct psif *psif = io->port_data;
++ /* TX underrun morphs automagically into a premature STOP;
++ * we'll probably observe UVRE even when it's not documented.
++ */
++ } else if (twi->acks_left && (twi->mask & TWI_BIT(TXRDY))) {
++ dev_err(&twi->adapter.dev, "UNDERRUN TX! %04x, %d to go\n",
++ old_status, twi->acks_left);
++ twi->status = -ENOSR;
++ }
+
-+ psif->open = 0;
++ twi_writel(twi, IDR, ~0UL);
++ complete(&twi->comp);
+
-+ psif_writel(psif, IDR, ~0UL);
-+ psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
++ dev_dbg(&twi->adapter.dev, "ISR: SR 0x%04X, acks %i --> %d\n",
++ old_status, twi->acks_left, twi->status);
+
-+ clk_disable(psif->pclk);
++ return IRQ_HANDLED;
+}
+
-+static void psif_set_prescaler(struct psif *psif)
-+{
-+ unsigned long prscv;
-+ unsigned long rate = clk_get_rate(psif->pclk);
-+
-+ /* PRSCV = Pulse length (100 us) * PSIF module frequency. */
-+ prscv = 100 * (rate / 1000000UL);
-+
-+ if (prscv > ((1<<PSIF_PSR_PRSCV_SIZE) - 1)) {
-+ prscv = (1<<PSIF_PSR_PRSCV_SIZE) - 1;
-+ dev_dbg(&psif->pdev->dev, "pclk too fast, "
-+ "prescaler set to max\n");
-+ }
+
-+ clk_enable(psif->pclk);
-+ psif_writel(psif, PSR, prscv);
-+ clk_disable(psif->pclk);
++/*
++ * Return list of supported functionality.
++ *
++ * NOTE: see warning above about repeated starts; this driver is falsely
++ * claiming to support "combined" transfers. The mid-message STOPs mean
++ * some slaves will never work with this driver. (Use i2c-gpio...)
++ */
++static u32 twi_func(struct i2c_adapter *adapter)
++{
++ return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL)
++ & ~I2C_FUNC_SMBUS_QUICK;
+}
+
-+static int __init psif_probe(struct platform_device *pdev)
++static struct i2c_algorithm twi_algorithm = {
++ .master_xfer = twi_xfer,
++ .functionality = twi_func,
++};
++
++/*
++ * Main initialization routine.
++ */
++static int __init twi_probe(struct platform_device *pdev)
+{
++ struct atmel_twi *twi;
+ struct resource *regs;
-+ struct psif *psif;
-+ struct serio *io;
+ struct clk *pclk;
-+ int irq;
-+ int ret;
-+
-+ psif = kzalloc(sizeof(struct psif), GFP_KERNEL);
-+ if (!psif) {
-+ dev_dbg(&pdev->dev, "out of memory\n");
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+ psif->pdev = pdev;
-+
-+ io = kzalloc(sizeof(struct serio), GFP_KERNEL);
-+ if (!io) {
-+ dev_dbg(&pdev->dev, "out of memory\n");
-+ ret = -ENOMEM;
-+ goto out_free_psif;
-+ }
-+ psif->io = io;
++ struct i2c_adapter *adapter;
++ int rc, irq;
+
+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!regs) {
-+ dev_dbg(&pdev->dev, "no mmio resources defined\n");
-+ ret = -ENOMEM;
-+ goto out_free_io;
-+ }
-+
-+ psif->regs = ioremap(regs->start, regs->end - regs->start + 1);
-+ if (!psif->regs) {
-+ ret = -ENOMEM;
-+ dev_dbg(&pdev->dev, "could not map I/O memory\n");
-+ goto out_free_io;
-+ }
++ if (!regs)
++ return -ENXIO;
+
-+ pclk = clk_get(&pdev->dev, "pclk");
-+ if (IS_ERR(pclk)) {
-+ dev_dbg(&pdev->dev, "could not get peripheral clock\n");
-+ ret = PTR_ERR(pclk);
-+ goto out_iounmap;
-+ }
-+ psif->pclk = pclk;
++ pclk = clk_get(&pdev->dev, "twi_pclk");
++ if (IS_ERR(pclk))
++ return PTR_ERR(pclk);
++ clk_enable(pclk);
+
-+ /* Reset the PSIF to enter at a known state. */
-+ ret = clk_enable(pclk);
-+ if (ret) {
-+ dev_dbg(&pdev->dev, "could not enable pclk\n");
-+ goto out_put_clk;
++ rc = -ENOMEM;
++ twi = kzalloc(sizeof(struct atmel_twi), GFP_KERNEL);
++ if (!twi) {
++ dev_dbg(&pdev->dev, "can't allocate interface!\n");
++ goto err_alloc_twi;
+ }
-+ psif_writel(psif, CR, PSIF_BIT(CR_SWRST));
-+ clk_disable(pclk);
+
-+ setup_timer(&psif->tx_timer, psif_transmit_data, (unsigned long)psif);
++ twi->pclk = pclk;
++ twi->regs = ioremap(regs->start, regs->end - regs->start + 1);
++ if (!twi->regs)
++ goto err_ioremap;
+
+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0) {
-+ dev_dbg(&pdev->dev, "could not get irq\n");
-+ ret = -ENXIO;
-+ goto out_put_clk;
++ rc = request_irq(irq, twi_interrupt, 0, "twi", twi);
++ if (rc) {
++ dev_dbg(&pdev->dev, "can't bind irq!\n");
++ goto err_irq;
+ }
-+ ret = request_irq(irq, psif_interrupt, IRQF_SHARED, "at32psif", psif);
-+ if (ret) {
-+ dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
-+ goto out_put_clk;
++ twi->irq = irq;
++
++ rc = twi_hwinit(twi);
++ if (rc) {
++ dev_err(&pdev->dev, "Unable to set baudrate\n");
++ goto err_hw_init;
+ }
-+ psif->irq = irq;
+
-+ io->id.type = SERIO_8042;
-+ io->write = psif_write;
-+ io->open = psif_open;
-+ io->close = psif_close;
-+ strlcpy(io->name, pdev->dev.bus_id, sizeof(io->name));
-+ strlcpy(io->phys, pdev->dev.bus_id, sizeof(io->phys));
-+ io->port_data = psif;
-+ io->dev.parent = &pdev->dev;
++ adapter = &twi->adapter;
++ sprintf(adapter->name, "TWI");
++ adapter->algo = &twi_algorithm;
++ adapter->class = I2C_CLASS_ALL;
++ adapter->nr = pdev->id;
++ adapter->dev.parent = &pdev->dev;
+
-+ psif_set_prescaler(psif);
++ platform_set_drvdata(pdev, twi);
+
-+ spin_lock_init(&psif->lock);
-+ serio_register_port(psif->io);
-+ platform_set_drvdata(pdev, psif);
++ rc = i2c_add_numbered_adapter(adapter);
++ if (rc) {
++ dev_dbg(&pdev->dev, "Adapter %s registration failed\n",
++ adapter->name);
++ goto err_register;
++ }
+
-+ dev_info(&pdev->dev, "Atmel AVR32 PSIF PS/2 driver on 0x%08x irq %d\n",
-+ (int)psif->regs, psif->irq);
++ dev_info(&pdev->dev,
++ "Atmel TWI/I2C adapter (baudrate %dk) at 0x%08lx.\n",
++ baudrate/1000, (unsigned long)regs->start);
+
+ return 0;
+
-+out_put_clk:
-+ clk_put(psif->pclk);
-+out_iounmap:
-+ iounmap(psif->regs);
-+out_free_io:
-+ kfree(io);
-+out_free_psif:
-+ kfree(psif);
-+out:
-+ return ret;
-+}
-+
-+static int __exit psif_remove(struct platform_device *pdev)
-+{
-+ struct psif *psif = platform_get_drvdata(pdev);
-+
-+ psif_writel(psif, IDR, ~0UL);
-+ psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
-+
-+ serio_unregister_port(psif->io);
-+ iounmap(psif->regs);
-+ free_irq(psif->irq, psif);
-+ clk_put(psif->pclk);
-+ kfree(psif);
+
++err_register:
+ platform_set_drvdata(pdev, NULL);
+
-+ return 0;
-+}
++err_hw_init:
++ free_irq(irq, twi);
+
-+#ifdef CONFIG_PM
-+static int psif_suspend(struct platform_device *pdev, pm_message_t state)
-+{
-+ struct psif *psif = platform_get_drvdata(pdev);
++err_irq:
++ iounmap(twi->regs);
+
-+ if (psif->open) {
-+ psif_writel(psif, CR, PSIF_BIT(CR_RXDIS) | PSIF_BIT(CR_TXDIS));
-+ clk_disable(psif->pclk);
-+ }
++err_ioremap:
++ kfree(twi);
+
-+ return 0;
++err_alloc_twi:
++ clk_disable(pclk);
++ clk_put(pclk);
++
++ return rc;
+}
+
-+static int psif_resume(struct platform_device *pdev)
++static int __exit twi_remove(struct platform_device *pdev)
+{
-+ struct psif *psif = platform_get_drvdata(pdev);
++ struct atmel_twi *twi = platform_get_drvdata(pdev);
++ int res;
+
-+ if (psif->open) {
-+ clk_enable(psif->pclk);
-+ psif_set_prescaler(psif);
-+ psif_writel(psif, CR, PSIF_BIT(CR_RXEN) | PSIF_BIT(CR_TXEN));
-+ }
++ platform_set_drvdata(pdev, NULL);
++ res = i2c_del_adapter(&twi->adapter);
++ twi_writel(twi, CR, TWI_BIT(MSDIS));
++ iounmap(twi->regs);
++ clk_disable(twi->pclk);
++ clk_put(twi->pclk);
++ free_irq(twi->irq, twi);
++ kfree(twi);
+
-+ return 0;
++ return res;
+}
-+#else
-+#define psif_suspend NULL
-+#define psif_resume NULL
-+#endif
+
-+static struct platform_driver psif_driver = {
-+ .remove = __exit_p(psif_remove),
++static struct platform_driver twi_driver = {
++ .remove = __exit_p(twi_remove),
+ .driver = {
-+ .name = "atmel_psif",
++ .name = "atmel_twi",
++ .owner = THIS_MODULE,
+ },
-+ .suspend = psif_suspend,
-+ .resume = psif_resume,
+};
+
-+static int __init psif_init(void)
++static int __init atmel_twi_init(void)
+{
-+ return platform_driver_probe(&psif_driver, psif_probe);
++ return platform_driver_probe(&twi_driver, twi_probe);
+}
+
-+static void __exit psif_exit(void)
++static void __exit atmel_twi_exit(void)
+{
-+ platform_driver_unregister(&psif_driver);
++ platform_driver_unregister(&twi_driver);
+}
+
-+module_init(psif_init);
-+module_exit(psif_exit);
++module_init(atmel_twi_init);
++module_exit(atmel_twi_exit);
++
++MODULE_AUTHOR("Espen Krangnes");
++MODULE_DESCRIPTION("I2C driver for Atmel TWI");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-atmeltwi.h
+@@ -0,0 +1,117 @@
++/*
++ * Register definitions for the Atmel Two-Wire Interface
++ */
++
++#ifndef __ATMELTWI_H__
++#define __ATMELTWI_H__
++
++/* TWI register offsets */
++#define TWI_CR 0x0000
++#define TWI_MMR 0x0004
++#define TWI_SMR 0x0008
++#define TWI_IADR 0x000c
++#define TWI_CWGR 0x0010
++#define TWI_SR 0x0020
++#define TWI_IER 0x0024
++#define TWI_IDR 0x0028
++#define TWI_IMR 0x002c
++#define TWI_RHR 0x0030
++#define TWI_THR 0x0034
++
++/* Bitfields in CR */
++#define TWI_START_OFFSET 0
++#define TWI_START_SIZE 1
++#define TWI_STOP_OFFSET 1
++#define TWI_STOP_SIZE 1
++#define TWI_MSEN_OFFSET 2
++#define TWI_MSEN_SIZE 1
++#define TWI_MSDIS_OFFSET 3
++#define TWI_MSDIS_SIZE 1
++#define TWI_SVEN_OFFSET 4
++#define TWI_SVEN_SIZE 1
++#define TWI_SVDIS_OFFSET 5
++#define TWI_SVDIS_SIZE 1
++#define TWI_SWRST_OFFSET 7
++#define TWI_SWRST_SIZE 1
+
-+MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
-+MODULE_DESCRIPTION("Atmel AVR32 PSIF PS/2 driver");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/input/serio/at32psif.h
-@@ -0,0 +1,82 @@
-+/*
-+ * Copyright (C) 2007 Atmel Corporation
-+ *
-+ * Driver for the AT32AP700X PS/2 controller (PSIF).
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ */
++/* Bitfields in MMR */
++#define TWI_IADRSZ_OFFSET 8
++#define TWI_IADRSZ_SIZE 2
++#define TWI_MREAD_OFFSET 12
++#define TWI_MREAD_SIZE 1
++#define TWI_DADR_OFFSET 16
++#define TWI_DADR_SIZE 7
+
-+#ifndef _AT32PSIF_H
-+#define _AT32PSIF_H
++/* Bitfields in SMR */
++#define TWI_SADR_OFFSET 16
++#define TWI_SADR_SIZE 7
+
-+/* PSIF register offsets */
-+#define PSIF_CR 0x00
-+#define PSIF_RHR 0x04
-+#define PSIF_THR 0x08
-+#define PSIF_SR 0x10
-+#define PSIF_IER 0x14
-+#define PSIF_IDR 0x18
-+#define PSIF_IMR 0x1c
-+#define PSIF_PSR 0x24
++/* Bitfields in IADR */
++#define TWI_IADR_OFFSET 0
++#define TWI_IADR_SIZE 24
+
-+/* Bitfields in control register. */
-+#define PSIF_CR_RXDIS_OFFSET 1
-+#define PSIF_CR_RXDIS_SIZE 1
-+#define PSIF_CR_RXEN_OFFSET 0
-+#define PSIF_CR_RXEN_SIZE 1
-+#define PSIF_CR_SWRST_OFFSET 15
-+#define PSIF_CR_SWRST_SIZE 1
-+#define PSIF_CR_TXDIS_OFFSET 9
-+#define PSIF_CR_TXDIS_SIZE 1
-+#define PSIF_CR_TXEN_OFFSET 8
-+#define PSIF_CR_TXEN_SIZE 1
++/* Bitfields in CWGR */
++#define TWI_CLDIV_OFFSET 0
++#define TWI_CLDIV_SIZE 8
++#define TWI_CHDIV_OFFSET 8
++#define TWI_CHDIV_SIZE 8
++#define TWI_CKDIV_OFFSET 16
++#define TWI_CKDIV_SIZE 3
+
-+/* Bitfields in interrupt disable, enable, mask and status register. */
-+#define PSIF_NACK_OFFSET 8
-+#define PSIF_NACK_SIZE 1
-+#define PSIF_OVRUN_OFFSET 5
-+#define PSIF_OVRUN_SIZE 1
-+#define PSIF_PARITY_OFFSET 9
-+#define PSIF_PARITY_SIZE 1
-+#define PSIF_RXRDY_OFFSET 4
-+#define PSIF_RXRDY_SIZE 1
-+#define PSIF_TXEMPTY_OFFSET 1
-+#define PSIF_TXEMPTY_SIZE 1
-+#define PSIF_TXRDY_OFFSET 0
-+#define PSIF_TXRDY_SIZE 1
++/* Bitfields in SR */
++#define TWI_TXCOMP_OFFSET 0
++#define TWI_TXCOMP_SIZE 1
++#define TWI_RXRDY_OFFSET 1
++#define TWI_RXRDY_SIZE 1
++#define TWI_TXRDY_OFFSET 2
++#define TWI_TXRDY_SIZE 1
++#define TWI_SVDIR_OFFSET 3
++#define TWI_SVDIR_SIZE 1
++#define TWI_SVACC_OFFSET 4
++#define TWI_SVACC_SIZE 1
++#define TWI_GCACC_OFFSET 5
++#define TWI_GCACC_SIZE 1
++#define TWI_OVRE_OFFSET 6
++#define TWI_OVRE_SIZE 1
++#define TWI_UNRE_OFFSET 7
++#define TWI_UNRE_SIZE 1
++#define TWI_NACK_OFFSET 8
++#define TWI_NACK_SIZE 1
++#define TWI_ARBLST_OFFSET 9
++#define TWI_ARBLST_SIZE 1
+
-+/* Bitfields in prescale register. */
-+#define PSIF_PSR_PRSCV_OFFSET 0
-+#define PSIF_PSR_PRSCV_SIZE 12
++/* Bitfields in RHR */
++#define TWI_RXDATA_OFFSET 0
++#define TWI_RXDATA_SIZE 8
+
-+/* Bitfields in receive hold register. */
-+#define PSIF_RHR_RXDATA_OFFSET 0
-+#define PSIF_RHR_RXDATA_SIZE 8
++/* Bitfields in THR */
++#define TWI_TXDATA_OFFSET 0
++#define TWI_TXDATA_SIZE 8
+
-+/* Bitfields in transmit hold register. */
-+#define PSIF_THR_TXDATA_OFFSET 0
-+#define PSIF_THR_TXDATA_SIZE 8
++/* Constants for IADRSZ */
++#define TWI_IADRSZ_NO_ADDR 0
++#define TWI_IADRSZ_ONE_BYTE 1
++#define TWI_IADRSZ_TWO_BYTES 2
++#define TWI_IADRSZ_THREE_BYTES 3
+
+/* Bit manipulation macros */
-+#define PSIF_BIT(name) \
-+ (1 << PSIF_##name##_OFFSET)
-+#define PSIF_BF(name, value) \
-+ (((value) & ((1 << PSIF_##name##_SIZE) - 1)) \
-+ << PSIF_##name##_OFFSET)
-+#define PSIF_BFEXT(name, value)\
-+ (((value) >> PSIF_##name##_OFFSET) \
-+ & ((1 << PSIF_##name##_SIZE) - 1))
-+#define PSIF_BFINS(name, value, old) \
-+ (((old) & ~(((1 << PSIF_##name##_SIZE) - 1) \
-+ << PSIF_##name##_OFFSET)) \
-+ | PSIF_BF(name, value))
++#define TWI_BIT(name) \
++ (1 << TWI_##name##_OFFSET)
++#define TWI_BF(name, value) \
++ (((value) & ((1 << TWI_##name##_SIZE) - 1)) \
++ << TWI_##name##_OFFSET)
++#define TWI_BFEXT(name, value) \
++ (((value) >> TWI_##name##_OFFSET) \
++ & ((1 << TWI_##name##_SIZE) - 1))
++#define TWI_BFINS(name, value, old) \
++ (((old) & ~(((1 << TWI_##name##_SIZE) - 1) \
++ << TWI_##name##_OFFSET)) \
++ | TWI_BF(name, (value)))
+
+/* Register access macros */
-+#define psif_readl(port, reg) \
-+ __raw_readl((port)->regs + PSIF_##reg)
-+#define psif_writel(port, reg, value) \
-+ __raw_writel((value), (port)->regs + PSIF_##reg)
++#define twi_readl(port, reg) \
++ __raw_readl((port)->regs + TWI_##reg)
++#define twi_writel(port, reg, value) \
++ __raw_writel((value), (port)->regs + TWI_##reg)
+
-+#endif /* _AT32PSIF_H */
++#endif /* __ATMELTWI_H__ */
--- a/drivers/input/serio/Kconfig
+++ b/drivers/input/serio/Kconfig
@@ -88,6 +88,17 @@
obj-$(CONFIG_SERIO_Q40KBD) += q40kbd.o
obj-$(CONFIG_SERIO_GSCPS2) += gscps2.o
obj-$(CONFIG_HP_SDC) += hp_sdc.o
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -18,6 +18,13 @@
-
- comment "LED drivers"
-
-+config LEDS_ATMEL_PWM
-+ tristate "LED Support using Atmel PWM outputs"
-+ depends on LEDS_CLASS && ATMEL_PWM
-+ help
-+ This option enables support for LEDs driven using outputs
-+ of the dedicated PWM controller found on newer Atmel SOCs.
-+
- config LEDS_CORGI
- tristate "LED Support for the Sharp SL-C7x0 series"
- depends on LEDS_CLASS && PXA_SHARP_C7xx
--- /dev/null
-+++ b/drivers/leds/leds-atmel-pwm.c
-@@ -0,0 +1,155 @@
++++ b/drivers/input/serio/at32psif.c
+@@ -0,0 +1,351 @@
++/*
++ * Copyright (C) 2007 Atmel Corporation
++ *
++ * Driver for the AT32AP700X PS/2 controller (PSIF).
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
+#include <linux/kernel.h>
-+#include <linux/platform_device.h>
-+#include <linux/leds.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/serio.h>
++#include <linux/timer.h>
++#include <linux/interrupt.h>
++#include <linux/err.h>
+#include <linux/io.h>
-+#include <linux/atmel_pwm.h>
++#include <linux/clk.h>
++#include <linux/platform_device.h>
+
++#include "at32psif.h"
+
-+struct pwmled {
-+ struct led_classdev cdev;
-+ struct pwm_channel pwmc;
-+ struct gpio_led *desc;
-+ u32 mult;
-+ u8 active_low;
-+};
++#define PSIF_BUF_SIZE 16
+
++#define ring_is_empty(_psif) (_psif->head == _psif->tail)
++#define ring_next_head(_psif) ((_psif->head + 1) & (PSIF_BUF_SIZE - 1))
++#define ring_next_tail(_psif) ((_psif->tail + 1) & (PSIF_BUF_SIZE - 1))
+
-+/*
-+ * For simplicity, we use "brightness" as if it were a linear function
-+ * of PWM duty cycle. However, a logarithmic function of duty cycle is
-+ * probably a better match for perceived brightness: two is half as bright
-+ * as four, four is half as bright as eight, etc
-+ */
-+static void pwmled_brightness(struct led_classdev *cdev, enum led_brightness b)
++struct psif {
++ struct platform_device *pdev;
++ struct clk *pclk;
++ struct serio *io;
++ struct timer_list tx_timer;
++ void __iomem *regs;
++ unsigned int irq;
++ unsigned int open;
++ /* Prevent concurrent writes to circular buffer. */
++ spinlock_t lock;
++ unsigned int head;
++ unsigned int tail;
++ unsigned char buffer[PSIF_BUF_SIZE];
++};
++
++static irqreturn_t psif_interrupt(int irq, void *_ptr)
+{
-+ struct pwmled *led;
++ struct psif *psif = _ptr;
++ int retval = IRQ_NONE;
++ unsigned int io_flags = 0;
++ unsigned long status;
+
-+ /* update the duty cycle for the *next* period */
-+ led = container_of(cdev, struct pwmled, cdev);
-+ pwm_channel_writel(&led->pwmc, PWM_CUPD, led->mult * (unsigned) b);
-+}
++ status = psif_readl(psif, SR);
+
-+/*
-+ * NOTE: we reuse the platform_data structure of GPIO leds,
-+ * but repurpose its "gpio" number as a PWM channel number.
-+ */
-+static int __init pwmled_probe(struct platform_device *pdev)
-+{
-+ const struct gpio_led_platform_data *pdata;
-+ struct pwmled *leds;
-+ unsigned i;
-+ int status;
++ if (status & PSIF_BIT(RXRDY)) {
++ unsigned char val = (unsigned char) psif_readl(psif, RHR);
+
-+ pdata = pdev->dev.platform_data;
-+ if (!pdata || pdata->num_leds < 1)
-+ return -ENODEV;
++ if (status & PSIF_BIT(PARITY))
++ io_flags |= SERIO_PARITY;
++ if (status & PSIF_BIT(OVRUN))
++ dev_err(&psif->pdev->dev, "overrun read error\n");
+
-+ leds = kcalloc(pdata->num_leds, sizeof(*leds), GFP_KERNEL);
-+ if (!leds)
-+ return -ENOMEM;
++ serio_interrupt(psif->io, val, io_flags);
+
-+ for (i = 0; i < pdata->num_leds; i++) {
-+ struct pwmled *led = leds + i;
-+ const struct gpio_led *dat = pdata->leds + i;
-+ u32 tmp;
++ retval = IRQ_HANDLED;
++ }
+
-+ led->cdev.name = dat->name;
-+ led->cdev.brightness = LED_OFF;
-+ led->cdev.brightness_set = pwmled_brightness;
-+ led->cdev.default_trigger = dat->default_trigger;
++ spin_lock(&psif->lock);
+
-+ led->active_low = dat->active_low;
++ if (status & PSIF_BIT(TXEMPTY)) {
++ if (status & PSIF_BIT(NACK))
++ dev_err(&psif->pdev->dev, "NACK error\n");
+
-+ status = pwm_channel_alloc(dat->gpio, &led->pwmc);
-+ if (status < 0)
-+ goto err;
++ psif_writel(psif, IDR, PSIF_BIT(TXEMPTY));
+
-+ /*
-+ * Prescale clock by 2^x, so PWM counts in low MHz.
-+ * Start each cycle with the LED active, so increasing
-+ * the duty cycle gives us more time on (== brighter).
-+ */
-+ tmp = 5;
-+ if (!led->active_low)
-+ tmp |= PWM_CPR_CPOL;
-+ pwm_channel_writel(&led->pwmc, PWM_CMR, tmp);
++ if (!ring_is_empty(psif))
++ mod_timer(&psif->tx_timer,
++ jiffies + msecs_to_jiffies(1));
+
-+ /*
-+ * Pick a period so PWM cycles at 100+ Hz; and a multiplier
-+ * for scaling duty cycle: brightness * mult.
-+ */
-+ tmp = (led->pwmc.mck / (1 << 5)) / 100;
-+ tmp /= 255;
-+ led->mult = tmp;
-+ pwm_channel_writel(&led->pwmc, PWM_CDTY,
-+ led->cdev.brightness * 255);
-+ pwm_channel_writel(&led->pwmc, PWM_CPRD,
-+ LED_FULL * tmp);
-+
-+ pwm_channel_enable(&led->pwmc);
-+
-+ /* Hand it over to the LED framework */
-+ status = led_classdev_register(&pdev->dev, &led->cdev);
-+ if (status < 0) {
-+ pwm_channel_free(&led->pwmc);
-+ goto err;
-+ }
++ retval = IRQ_HANDLED;
+ }
+
-+ platform_set_drvdata(pdev, leds);
-+ return 0;
++ spin_unlock(&psif->lock);
+
-+err:
-+ while (i-- > 0) {
-+ led_classdev_unregister(&leds[i].cdev);
-+ pwm_channel_free(&leds[i].pwmc);
-+ }
-+ kfree(leds);
++ return retval;
++}
++
++static void psif_transmit_data(unsigned long data)
++{
++ struct psif *psif = (struct psif *)data;
++ unsigned long flags;
++
++ spin_lock_irqsave(&psif->lock, flags);
++
++ psif_writel(psif, THR, psif->buffer[psif->tail]);
++ psif->tail = ring_next_tail(psif);
++
++ if (!ring_is_empty(psif))
++ psif_writel(psif, IER, PSIF_BIT(TXEMPTY));
+
-+ return status;
++ spin_unlock_irqrestore(&psif->lock, flags);
+}
+
-+static int __exit pwmled_remove(struct platform_device *pdev)
++static int psif_write(struct serio *io, unsigned char val)
+{
-+ const struct gpio_led_platform_data *pdata;
-+ struct pwmled *leds;
-+ unsigned i;
++ struct psif *psif = io->port_data;
++ unsigned long flags;
++ unsigned int head;
+
-+ pdata = pdev->dev.platform_data;
-+ leds = platform_get_drvdata(pdev);
++ spin_lock_irqsave(&psif->lock, flags);
+
-+ for (i = 0; i < pdata->num_leds; i++) {
-+ struct pwmled *led = leds + i;
++ head = ring_next_head(psif);
+
-+ led_classdev_unregister(&led->cdev);
-+ pwm_channel_free(&led->pwmc);
++ if (head != psif->tail) {
++ psif->buffer[psif->head] = val;
++ psif->head = head;
++ } else {
++ dev_err(&psif->pdev->dev, "underrun write error\n");
+ }
+
-+ kfree(leds);
-+ platform_set_drvdata(pdev, NULL);
-+ return 0;
-+}
++ spin_unlock_irqrestore(&psif->lock, flags);
+
-+static struct platform_driver pwmled_driver = {
-+ .driver = {
-+ .name = "leds-atmel-pwm",
-+ .owner = THIS_MODULE,
-+ },
-+ /* REVISIT add suspend() and resume() methods */
-+ .remove = __exit_p(pwmled_remove),
-+};
++ /* Make sure TXEMPTY interrupt is enabled. */
++ psif_writel(psif, IER, PSIF_BIT(TXEMPTY));
+
-+static int __init modinit(void)
-+{
-+ return platform_driver_probe(&pwmled_driver, pwmled_probe);
++ return 0;
+}
-+module_init(modinit);
+
-+static void __exit modexit(void)
++static int psif_open(struct serio *io)
+{
-+ platform_driver_unregister(&pwmled_driver);
-+}
-+module_exit(modexit);
++ struct psif *psif = io->port_data;
++ int retval;
+
-+MODULE_DESCRIPTION("Driver for LEDs with PWM-controlled brightness");
-+MODULE_LICENSE("GPL");
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -5,6 +5,7 @@
- obj-$(CONFIG_LEDS_TRIGGERS) += led-triggers.o
-
- # LED Platform Drivers
-+obj-$(CONFIG_LEDS_ATMEL_PWM) += leds-atmel-pwm.o
- obj-$(CONFIG_LEDS_CORGI) += leds-corgi.o
- obj-$(CONFIG_LEDS_LOCOMO) += leds-locomo.o
- obj-$(CONFIG_LEDS_SPITZ) += leds-spitz.o
---- /dev/null
-+++ b/drivers/misc/atmel_pwm.c
-@@ -0,0 +1,409 @@
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/interrupt.h>
-+#include <linux/platform_device.h>
-+#include <linux/atmel_pwm.h>
++ retval = clk_enable(psif->pclk);
++ if (retval)
++ goto out;
+
++ psif_writel(psif, CR, PSIF_BIT(CR_TXEN) | PSIF_BIT(CR_RXEN));
++ psif_writel(psif, IER, PSIF_BIT(RXRDY));
+
-+/*
-+ * This is a simple driver for the PWM controller found in various newer
-+ * Atmel SOCs, including the AVR32 series and the AT91sam9263.
-+ *
-+ * Chips with current Linux ports have only 4 PWM channels, out of max 32.
-+ * AT32UC3A and AT32UC3B chips have 7 channels (but currently no Linux).
-+ * Docs are inconsistent about the width of the channel counter registers;
-+ * it's at least 16 bits, but several places say 20 bits.
-+ */
-+#define PWM_NCHAN 4 /* max 32 */
++ psif->open = 1;
++out:
++ return retval;
++}
+
-+struct pwm {
-+ spinlock_t lock;
-+ struct platform_device *pdev;
-+ u32 mask;
-+ int irq;
-+ void __iomem *base;
-+ struct clk *clk;
-+ struct pwm_channel *channel[PWM_NCHAN];
-+ void (*handler[PWM_NCHAN])(struct pwm_channel *);
-+};
++static void psif_close(struct serio *io)
++{
++ struct psif *psif = io->port_data;
+
++ psif->open = 0;
+
-+/* global PWM controller registers */
-+#define PWM_MR 0x00
-+#define PWM_ENA 0x04
-+#define PWM_DIS 0x08
-+#define PWM_SR 0x0c
-+#define PWM_IER 0x10
-+#define PWM_IDR 0x14
-+#define PWM_IMR 0x18
-+#define PWM_ISR 0x1c
++ psif_writel(psif, IDR, ~0UL);
++ psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
+
-+static inline void pwm_writel(const struct pwm *p, unsigned offset, u32 val)
-+{
-+ __raw_writel(val, p->base + offset);
++ clk_disable(psif->pclk);
+}
+
-+static inline u32 pwm_readl(const struct pwm *p, unsigned offset)
++static void psif_set_prescaler(struct psif *psif)
+{
-+ return __raw_readl(p->base + offset);
-+}
++ unsigned long prscv;
++ unsigned long rate = clk_get_rate(psif->pclk);
+
-+static inline void __iomem *pwmc_regs(const struct pwm *p, int index)
-+{
-+ return p->base + 0x200 + index * 0x20;
-+}
++ /* PRSCV = Pulse length (100 us) * PSIF module frequency. */
++ prscv = 100 * (rate / 1000000UL);
+
-+static struct pwm *pwm;
++ if (prscv > ((1<<PSIF_PSR_PRSCV_SIZE) - 1)) {
++ prscv = (1<<PSIF_PSR_PRSCV_SIZE) - 1;
++ dev_dbg(&psif->pdev->dev, "pclk too fast, "
++ "prescaler set to max\n");
++ }
+
-+static void pwm_dumpregs(struct pwm_channel *ch, char *tag)
-+{
-+ struct device *dev = &pwm->pdev->dev;
-+
-+ dev_dbg(dev, "%s: mr %08x, sr %08x, imr %08x\n",
-+ tag,
-+ pwm_readl(pwm, PWM_MR),
-+ pwm_readl(pwm, PWM_SR),
-+ pwm_readl(pwm, PWM_IMR));
-+ dev_dbg(dev,
-+ "pwm ch%d - mr %08x, dty %u, prd %u, cnt %u\n",
-+ ch->index,
-+ pwm_channel_readl(ch, PWM_CMR),
-+ pwm_channel_readl(ch, PWM_CDTY),
-+ pwm_channel_readl(ch, PWM_CPRD),
-+ pwm_channel_readl(ch, PWM_CCNT));
++ clk_enable(psif->pclk);
++ psif_writel(psif, PSR, prscv);
++ clk_disable(psif->pclk);
+}
+
-+
-+/**
-+ * pwm_channel_alloc - allocate an unused PWM channel
-+ * @index: identifies the channel
-+ * @ch: structure to be initialized
-+ *
-+ * Drivers allocate PWM channels according to the board's wiring, and
-+ * matching board-specific setup code. Returns zero or negative errno.
-+ */
-+int pwm_channel_alloc(int index, struct pwm_channel *ch)
++static int __init psif_probe(struct platform_device *pdev)
+{
-+ unsigned long flags;
-+ int status = 0;
-+
-+ /* insist on PWM init, with this signal pinned out */
-+ if (!pwm || !(pwm->mask & 1 << index))
-+ return -ENODEV;
++ struct resource *regs;
++ struct psif *psif;
++ struct serio *io;
++ struct clk *pclk;
++ int irq;
++ int ret;
+
-+ if (index < 0 || index >= PWM_NCHAN || !ch)
-+ return -EINVAL;
-+ memset(ch, 0, sizeof *ch);
++ psif = kzalloc(sizeof(struct psif), GFP_KERNEL);
++ if (!psif) {
++ dev_dbg(&pdev->dev, "out of memory\n");
++ ret = -ENOMEM;
++ goto out;
++ }
++ psif->pdev = pdev;
+
-+ spin_lock_irqsave(&pwm->lock, flags);
-+ if (pwm->channel[index])
-+ status = -EBUSY;
-+ else {
-+ clk_enable(pwm->clk);
++ io = kzalloc(sizeof(struct serio), GFP_KERNEL);
++ if (!io) {
++ dev_dbg(&pdev->dev, "out of memory\n");
++ ret = -ENOMEM;
++ goto out_free_psif;
++ }
++ psif->io = io;
+
-+ ch->regs = pwmc_regs(pwm, index);
-+ ch->index = index;
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!regs) {
++ dev_dbg(&pdev->dev, "no mmio resources defined\n");
++ ret = -ENOMEM;
++ goto out_free_io;
++ }
+
-+ /* REVISIT: ap7000 seems to go 2x as fast as we expect!! */
-+ ch->mck = clk_get_rate(pwm->clk);
++ psif->regs = ioremap(regs->start, regs->end - regs->start + 1);
++ if (!psif->regs) {
++ ret = -ENOMEM;
++ dev_dbg(&pdev->dev, "could not map I/O memory\n");
++ goto out_free_io;
++ }
+
-+ pwm->channel[index] = ch;
-+ pwm->handler[index] = NULL;
++ pclk = clk_get(&pdev->dev, "pclk");
++ if (IS_ERR(pclk)) {
++ dev_dbg(&pdev->dev, "could not get peripheral clock\n");
++ ret = PTR_ERR(pclk);
++ goto out_iounmap;
++ }
++ psif->pclk = pclk;
+
-+ /* channel and irq are always disabled when we return */
-+ pwm_writel(pwm, PWM_DIS, 1 << index);
-+ pwm_writel(pwm, PWM_IDR, 1 << index);
++ /* Reset the PSIF to enter at a known state. */
++ ret = clk_enable(pclk);
++ if (ret) {
++ dev_dbg(&pdev->dev, "could not enable pclk\n");
++ goto out_put_clk;
+ }
-+ spin_unlock_irqrestore(&pwm->lock, flags);
-+ return status;
-+}
-+EXPORT_SYMBOL(pwm_channel_alloc);
++ psif_writel(psif, CR, PSIF_BIT(CR_SWRST));
++ clk_disable(pclk);
+
-+static int pwmcheck(struct pwm_channel *ch)
-+{
-+ int index;
++ setup_timer(&psif->tx_timer, psif_transmit_data, (unsigned long)psif);
+
-+ if (!pwm)
-+ return -ENODEV;
-+ if (!ch)
-+ return -EINVAL;
-+ index = ch->index;
-+ if (index < 0 || index >= PWM_NCHAN || pwm->channel[index] != ch)
-+ return -EINVAL;
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0) {
++ dev_dbg(&pdev->dev, "could not get irq\n");
++ ret = -ENXIO;
++ goto out_put_clk;
++ }
++ ret = request_irq(irq, psif_interrupt, IRQF_SHARED, "at32psif", psif);
++ if (ret) {
++ dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
++ goto out_put_clk;
++ }
++ psif->irq = irq;
+
-+ return index;
-+}
++ io->id.type = SERIO_8042;
++ io->write = psif_write;
++ io->open = psif_open;
++ io->close = psif_close;
++ strlcpy(io->name, pdev->dev.bus_id, sizeof(io->name));
++ strlcpy(io->phys, pdev->dev.bus_id, sizeof(io->phys));
++ io->port_data = psif;
++ io->dev.parent = &pdev->dev;
+
-+/**
-+ * pwm_channel_free - release a previously allocated channel
-+ * @ch: the channel being released
-+ *
-+ * The channel is completely shut down (counter and IRQ disabled),
-+ * and made available for re-use. Returns zero, or negative errno.
-+ */
-+int pwm_channel_free(struct pwm_channel *ch)
-+{
-+ unsigned long flags;
-+ int t;
++ psif_set_prescaler(psif);
++
++ spin_lock_init(&psif->lock);
++ serio_register_port(psif->io);
++ platform_set_drvdata(pdev, psif);
+
-+ spin_lock_irqsave(&pwm->lock, flags);
-+ t = pwmcheck(ch);
-+ if (t >= 0) {
-+ pwm->channel[t] = NULL;
-+ pwm->handler[t] = NULL;
++ dev_info(&pdev->dev, "Atmel AVR32 PSIF PS/2 driver on 0x%08x irq %d\n",
++ (int)psif->regs, psif->irq);
+
-+ /* channel and irq are always disabled when we return */
-+ pwm_writel(pwm, PWM_DIS, 1 << t);
-+ pwm_writel(pwm, PWM_IDR, 1 << t);
++ return 0;
+
-+ clk_disable(pwm->clk);
-+ t = 0;
-+ }
-+ spin_unlock_irqrestore(&pwm->lock, flags);
-+ return t;
++out_put_clk:
++ clk_put(psif->pclk);
++out_iounmap:
++ iounmap(psif->regs);
++out_free_io:
++ kfree(io);
++out_free_psif:
++ kfree(psif);
++out:
++ return ret;
+}
-+EXPORT_SYMBOL(pwm_channel_free);
+
-+int __pwm_channel_onoff(struct pwm_channel *ch, int enabled)
++static int __exit psif_remove(struct platform_device *pdev)
+{
-+ unsigned long flags;
-+ int t;
-+
-+ /* OMITTED FUNCTIONALITY: starting several channels in synch */
-+
-+ spin_lock_irqsave(&pwm->lock, flags);
-+ t = pwmcheck(ch);
-+ if (t >= 0) {
-+ pwm_writel(pwm, enabled ? PWM_ENA : PWM_DIS, 1 << t);
-+ t = 0;
-+ pwm_dumpregs(ch, enabled ? "enable" : "disable");
-+ }
-+ spin_unlock_irqrestore(&pwm->lock, flags);
++ struct psif *psif = platform_get_drvdata(pdev);
+
-+ return t;
-+}
-+EXPORT_SYMBOL(__pwm_channel_onoff);
++ psif_writel(psif, IDR, ~0UL);
++ psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
+
-+/**
-+ * pwm_clk_alloc - allocate and configure CLKA or CLKB
-+ * @prescale: from 0..10, the power of two used to divide MCK
-+ * @div: from 1..255, the linear divisor to use
-+ *
-+ * Returns PWM_CPR_CLKA, PWM_CPR_CLKB, or negative errno. The allocated
-+ * clock will run with a period of (2^prescale * div) / MCK, or twice as
-+ * long if center aligned PWM output is used. The clock must later be
-+ * deconfigured using pwm_clk_free().
-+ */
-+int pwm_clk_alloc(unsigned prescale, unsigned div)
-+{
-+ unsigned long flags;
-+ u32 mr;
-+ u32 val = (prescale << 8) | div;
-+ int ret = -EBUSY;
++ serio_unregister_port(psif->io);
++ iounmap(psif->regs);
++ free_irq(psif->irq, psif);
++ clk_put(psif->pclk);
++ kfree(psif);
+
-+ if (prescale >= 10 || div == 0 || div > 255)
-+ return -EINVAL;
++ platform_set_drvdata(pdev, NULL);
+
-+ spin_lock_irqsave(&pwm->lock, flags);
-+ mr = pwm_readl(pwm, PWM_MR);
-+ if ((mr & 0xffff) == 0) {
-+ mr |= val;
-+ ret = PWM_CPR_CLKA;
-+ }
-+ if ((mr & (0xffff << 16)) == 0) {
-+ mr |= val << 16;
-+ ret = PWM_CPR_CLKB;
-+ }
-+ if (ret > 0)
-+ pwm_writel(pwm, PWM_MR, mr);
-+ spin_unlock_irqrestore(&pwm->lock, flags);
-+ return ret;
++ return 0;
+}
-+EXPORT_SYMBOL(pwm_clk_alloc);
+
-+/**
-+ * pwm_clk_free - deconfigure and release CLKA or CLKB
-+ *
-+ * Reverses the effect of pwm_clk_alloc().
-+ */
-+void pwm_clk_free(unsigned clk)
++#ifdef CONFIG_PM
++static int psif_suspend(struct platform_device *pdev, pm_message_t state)
+{
-+ unsigned long flags;
-+ u32 mr;
-+
-+ spin_lock_irqsave(&pwm->lock, flags);
-+ mr = pwm_readl(pwm, PWM_MR);
-+ if (clk == PWM_CPR_CLKA)
-+ pwm_writel(pwm, PWM_MR, mr & ~(0xffff << 0));
-+ if (clk == PWM_CPR_CLKB)
-+ pwm_writel(pwm, PWM_MR, mr & ~(0xffff << 16));
-+ spin_unlock_irqrestore(&pwm->lock, flags);
-+}
-+EXPORT_SYMBOL(pwm_clk_free);
++ struct psif *psif = platform_get_drvdata(pdev);
+
-+/**
-+ * pwm_channel_handler - manage channel's IRQ handler
-+ * @ch: the channel
-+ * @handler: the handler to use, possibly NULL
-+ *
-+ * If the handler is non-null, the handler will be called after every
-+ * period of this PWM channel. If the handler is null, this channel
-+ * won't generate an IRQ.
-+ */
-+int pwm_channel_handler(struct pwm_channel *ch,
-+ void (*handler)(struct pwm_channel *ch))
-+{
-+ unsigned long flags;
-+ int t;
-+
-+ spin_lock_irqsave(&pwm->lock, flags);
-+ t = pwmcheck(ch);
-+ if (t >= 0) {
-+ pwm->handler[t] = handler;
-+ pwm_writel(pwm, handler ? PWM_IER : PWM_IDR, 1 << t);
-+ t = 0;
++ if (psif->open) {
++ psif_writel(psif, CR, PSIF_BIT(CR_RXDIS) | PSIF_BIT(CR_TXDIS));
++ clk_disable(psif->pclk);
+ }
-+ spin_unlock_irqrestore(&pwm->lock, flags);
+
-+ return t;
++ return 0;
+}
-+EXPORT_SYMBOL(pwm_channel_handler);
+
-+static irqreturn_t pwm_irq(int id, void *_pwm)
++static int psif_resume(struct platform_device *pdev)
+{
-+ struct pwm *p = _pwm;
-+ irqreturn_t handled = IRQ_NONE;
-+ u32 irqstat;
-+ int index;
-+
-+ spin_lock(&p->lock);
-+
-+ /* ack irqs, then handle them */
-+ irqstat = pwm_readl(pwm, PWM_ISR);
-+
-+ while (irqstat) {
-+ struct pwm_channel *ch;
-+ void (*handler)(struct pwm_channel *ch);
-+
-+ index = ffs(irqstat) - 1;
-+ irqstat &= ~(1 << index);
-+ ch = pwm->channel[index];
-+ handler = pwm->handler[index];
-+ if (handler && ch) {
-+ spin_unlock(&p->lock);
-+ handler(ch);
-+ spin_lock(&p->lock);
-+ handled = IRQ_HANDLED;
-+ }
++ struct psif *psif = platform_get_drvdata(pdev);
++
++ if (psif->open) {
++ clk_enable(psif->pclk);
++ psif_set_prescaler(psif);
++ psif_writel(psif, CR, PSIF_BIT(CR_RXEN) | PSIF_BIT(CR_TXEN));
+ }
+
-+ spin_unlock(&p->lock);
-+ return handled;
++ return 0;
+}
++#else
++#define psif_suspend NULL
++#define psif_resume NULL
++#endif
+
-+static int __init pwm_probe(struct platform_device *pdev)
-+{
-+ struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ int irq = platform_get_irq(pdev, 0);
-+ u32 *mp = pdev->dev.platform_data;
-+ struct pwm *p;
-+ int status = -EIO;
-+
-+ if (pwm)
-+ return -EBUSY;
-+ if (!r || irq < 0 || !mp || !*mp)
-+ return -ENODEV;
-+ if (*mp & ~((1<<PWM_NCHAN)-1)) {
-+ dev_warn(&pdev->dev, "mask 0x%x ... more than %d channels\n",
-+ *mp, PWM_NCHAN);
-+ return -EINVAL;
-+ }
++static struct platform_driver psif_driver = {
++ .remove = __exit_p(psif_remove),
++ .driver = {
++ .name = "atmel_psif",
++ },
++ .suspend = psif_suspend,
++ .resume = psif_resume,
++};
+
-+ p = kzalloc(sizeof(*p), GFP_KERNEL);
-+ if (!p)
-+ return -ENOMEM;
++static int __init psif_init(void)
++{
++ return platform_driver_probe(&psif_driver, psif_probe);
++}
+
-+ spin_lock_init(&p->lock);
-+ p->pdev = pdev;
-+ p->mask = *mp;
-+ p->irq = irq;
-+ p->base = ioremap(r->start, r->end - r->start + 1);
-+ if (!p->base)
-+ goto fail;
-+ p->clk = clk_get(&pdev->dev, "mck");
-+ if (IS_ERR(p->clk)) {
-+ status = PTR_ERR(p->clk);
-+ p->clk = NULL;
-+ goto fail;
-+ }
++static void __exit psif_exit(void)
++{
++ platform_driver_unregister(&psif_driver);
++}
+
-+ status = request_irq(irq, pwm_irq, 0, pdev->name, p);
-+ if (status < 0)
-+ goto fail;
++module_init(psif_init);
++module_exit(psif_exit);
+
-+ pwm = p;
-+ platform_set_drvdata(pdev, p);
++MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
++MODULE_DESCRIPTION("Atmel AVR32 PSIF PS/2 driver");
++MODULE_LICENSE("GPL");
+--- /dev/null
++++ b/drivers/input/serio/at32psif.h
+@@ -0,0 +1,82 @@
++/*
++ * Copyright (C) 2007 Atmel Corporation
++ *
++ * Driver for the AT32AP700X PS/2 controller (PSIF).
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
+
-+ return 0;
++#ifndef _AT32PSIF_H
++#define _AT32PSIF_H
+
-+fail:
-+ if (p->clk)
-+ clk_put(p->clk);
-+ if (p->base)
-+ iounmap(p->base);
++/* PSIF register offsets */
++#define PSIF_CR 0x00
++#define PSIF_RHR 0x04
++#define PSIF_THR 0x08
++#define PSIF_SR 0x10
++#define PSIF_IER 0x14
++#define PSIF_IDR 0x18
++#define PSIF_IMR 0x1c
++#define PSIF_PSR 0x24
+
-+ kfree(p);
-+ return status;
-+}
++/* Bitfields in control register. */
++#define PSIF_CR_RXDIS_OFFSET 1
++#define PSIF_CR_RXDIS_SIZE 1
++#define PSIF_CR_RXEN_OFFSET 0
++#define PSIF_CR_RXEN_SIZE 1
++#define PSIF_CR_SWRST_OFFSET 15
++#define PSIF_CR_SWRST_SIZE 1
++#define PSIF_CR_TXDIS_OFFSET 9
++#define PSIF_CR_TXDIS_SIZE 1
++#define PSIF_CR_TXEN_OFFSET 8
++#define PSIF_CR_TXEN_SIZE 1
+
-+static int __exit pwm_remove(struct platform_device *pdev)
-+{
-+ struct pwm *p = platform_get_drvdata(pdev);
++/* Bitfields in interrupt disable, enable, mask and status register. */
++#define PSIF_NACK_OFFSET 8
++#define PSIF_NACK_SIZE 1
++#define PSIF_OVRUN_OFFSET 5
++#define PSIF_OVRUN_SIZE 1
++#define PSIF_PARITY_OFFSET 9
++#define PSIF_PARITY_SIZE 1
++#define PSIF_RXRDY_OFFSET 4
++#define PSIF_RXRDY_SIZE 1
++#define PSIF_TXEMPTY_OFFSET 1
++#define PSIF_TXEMPTY_SIZE 1
++#define PSIF_TXRDY_OFFSET 0
++#define PSIF_TXRDY_SIZE 1
+
-+ if (p != pwm)
-+ return -EINVAL;
++/* Bitfields in prescale register. */
++#define PSIF_PSR_PRSCV_OFFSET 0
++#define PSIF_PSR_PRSCV_SIZE 12
+
-+ clk_enable(pwm->clk);
-+ pwm_writel(pwm, PWM_DIS, (1 << PWM_NCHAN) - 1);
-+ pwm_writel(pwm, PWM_IDR, (1 << PWM_NCHAN) - 1);
-+ clk_disable(pwm->clk);
++/* Bitfields in receive hold register. */
++#define PSIF_RHR_RXDATA_OFFSET 0
++#define PSIF_RHR_RXDATA_SIZE 8
+
-+ pwm = NULL;
++/* Bitfields in transmit hold register. */
++#define PSIF_THR_TXDATA_OFFSET 0
++#define PSIF_THR_TXDATA_SIZE 8
+
-+ free_irq(p->irq, p);
-+ clk_put(p->clk);
-+ iounmap(p->base);
-+ kfree(p);
++/* Bit manipulation macros */
++#define PSIF_BIT(name) \
++ (1 << PSIF_##name##_OFFSET)
++#define PSIF_BF(name, value) \
++ (((value) & ((1 << PSIF_##name##_SIZE) - 1)) \
++ << PSIF_##name##_OFFSET)
++#define PSIF_BFEXT(name, value)\
++ (((value) >> PSIF_##name##_OFFSET) \
++ & ((1 << PSIF_##name##_SIZE) - 1))
++#define PSIF_BFINS(name, value, old) \
++ (((old) & ~(((1 << PSIF_##name##_SIZE) - 1) \
++ << PSIF_##name##_OFFSET)) \
++ | PSIF_BF(name, value))
+
-+ return 0;
-+}
++/* Register access macros */
++#define psif_readl(port, reg) \
++ __raw_readl((port)->regs + PSIF_##reg)
++#define psif_writel(port, reg, value) \
++ __raw_writel((value), (port)->regs + PSIF_##reg)
+
-+static struct platform_driver atmel_pwm_driver = {
-+ .driver = {
-+ .name = "atmel_pwm",
-+ .owner = THIS_MODULE,
-+ },
-+ .remove = __exit_p(pwm_remove),
++#endif /* _AT32PSIF_H */
+--- a/drivers/misc/Kconfig
++++ b/drivers/misc/Kconfig
+@@ -22,6 +22,39 @@
+ purposes including software controlled power-efficent backlights
+ on LCD displays, motor control, and waveform generation.
+
++config ATMEL_TCLIB
++ bool "Atmel AT32/AT91 Timer/Counter Library"
++ depends on (AVR32 || ARCH_AT91)
++ help
++ Select this if you want a library to allocate the Timer/Counter
++ blocks found on many Atmel processors. This facilitates using
++ these blocks by different drivers despite processor differences.
+
-+ /* NOTE: PWM can keep running in AVR32 "idle" and "frozen" states;
-+ * and all AT91sam9263 states, albeit at reduced clock rate if
-+ * MCK becomes the slow clock (i.e. what Linux labels STR).
-+ */
-+};
++config ATMEL_TCB_CLKSRC
++ bool "TC Block Clocksource"
++ depends on ATMEL_TCLIB && GENERIC_TIME
++ default y
++ help
++ Select this to get a high precision clocksource based on a
++ TC block with a 5+ MHz base clock rate. Two timer channels
++ are combined to make a single 32-bit timer.
+
-+static int __init pwm_init(void)
-+{
-+ return platform_driver_probe(&atmel_pwm_driver, pwm_probe);
-+}
-+module_init(pwm_init);
++ When GENERIC_CLOCKEVENTS is defined, the third timer channel
++ may be used as a clock event device supporting oneshot mode
++ (delays of up to two seconds) based on the 32 KiHz clock.
+
-+static void __exit pwm_exit(void)
-+{
-+ platform_driver_unregister(&atmel_pwm_driver);
-+}
-+module_exit(pwm_exit);
++config ATMEL_TCB_CLKSRC_BLOCK
++ int
++ depends on ATMEL_TCB_CLKSRC
++ prompt "TC Block" if ARCH_AT91RM9200 || ARCH_AT91SAM9260 || CPU_AT32AP700X
++ default 0
++ range 0 1
++ help
++ Some chips provide more than one TC block, so you have the
++ choice of which one to use for the clock framework. The other
++ TC can be used for other purposes, such as PWM generation and
++ interval timing.
+
-+MODULE_DESCRIPTION("Driver for AT32/AT91 PWM module");
-+MODULE_LICENSE("GPL");
+ config IBM_ASM
+ tristate "Device driver for IBM RSA service processor"
+ depends on X86 && PCI && INPUT && EXPERIMENTAL
+--- a/drivers/misc/Makefile
++++ b/drivers/misc/Makefile
+@@ -10,6 +10,7 @@
+ obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
+ obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
+ obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
++obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
+ obj-$(CONFIG_TC1100_WMI) += tc1100-wmi.o
+ obj-$(CONFIG_LKDTM) += lkdtm.o
+ obj-$(CONFIG_TIFM_CORE) += tifm_core.o
--- /dev/null
+++ b/drivers/misc/atmel_tclib.c
@@ -0,0 +1,161 @@
+ return platform_driver_probe(&tc_driver, tc_probe);
+}
+arch_initcall(tc_init);
---- a/drivers/misc/Kconfig
-+++ b/drivers/misc/Kconfig
-@@ -13,6 +13,48 @@
+--- a/drivers/mmc/host/Kconfig
++++ b/drivers/mmc/host/Kconfig
+@@ -91,6 +91,16 @@
- if MISC_DEVICES
+ If unsure, say N.
-+config ATMEL_PWM
-+ tristate "Atmel AT32/AT91 PWM support"
-+ depends on AVR32 || ARCH_AT91
-+ help
-+ This option enables device driver support for the PWM channels
-+ on certain Atmel prcoessors. Pulse Width Modulation is used for
-+ purposes including software controlled power-efficent backlights
-+ on LCD displays, motor control, and waveform generation.
-+
-+config ATMEL_TCLIB
-+ bool "Atmel AT32/AT91 Timer/Counter Library"
-+ depends on (AVR32 || ARCH_AT91)
-+ help
-+ Select this if you want a library to allocate the Timer/Counter
-+ blocks found on many Atmel processors. This facilitates using
-+ these blocks by different drivers despite processor differences.
-+
-+config ATMEL_TCB_CLKSRC
-+ bool "TC Block Clocksource"
-+ depends on ATMEL_TCLIB && GENERIC_TIME
-+ default y
++config MMC_ATMELMCI
++ tristate "Atmel Multimedia Card Interface support"
++ depends on AVR32 && MMC
+ help
-+ Select this to get a high precision clocksource based on a
-+ TC block with a 5+ MHz base clock rate. Two timer channels
-+ are combined to make a single 32-bit timer.
-+
-+ When GENERIC_CLOCKEVENTS is defined, the third timer channel
-+ may be used as a clock event device supporting oneshot mode
-+ (delays of up to two seconds) based on the 32 KiHz clock.
++ This selects the Atmel Multimedia Card Interface. If you have
++ a AT91 (ARM) or AT32 (AVR32) platform with a Multimedia Card
++ slot, say Y or M here.
+
-+config ATMEL_TCB_CLKSRC_BLOCK
-+ int
-+ depends on ATMEL_TCB_CLKSRC
-+ prompt "TC Block" if ARCH_AT91RM9200 || ARCH_AT91SAM9260 || CPU_AT32AP700X
-+ default 0
-+ range 0 1
-+ help
-+ Some chips provide more than one TC block, so you have the
-+ choice of which one to use for the clock framework. The other
-+ TC can be used for other purposes, such as PWM generation and
-+ interval timing.
++ If unsure, say N.
+
- config IBM_ASM
- tristate "Device driver for IBM RSA service processor"
- depends on X86 && PCI && INPUT && EXPERIMENTAL
---- a/drivers/misc/Makefile
-+++ b/drivers/misc/Makefile
-@@ -7,7 +7,9 @@
- obj-$(CONFIG_HDPU_FEATURES) += hdpuftrs/
- obj-$(CONFIG_MSI_LAPTOP) += msi-laptop.o
- obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
-+obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
- obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
-+obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
- obj-$(CONFIG_LKDTM) += lkdtm.o
- obj-$(CONFIG_TIFM_CORE) += tifm_core.o
- obj-$(CONFIG_TIFM_7XX1) += tifm_7xx1.o
+ config MMC_IMX
+ tristate "Motorola i.MX Multimedia Card Interface support"
+ depends on ARCH_IMX
+--- a/drivers/mmc/host/Makefile
++++ b/drivers/mmc/host/Makefile
+@@ -15,6 +15,7 @@
+ obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
+ obj-$(CONFIG_MMC_OMAP) += omap.o
+ obj-$(CONFIG_MMC_AT91) += at91_mci.o
++obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
+ obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
+ obj-$(CONFIG_MMC_SPI) += mmc_spi.o
+ obj-$(CONFIG_GPIOMMC) += gpiommc.o
--- /dev/null
+++ b/drivers/mmc/host/atmel-mci.c
-@@ -0,0 +1,1220 @@
+@@ -0,0 +1,1234 @@
+/*
+ * Atmel MultiMedia Card Interface driver
+ *
+ struct clk *mck;
+ struct platform_device *pdev;
+
++ int pending_stop;
+#ifdef CONFIG_DEBUG_FS
+ struct dentry *debugfs_root;
+ struct dentry *debugfs_regs;
+ data->bytes_xfered = data->blocks * data->blksz;
+ atmci_data_complete(host, data);
+ }
++ /* See if there is a pending STOP which can be sent */
++ if (host->pending_stop && mci_cmd_is_complete(host)) {
++ host->pending_stop = 0;
++ if (mrq->stop && !mci_set_stop_sent_is_completed(host))
++ send_stop_cmd(host->mmc, mrq->data, 0);
++ }
+}
+
+static void atmci_cmd_interrupt(struct mmc_host *mmc, u32 status)
+ * drivers) or when interrupts are disabled for a long time.
+ */
+ mci_set_dma_complete(host);
-+ if (data->stop && mci_cmd_is_complete(host)
-+ && !mci_set_stop_sent_is_completed(host))
-+ send_stop_cmd(host->mmc, data, 0);
++
++ if (data->stop) {
++ if (!mci_cmd_is_complete(host)) {
++ /* Just remember a STOP must be sent */
++ host->pending_stop = 1;
++ } else if (!mci_set_stop_sent_is_completed(host)) {
++ send_stop_cmd(host->mmc, data, 0);
++ host->pending_stop = 0;
++ }
++ }
+
+ /*
+ * Regardless of what the documentation says, we have to wait
+ __raw_writel((value), (port)->regs + MCI_##reg)
+
+#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
---- a/drivers/mmc/host/Kconfig
-+++ b/drivers/mmc/host/Kconfig
-@@ -91,6 +91,16 @@
-
- If unsure, say N.
-
-+config MMC_ATMELMCI
-+ tristate "Atmel Multimedia Card Interface support"
-+ depends on AVR32 && MMC
+--- a/drivers/mtd/nand/Kconfig
++++ b/drivers/mtd/nand/Kconfig
+@@ -272,12 +272,54 @@
+
+ If you say "m", the module will be called "cs553x_nand.ko".
+
+-config MTD_NAND_AT91
+- bool "Support for NAND Flash / SmartMedia on AT91"
+- depends on ARCH_AT91
++config MTD_NAND_ATMEL
++ bool "Support for NAND Flash / SmartMedia on AT91 and AVR32"
++ depends on ARCH_AT91 || AVR32
+ help
+ Enables support for NAND Flash / Smart Media Card interface
+- on Atmel AT91 processors.
++ on Atmel AT91 and AVR32 processors.
++choice
++ prompt "ECC management for NAND Flash / SmartMedia on AT91 / AVR32"
++ depends on MTD_NAND_ATMEL
++
++config MTD_NAND_ATMEL_ECC_HW
++ bool "Hardware ECC"
++ depends on ARCH_AT91SAM9263 || ARCH_AT91SAM9260 || AVR32
+ help
-+ This selects the Atmel Multimedia Card Interface. If you have
-+ a AT91 (ARM) or AT32 (AVR32) platform with a Multimedia Card
-+ slot, say Y or M here.
++ Use hardware ECC instead of software ECC when the chip
++ supports it.
+
-+ If unsure, say N.
++ The hardware ECC controller is capable of single bit error
++ correction and 2-bit random detection per page.
+
- config MMC_IMX
- tristate "Motorola i.MX Multimedia Card Interface support"
- depends on ARCH_IMX
---- a/drivers/mmc/host/Makefile
-+++ b/drivers/mmc/host/Makefile
-@@ -15,6 +15,7 @@
- obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
- obj-$(CONFIG_MMC_OMAP) += omap.o
- obj-$(CONFIG_MMC_AT91) += at91_mci.o
-+obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o
- obj-$(CONFIG_MMC_TIFM_SD) += tifm_sd.o
- obj-$(CONFIG_MMC_SPI) += mmc_spi.o
-
---- a/drivers/mtd/chips/cfi_cmdset_0001.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0001.c
-@@ -50,6 +50,7 @@
- #define I82802AC 0x00ac
- #define MANUFACTURER_ST 0x0020
- #define M50LPW080 0x002F
-+#define AT49BV640D 0x02de
-
- static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
- static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
-@@ -157,6 +158,47 @@
- }
- #endif
-
-+/* Atmel chips don't use the same PRI format as Intel chips */
-+static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
-+{
-+ struct map_info *map = mtd->priv;
-+ struct cfi_private *cfi = map->fldrv_priv;
-+ struct cfi_pri_intelext *extp = cfi->cmdset_priv;
-+ struct cfi_pri_atmel atmel_pri;
-+ uint32_t features = 0;
-+
-+ /* Reverse byteswapping */
-+ extp->FeatureSupport = cpu_to_le32(extp->FeatureSupport);
-+ extp->BlkStatusRegMask = cpu_to_le16(extp->BlkStatusRegMask);
-+ extp->ProtRegAddr = cpu_to_le16(extp->ProtRegAddr);
-+
-+ memcpy(&atmel_pri, extp, sizeof(atmel_pri));
-+ memset((char *)extp + 5, 0, sizeof(*extp) - 5);
-+
-+ printk(KERN_ERR "atmel Features: %02x\n", atmel_pri.Features);
-+
-+ if (atmel_pri.Features & 0x01) /* chip erase supported */
-+ features |= (1<<0);
-+ if (atmel_pri.Features & 0x02) /* erase suspend supported */
-+ features |= (1<<1);
-+ if (atmel_pri.Features & 0x04) /* program suspend supported */
-+ features |= (1<<2);
-+ if (atmel_pri.Features & 0x08) /* simultaneous operations supported */
-+ features |= (1<<9);
-+ if (atmel_pri.Features & 0x20) /* page mode read supported */
-+ features |= (1<<7);
-+ if (atmel_pri.Features & 0x40) /* queued erase supported */
-+ features |= (1<<4);
-+ if (atmel_pri.Features & 0x80) /* Protection bits supported */
-+ features |= (1<<6);
-+
-+ extp->FeatureSupport = features;
-+
-+ /* burst write mode not supported */
-+ cfi->cfiq->BufWriteTimeoutTyp = 0;
-+ cfi->cfiq->BufWriteTimeoutMax = 0;
-+}
++ NB : hardware and software ECC schemes are incompatible.
++ If you switch from one to another, you'll have to erase your
++ mtd partition.
+
- #ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
- /* Some Intel Strata Flash prior to FPO revision C has bugs in this area */
- static void fixup_intel_strataflash(struct mtd_info *mtd, void* param)
-@@ -234,6 +276,7 @@
- }
-
- static struct cfi_fixup cfi_fixup_table[] = {
-+ { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
- #ifdef CMDSET0001_DISABLE_ERASE_SUSPEND_ON_WRITE
- { CFI_MFR_ANY, CFI_ID_ANY, fixup_intel_strataflash, NULL },
- #endif
---- a/drivers/mtd/chips/cfi_cmdset_0002.c
-+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
-@@ -186,6 +186,10 @@
- extp->TopBottom = 2;
- else
- extp->TopBottom = 3;
-+
-+ /* burst write mode not supported */
-+ cfi->cfiq->BufWriteTimeoutTyp = 0;
-+ cfi->cfiq->BufWriteTimeoutMax = 0;
- }
-
- static void fixup_use_secsi(struct mtd_info *mtd, void *param)
-@@ -218,6 +222,7 @@
- }
++ If unsure, say Y
++
++config MTD_NAND_ATMEL_ECC_SOFT
++ bool "Software ECC"
++ help
++ Use software ECC.
++
++ NB : hardware and software ECC schemes are incompatible.
++ If you switch from one to another, you'll have to erase your
++ mtd partition.
++
++config MTD_NAND_ATMEL_ECC_NONE
++ bool "No ECC (testing only, DANGEROUS)"
++ depends on DEBUG_KERNEL
++ help
++ No ECC will be used.
++ It's not a good idea and it should be reserved for testing
++ purpose only.
++
++ If unsure, say N
++
++ endchoice
++
++endchoice
- static struct cfi_fixup cfi_fixup_table[] = {
-+ { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
- #ifdef AMD_BOOTLOC_BUG
- { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
- #endif
-@@ -230,7 +235,6 @@
- #if !FORCE_WORD_WRITE
- { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
- #endif
-- { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
- { 0, 0, NULL, NULL }
- };
- static struct cfi_fixup jedec_fixup_table[] = {
+ config MTD_NAND_CM_X270
+ tristate "Support for NAND Flash on CM-X270 modules"
+--- a/drivers/mtd/nand/Makefile
++++ b/drivers/mtd/nand/Makefile
+@@ -24,7 +24,7 @@
+ obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o
+ obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o
+ obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o
+-obj-$(CONFIG_MTD_NAND_AT91) += at91_nand.o
++obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o
+ obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
+ obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o
+ obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
+--- a/drivers/mtd/nand/at91_nand.c
++++ /dev/null
+@@ -1,236 +0,0 @@
+-/*
+- * drivers/mtd/nand/at91_nand.c
+- *
+- * Copyright (C) 2003 Rick Bronson
+- *
+- * Derived from drivers/mtd/nand/autcpu12.c
+- * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
+- *
+- * Derived from drivers/mtd/spia.c
+- * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
+- *
+- * This program is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License version 2 as
+- * published by the Free Software Foundation.
+- *
+- */
+-
+-#include <linux/slab.h>
+-#include <linux/module.h>
+-#include <linux/platform_device.h>
+-#include <linux/mtd/mtd.h>
+-#include <linux/mtd/nand.h>
+-#include <linux/mtd/partitions.h>
+-
+-#include <asm/io.h>
+-#include <asm/sizes.h>
+-
+-#include <asm/hardware.h>
+-#include <asm/arch/board.h>
+-#include <asm/arch/gpio.h>
+-
+-struct at91_nand_host {
+- struct nand_chip nand_chip;
+- struct mtd_info mtd;
+- void __iomem *io_base;
+- struct at91_nand_data *board;
+-};
+-
+-/*
+- * Hardware specific access to control-lines
+- */
+-static void at91_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+-{
+- struct nand_chip *nand_chip = mtd->priv;
+- struct at91_nand_host *host = nand_chip->priv;
+-
+- if (cmd == NAND_CMD_NONE)
+- return;
+-
+- if (ctrl & NAND_CLE)
+- writeb(cmd, host->io_base + (1 << host->board->cle));
+- else
+- writeb(cmd, host->io_base + (1 << host->board->ale));
+-}
+-
+-/*
+- * Read the Device Ready pin.
+- */
+-static int at91_nand_device_ready(struct mtd_info *mtd)
+-{
+- struct nand_chip *nand_chip = mtd->priv;
+- struct at91_nand_host *host = nand_chip->priv;
+-
+- return at91_get_gpio_value(host->board->rdy_pin);
+-}
+-
+-/*
+- * Enable NAND.
+- */
+-static void at91_nand_enable(struct at91_nand_host *host)
+-{
+- if (host->board->enable_pin)
+- at91_set_gpio_value(host->board->enable_pin, 0);
+-}
+-
+-/*
+- * Disable NAND.
+- */
+-static void at91_nand_disable(struct at91_nand_host *host)
+-{
+- if (host->board->enable_pin)
+- at91_set_gpio_value(host->board->enable_pin, 1);
+-}
+-
+-#ifdef CONFIG_MTD_PARTITIONS
+-const char *part_probes[] = { "cmdlinepart", NULL };
+-#endif
+-
+-/*
+- * Probe for the NAND device.
+- */
+-static int __init at91_nand_probe(struct platform_device *pdev)
+-{
+- struct at91_nand_host *host;
+- struct mtd_info *mtd;
+- struct nand_chip *nand_chip;
+- int res;
+-
+-#ifdef CONFIG_MTD_PARTITIONS
+- struct mtd_partition *partitions = NULL;
+- int num_partitions = 0;
+-#endif
+-
+- /* Allocate memory for the device structure (and zero it) */
+- host = kzalloc(sizeof(struct at91_nand_host), GFP_KERNEL);
+- if (!host) {
+- printk(KERN_ERR "at91_nand: failed to allocate device structure.\n");
+- return -ENOMEM;
+- }
+-
+- host->io_base = ioremap(pdev->resource[0].start,
+- pdev->resource[0].end - pdev->resource[0].start + 1);
+- if (host->io_base == NULL) {
+- printk(KERN_ERR "at91_nand: ioremap failed\n");
+- kfree(host);
+- return -EIO;
+- }
+-
+- mtd = &host->mtd;
+- nand_chip = &host->nand_chip;
+- host->board = pdev->dev.platform_data;
+-
+- nand_chip->priv = host; /* link the private data structures */
+- mtd->priv = nand_chip;
+- mtd->owner = THIS_MODULE;
+-
+- /* Set address of NAND IO lines */
+- nand_chip->IO_ADDR_R = host->io_base;
+- nand_chip->IO_ADDR_W = host->io_base;
+- nand_chip->cmd_ctrl = at91_nand_cmd_ctrl;
+-
+- if (host->board->rdy_pin)
+- nand_chip->dev_ready = at91_nand_device_ready;
+-
+- nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
+- nand_chip->chip_delay = 20; /* 20us command delay time */
+-
+- if (host->board->bus_width_16) /* 16-bit bus width */
+- nand_chip->options |= NAND_BUSWIDTH_16;
+-
+- platform_set_drvdata(pdev, host);
+- at91_nand_enable(host);
+-
+- if (host->board->det_pin) {
+- if (at91_get_gpio_value(host->board->det_pin)) {
+- printk ("No SmartMedia card inserted.\n");
+- res = ENXIO;
+- goto out;
+- }
+- }
+-
+- /* Scan to find existance of the device */
+- if (nand_scan(mtd, 1)) {
+- res = -ENXIO;
+- goto out;
+- }
+-
+-#ifdef CONFIG_MTD_PARTITIONS
+-#ifdef CONFIG_MTD_CMDLINE_PARTS
+- mtd->name = "at91_nand";
+- num_partitions = parse_mtd_partitions(mtd, part_probes,
+- &partitions, 0);
+-#endif
+- if (num_partitions <= 0 && host->board->partition_info)
+- partitions = host->board->partition_info(mtd->size,
+- &num_partitions);
+-
+- if ((!partitions) || (num_partitions == 0)) {
+- printk(KERN_ERR "at91_nand: No parititions defined, or unsupported device.\n");
+- res = ENXIO;
+- goto release;
+- }
+-
+- res = add_mtd_partitions(mtd, partitions, num_partitions);
+-#else
+- res = add_mtd_device(mtd);
+-#endif
+-
+- if (!res)
+- return res;
+-
+-release:
+- nand_release(mtd);
+-out:
+- at91_nand_disable(host);
+- platform_set_drvdata(pdev, NULL);
+- iounmap(host->io_base);
+- kfree(host);
+- return res;
+-}
+-
+-/*
+- * Remove a NAND device.
+- */
+-static int __devexit at91_nand_remove(struct platform_device *pdev)
+-{
+- struct at91_nand_host *host = platform_get_drvdata(pdev);
+- struct mtd_info *mtd = &host->mtd;
+-
+- nand_release(mtd);
+-
+- at91_nand_disable(host);
+-
+- iounmap(host->io_base);
+- kfree(host);
+-
+- return 0;
+-}
+-
+-static struct platform_driver at91_nand_driver = {
+- .probe = at91_nand_probe,
+- .remove = at91_nand_remove,
+- .driver = {
+- .name = "at91_nand",
+- .owner = THIS_MODULE,
+- },
+-};
+-
+-static int __init at91_nand_init(void)
+-{
+- return platform_driver_register(&at91_nand_driver);
+-}
+-
+-
+-static void __exit at91_nand_exit(void)
+-{
+- platform_driver_unregister(&at91_nand_driver);
+-}
+-
+-
+-module_init(at91_nand_init);
+-module_exit(at91_nand_exit);
+-
+-MODULE_LICENSE("GPL");
+-MODULE_AUTHOR("Rick Bronson");
+-MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91RM9200");
--- /dev/null
-+++ b/drivers/pcmcia/at32_cf.c
-@@ -0,0 +1,533 @@
++++ b/drivers/mtd/nand/atmel_nand.c
+@@ -0,0 +1,650 @@
+/*
-+ * Driver for AVR32 Static Memory Controller: CompactFlash support
++ * Copyright (C) 2003 Rick Bronson
+ *
-+ * Copyright (C) 2006 Atmel Norway
++ * Derived from drivers/mtd/nand/autcpu12.c
++ * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of the
-+ * License, or (at your option) any later version.
++ * Derived from drivers/mtd/spia.c
++ * Copyright (C) 2000 Steven J. Hill (sjhill@cotw.com)
+ *
-+ * This program is distributed in the hope that it will be useful, but
-+ * WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-+ * General Public License for more details.
+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-+ * 02111-1307, USA.
++ * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
++ * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright (C) 2007
++ *
++ * Derived from Das U-Boot source code
++ * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
++ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
++ *
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
+ *
-+ * The full GNU General Public License is included in this
-+ * distribution in the file called COPYING.
+ */
++
++#include <linux/slab.h>
+#include <linux/module.h>
-+#include <linux/kernel.h>
+#include <linux/platform_device.h>
-+#include <linux/init.h>
-+#include <linux/device.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/err.h>
-+#include <linux/clk.h>
-+#include <linux/dma-mapping.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/mtd/partitions.h>
+
-+#include <pcmcia/ss.h>
++#include <linux/gpio.h>
++#include <linux/io.h>
+
-+#include <asm/gpio.h>
-+#include <asm/io.h>
+#include <asm/arch/board.h>
++#include <asm/arch/cpu.h>
+
-+#include <asm/arch/smc.h>
-+
-+struct at32_cf_socket {
-+ struct pcmcia_socket socket;
-+ int detect_pin;
-+ int reset_pin;
-+ int vcc_pin;
-+ int ready_pin;
-+ struct resource res_attr;
-+ struct resource res_mem;
-+ struct resource res_io;
-+ struct smc_config smc;
-+ unsigned int irq;
-+ unsigned int cf_cs;
-+ socket_state_t state;
-+ unsigned present:1;
-+};
-+#define to_at32_cf(sock) container_of(sock, struct at32_cf_socket, socket)
-+
-+/*
-+ * We have the following memory layout relative to the base address:
-+ *
-+ * Alt IDE Mode: 00e0 0000 -> 00ff ffff
-+ * True IDE Mode: 00c0 0000 -> 00df ffff
-+ * I/O memory: 0080 0000 -> 00bf ffff
-+ * Common memory: 0040 0000 -> 007f ffff
-+ * Attribute memory: 0000 0000 -> 003f ffff
-+ */
-+#define CF_ATTR_OFFSET 0x00000000
-+#define CF_MEM_OFFSET 0x00400000
-+#define CF_IO_OFFSET 0x00800000
-+#define CF_RES_SIZE 4096
++#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW
++#define hard_ecc 1
++#else
++#define hard_ecc 0
++#endif
+
-+#ifdef DEBUG
++#ifdef CONFIG_MTD_NAND_ATMEL_ECC_NONE
++#define no_ecc 1
++#else
++#define no_ecc 0
++#endif
+
-+static int pc_debug;
-+module_param(pc_debug, int, 0644);
++/* Register access macros */
++#define ecc_readl(add, reg) \
++ __raw_readl(add + ATMEL_ECC_##reg)
++#define ecc_writel(add, reg, value) \
++ __raw_writel((value), add + ATMEL_ECC_##reg)
+
-+static void at32_cf_debug(struct at32_cf_socket *cf, const char *func,
-+ int level, const char *fmt, ...)
-+{
-+ va_list args;
++#include "atmel_nand_ecc.h" /* Hardware ECC registers */
+
-+ if (pc_debug > level) {
-+ printk(KERN_DEBUG "at32_cf/%u: %s: ", cf->cf_cs, func);
-+ va_start(args, fmt);
-+ vprintk(fmt, args);
-+ va_end(args);
-+ }
-+}
++/* oob layout for large page size
++ * bad block info is on bytes 0 and 1
++ * the bytes have to be consecutives to avoid
++ * several NAND_CMD_RNDOUT during read
++ */
++static struct nand_ecclayout atmel_oobinfo_large = {
++ .eccbytes = 4,
++ .eccpos = {60, 61, 62, 63},
++ .oobfree = {
++ {2, 58}
++ },
++};
+
-+#define debug(cf, lvl, fmt, arg...) \
-+ at32_cf_debug(cf, __func__, lvl, fmt, ##arg)
++/* oob layout for small page size
++ * bad block info is on bytes 4 and 5
++ * the bytes have to be consecutives to avoid
++ * several NAND_CMD_RNDOUT during read
++ */
++static struct nand_ecclayout atmel_oobinfo_small = {
++ .eccbytes = 4,
++ .eccpos = {0, 1, 2, 3},
++ .oobfree = {
++ {6, 10}
++ },
++};
+
-+#else
-+#define debug(cf, lvl, fmt, arg...) do { } while (0)
-+#endif
++struct atmel_nand_host {
++ struct nand_chip nand_chip;
++ struct mtd_info mtd;
++ void __iomem *io_base;
++ struct atmel_nand_data *board;
++ struct device *dev;
++ void __iomem *ecc;
++};
+
-+static inline int at32_cf_present(struct at32_cf_socket *cf)
++/*
++ * Enable NAND.
++ */
++static void atmel_nand_enable(struct atmel_nand_host *host)
+{
-+ int present = 1;
-+
-+ /* If we don't have a detect pin, assume the card is present */
-+ if (cf->detect_pin >= 0)
-+ present = !gpio_get_value(cf->detect_pin);
-+
-+ return present;
++ if (host->board->enable_pin)
++ gpio_set_value(host->board->enable_pin, 0);
+}
+
-+static irqreturn_t at32_cf_irq(int irq, void *dev_id)
++/*
++ * Disable NAND.
++ */
++static void atmel_nand_disable(struct atmel_nand_host *host)
+{
-+ struct at32_cf_socket *cf = dev_id;
-+ unsigned int present;
-+
-+ present = at32_cf_present(cf);
-+ if (present != cf->present) {
-+ cf->present = present;
-+ debug(cf, 3, "card %s\n", present ? "present" : "gone");
-+ pcmcia_parse_events(&cf->socket, SS_DETECT);
-+ }
-+
-+ return IRQ_HANDLED;
++ if (host->board->enable_pin)
++ gpio_set_value(host->board->enable_pin, 1);
+}
+
-+static int at32_cf_get_status(struct pcmcia_socket *sock, u_int *value)
++/*
++ * Hardware specific access to control-lines
++ */
++static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
-+ struct at32_cf_socket *cf;
-+ u_int status = 0;
-+
-+ cf = container_of(sock, struct at32_cf_socket, socket);
++ struct nand_chip *nand_chip = mtd->priv;
++ struct atmel_nand_host *host = nand_chip->priv;
+
-+ if (at32_cf_present(cf)) {
-+ /* NOTE: gpio on AP7xxx is 3.3V */
-+ status = SS_DETECT | SS_3VCARD;
-+ if (cf->ready_pin < 0 || gpio_get_value(cf->ready_pin))
-+ status |= SS_READY;
-+ if (cf->vcc_pin < 0 || gpio_get_value(cf->vcc_pin))
-+ status |= SS_POWERON;
++ if (ctrl & NAND_CTRL_CHANGE) {
++ if (ctrl & NAND_NCE)
++ atmel_nand_enable(host);
++ else
++ atmel_nand_disable(host);
+ }
++ if (cmd == NAND_CMD_NONE)
++ return;
+
-+ *value = status;
-+ return 0;
++ if (ctrl & NAND_CLE)
++ writeb(cmd, host->io_base + (1 << host->board->cle));
++ else
++ writeb(cmd, host->io_base + (1 << host->board->ale));
+}
+
-+static int at32_cf_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
++/*
++ * Read the Device Ready pin.
++ */
++static int atmel_nand_device_ready(struct mtd_info *mtd)
+{
-+ struct at32_cf_socket *cf = container_of(sock, struct at32_cf_socket, socket);
++ struct nand_chip *nand_chip = mtd->priv;
++ struct atmel_nand_host *host = nand_chip->priv;
+
-+ debug(cf, 2, "mask: %s%s%s%s%s%sflags: %s%s%s%s%s%sVcc %d Vpp %d irq %d\n",
-+ (state->csc_mask==0)?"<NONE> ":"",
-+ (state->csc_mask&SS_DETECT)?"DETECT ":"",
-+ (state->csc_mask&SS_READY)?"READY ":"",
-+ (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"",
-+ (state->csc_mask&SS_BATWARN)?"BATWARN ":"",
-+ (state->csc_mask&SS_STSCHG)?"STSCHG ":"",
-+ (state->flags==0)?"<NONE> ":"",
-+ (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"",
-+ (state->flags&SS_IOCARD)?"IOCARD ":"",
-+ (state->flags&SS_RESET)?"RESET ":"",
-+ (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"",
-+ (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":"",
-+ state->Vcc, state->Vpp, state->io_irq);
++ return gpio_get_value(host->board->rdy_pin);
++}
+
-+ /*
-+ * TODO: Allow boards to override this in case they have level
-+ * converters.
-+ */
-+ switch (state->Vcc) {
-+ case 0:
-+ if (cf->vcc_pin >= 0)
-+ gpio_set_value(cf->vcc_pin, 0);
-+ break;
-+ case 33:
-+ if (cf->vcc_pin >= 0)
-+ gpio_set_value(cf->vcc_pin, 1);
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
++/*
++ * Minimal-overhead PIO for data access.
++ */
++static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
++{
++ struct nand_chip *nand_chip = mtd->priv;
+
-+ if (cf->reset_pin >= 0)
-+ gpio_set_value(cf->reset_pin, state->flags & SS_RESET);
++ __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
++}
+
-+ cf->state = *state;
++static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
++{
++ struct nand_chip *nand_chip = mtd->priv;
+
-+ return 0;
++ __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
+}
+
-+static int at32_cf_socket_init(struct pcmcia_socket *sock)
++static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+{
-+ debug(to_at32_cf(sock), 2, "called\n");
++ struct nand_chip *nand_chip = mtd->priv;
+
-+ return 0;
++ __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
+}
+
-+static int at32_cf_suspend(struct pcmcia_socket *sock)
++static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
+{
-+ debug(to_at32_cf(sock), 2, "called\n");
-+
-+ at32_cf_set_socket(sock, &dead_socket);
++ struct nand_chip *nand_chip = mtd->priv;
+
-+ return 0;
++ __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
+}
+
-+static int at32_cf_set_io_map(struct pcmcia_socket *sock,
-+ struct pccard_io_map *map)
++/*
++ * write oob for small pages
++ */
++static int atmel_nand_write_oob_512(struct mtd_info *mtd,
++ struct nand_chip *chip, int page)
+{
-+ struct at32_cf_socket *cf = container_of(sock, struct at32_cf_socket, socket);
-+ int retval;
-+
-+ debug(cf, 2, "map %u speed %u start 0x%08x stop 0x%08x\n",
-+ map->map, map->speed, map->start, map->stop);
-+ debug(cf, 2, "flags: %s%s%s%s%s%s%s%s\n",
-+ (map->flags == 0) ? "<NONE>":"",
-+ (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
-+ (map->flags & MAP_16BIT) ? "16BIT " : "",
-+ (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
-+ (map->flags & MAP_0WS) ? "0WS " : "",
-+ (map->flags & MAP_WRPROT) ? "WRPROT " : "",
-+ (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
-+ (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
++ int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
++ int eccsize = chip->ecc.size, length = mtd->oobsize;
++ int len, pos, status = 0;
++ const uint8_t *bufpoi = chip->oob_poi;
+
-+ map->flags &= MAP_ACTIVE | MAP_16BIT | MAP_USE_WAIT;
++ pos = eccsize + chunk;
+
-+ if (map->flags & MAP_16BIT)
-+ cf->smc.bus_width = 2;
-+ else
-+ cf->smc.bus_width = 1;
++ chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
++ len = min_t(int, length, chunk);
++ chip->write_buf(mtd, bufpoi, len);
++ bufpoi += len;
++ length -= len;
++ if (length > 0)
++ chip->write_buf(mtd, bufpoi, length);
+
-+ if (map->flags & MAP_USE_WAIT)
-+ cf->smc.nwait_mode = 3;
-+ else
-+ cf->smc.nwait_mode = 0;
++ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
++ status = chip->waitfunc(mtd, chip);
+
-+ retval = smc_set_configuration(cf->cf_cs, &cf->smc);
-+ if (retval) {
-+ printk(KERN_ERR "at32_cf: could not set up SMC for I/O\n");
-+ return retval;
-+ }
++ return status & NAND_STATUS_FAIL ? -EIO : 0;
+
-+ map->start = cf->socket.io_offset;
-+ map->stop = map->start + CF_RES_SIZE - 1;
++}
+
-+ return 0;
++/*
++ * read oob for small pages
++ */
++static int atmel_nand_read_oob_512(struct mtd_info *mtd,
++ struct nand_chip *chip, int page, int sndcmd)
++{
++ if (sndcmd) {
++ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
++ sndcmd = 0;
++ }
++ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
++ return sndcmd;
+}
+
-+static int
-+at32_cf_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *map)
++/*
++ * Calculate HW ECC
++ *
++ * function called after a write
++ *
++ * mtd: MTD block structure
++ * dat: raw data (unused)
++ * ecc_code: buffer for ECC
++ */
++static int atmel_nand_calculate(struct mtd_info *mtd,
++ const u_char *dat, unsigned char *ecc_code)
+{
-+ struct at32_cf_socket *cf;
-+ struct resource *res;
-+ int retval;
++ struct nand_chip *nand_chip = mtd->priv;
++ struct atmel_nand_host *host = nand_chip->priv;
++ uint32_t *eccpos = nand_chip->ecc.layout->eccpos;
++ unsigned int ecc_value;
+
-+ cf = container_of(sock, struct at32_cf_socket, socket);
++ /* get the first 2 ECC bytes */
++ ecc_value = ecc_readl(host->ecc, PR);
+
-+ debug(cf, 2, "map %u speed %u card_start %08x\n",
-+ map->map, map->speed, map->card_start);
-+ debug(cf, 2, "flags: %s%s%s%s%s%s%s%s\n",
-+ (map->flags==0)?"<NONE>":"",
-+ (map->flags&MAP_ACTIVE)?"ACTIVE ":"",
-+ (map->flags&MAP_16BIT)?"16BIT ":"",
-+ (map->flags&MAP_AUTOSZ)?"AUTOSZ ":"",
-+ (map->flags&MAP_0WS)?"0WS ":"",
-+ (map->flags&MAP_WRPROT)?"WRPROT ":"",
-+ (map->flags&MAP_ATTRIB)?"ATTRIB ":"",
-+ (map->flags&MAP_USE_WAIT)?"USE_WAIT ":"");
++ ecc_code[eccpos[0]] = ecc_value & 0xFF;
++ ecc_code[eccpos[1]] = (ecc_value >> 8) & 0xFF;
+
-+ if (map->card_start)
-+ return -EINVAL;
++ /* get the last 2 ECC bytes */
++ ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
+
-+ map->flags &= MAP_ACTIVE | MAP_ATTRIB | MAP_16BIT | MAP_USE_WAIT;
++ ecc_code[eccpos[2]] = ecc_value & 0xFF;
++ ecc_code[eccpos[3]] = (ecc_value >> 8) & 0xFF;
+
-+ if (map->flags & MAP_ATTRIB) {
-+ res = &cf->res_attr;
++ return 0;
++}
+
-+ /* Linksys WCF12 seems to use WAIT when reading CIS */
-+ map->flags |= MAP_USE_WAIT;
-+ } else {
-+ res = &cf->res_mem;
++/*
++ * HW ECC read page function
++ *
++ * mtd: mtd info structure
++ * chip: nand chip info structure
++ * buf: buffer to store read data
++ */
++static int atmel_nand_read_page(struct mtd_info *mtd,
++ struct nand_chip *chip, uint8_t *buf)
++{
++ int eccsize = chip->ecc.size;
++ int eccbytes = chip->ecc.bytes;
++ uint32_t *eccpos = chip->ecc.layout->eccpos;
++ uint8_t *p = buf;
++ uint8_t *oob = chip->oob_poi;
++ uint8_t *ecc_pos;
++ int stat;
++
++ /*
++ * Errata: ALE is incorrectly wired up to the ECC controller
++ * on the AP7000, so it will include the address cycles in the
++ * ECC calculation.
++ *
++ * Workaround: Reset the parity registers before reading the
++ * actual data.
++ */
++ if (cpu_is_at32ap7000()) {
++ struct atmel_nand_host *host = chip->priv;
++ ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
+ }
+
-+ if (map->flags & MAP_USE_WAIT)
-+ cf->smc.nwait_mode = 3;
-+ else
-+ cf->smc.nwait_mode = 0;
++ /* read the page */
++ chip->read_buf(mtd, p, eccsize);
+
-+ retval = smc_set_configuration(cf->cf_cs, &cf->smc);
-+ if (retval) {
-+ printk(KERN_ERR "at32_cf: could not set up SMC for mem\n");
-+ return retval;
++ /* move to ECC position if needed */
++ if (eccpos[0] != 0) {
++ /* This only works on large pages
++ * because the ECC controller waits for
++ * NAND_CMD_RNDOUTSTART after the
++ * NAND_CMD_RNDOUT.
++ * anyway, for small pages, the eccpos[0] == 0
++ */
++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
++ mtd->writesize + eccpos[0], -1);
+ }
+
-+ map->static_start = res->start;
++ /* the ECC controller needs to read the ECC just after the data */
++ ecc_pos = oob + eccpos[0];
++ chip->read_buf(mtd, ecc_pos, eccbytes);
+
-+ return 0;
-+}
++ /* check if there's an error */
++ stat = chip->ecc.correct(mtd, p, oob, NULL);
+
-+static struct pccard_operations at32_cf_ops = {
-+ .init = at32_cf_socket_init,
-+ .suspend = at32_cf_suspend,
-+ .get_status = at32_cf_get_status,
-+ .set_socket = at32_cf_set_socket,
-+ .set_io_map = at32_cf_set_io_map,
-+ .set_mem_map = at32_cf_set_mem_map,
-+};
++ if (stat < 0)
++ mtd->ecc_stats.failed++;
++ else
++ mtd->ecc_stats.corrected += stat;
+
-+static int __init request_pin(struct platform_device *pdev,
-+ unsigned int pin, const char *name)
-+{
-+ if (gpio_request(pin, name)) {
-+ dev_warn(&pdev->dev, "failed to request %s pin\n", name);
-+ return -1;
-+ }
++ /* get back to oob start (end of page) */
++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
+
-+ return pin;
-+}
++ /* read the oob */
++ chip->read_buf(mtd, oob, mtd->oobsize);
+
-+static struct smc_timing at32_cf_timing __initdata = {
-+ .ncs_read_setup = 30,
-+ .nrd_setup = 100,
-+ .ncs_write_setup = 30,
-+ .nwe_setup = 100,
++ return 0;
++}
+
-+ .ncs_read_pulse = 360,
-+ .nrd_pulse = 290,
-+ .ncs_write_pulse = 360,
-+ .nwe_pulse = 290,
++/*
++ * HW ECC Correction
++ *
++ * function called after a read
++ *
++ * mtd: MTD block structure
++ * dat: raw data read from the chip
++ * read_ecc: ECC from the chip (unused)
++ * isnull: unused
++ *
++ * Detect and correct a 1 bit error for a page
++ */
++static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
++ u_char *read_ecc, u_char *isnull)
++{
++ struct nand_chip *nand_chip = mtd->priv;
++ struct atmel_nand_host *host = nand_chip->priv;
++ unsigned int ecc_status;
++ unsigned int ecc_word, ecc_bit;
+
-+ .read_cycle = 420,
-+ .write_cycle = 420,
-+};
++ /* get the status from the Status Register */
++ ecc_status = ecc_readl(host->ecc, SR);
+
-+static int __init at32_cf_probe(struct platform_device *pdev)
-+{
-+ struct at32_cf_socket *cf;
-+ struct cf_platform_data *board = pdev->dev.platform_data;
-+ struct resource *res_skt;
-+ int irq;
-+ int ret;
++ /* if there's no error */
++ if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
++ return 0;
+
-+ dev_dbg(&pdev->dev, "probe");
++ /* get error bit offset (4 bits) */
++ ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
++ /* get word address (12 bits) */
++ ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
++ ecc_word >>= 4;
++
++ /* if there are multiple errors */
++ if (ecc_status & ATMEL_ECC_MULERR) {
++ /* check if it is a freshly erased block
++ * (filled with 0xff) */
++ if ((ecc_bit == ATMEL_ECC_BITADDR)
++ && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
++ /* the block has just been erased, return OK */
++ return 0;
++ }
++ /* it doesn't seems to be a freshly
++ * erased block.
++ * We can't correct so many errors */
++ dev_dbg(host->dev, "atmel_nand : multiple errors detected."
++ " Unable to correct.\n");
++ return -EIO;
++ }
+
-+ if (!board)
-+ return -ENXIO;
++ /* if there's a single bit error : we can correct it */
++ if (ecc_status & ATMEL_ECC_ECCERR) {
++ /* there's nothing much to do here.
++ * the bit error is on the ECC itself.
++ */
++ dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
++ " Nothing to correct\n");
++ return 0;
++ }
+
-+ res_skt = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res_skt)
-+ return -ENXIO;
++ dev_dbg(host->dev, "atmel_nand : one bit error on data."
++ " (word offset in the page :"
++ " 0x%x bit offset : 0x%x)\n",
++ ecc_word, ecc_bit);
++ /* correct the error */
++ if (nand_chip->options & NAND_BUSWIDTH_16) {
++ /* 16 bits words */
++ ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
++ } else {
++ /* 8 bits words */
++ dat[ecc_word] ^= (1 << ecc_bit);
++ }
++ dev_dbg(host->dev, "atmel_nand : error corrected\n");
++ return 1;
++}
+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0)
-+ return irq;
++/*
++ * Enable HW ECC : unused on most chips
++ */
++static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
++{
++ if (cpu_is_at32ap7000()) {
++ struct nand_chip *nand_chip = mtd->priv;
++ struct atmel_nand_host *host = nand_chip->priv;
++ ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
++ }
++}
+
-+ cf = kzalloc(sizeof(struct at32_cf_socket), GFP_KERNEL);
-+ if (!cf)
-+ return -ENOMEM;
++#ifdef CONFIG_MTD_PARTITIONS
++static const char *part_probes[] = { "cmdlinepart", NULL };
++#endif
+
-+ cf->detect_pin = -1;
-+ cf->reset_pin = -1;
-+ cf->vcc_pin = -1;
-+ cf->ready_pin = -1;
-+ cf->cf_cs = board->cs;
++/*
++ * Probe for the NAND device.
++ */
++static int __init atmel_nand_probe(struct platform_device *pdev)
++{
++ struct atmel_nand_host *host;
++ struct mtd_info *mtd;
++ struct nand_chip *nand_chip;
++ struct resource *regs;
++ struct resource *mem;
++ int res;
+
-+ if (board->detect_pin != GPIO_PIN_NONE)
-+ cf->detect_pin = request_pin(pdev, board->detect_pin,
-+ "cf_detect");
-+ if (board->reset_pin != GPIO_PIN_NONE)
-+ cf->reset_pin = request_pin(pdev, board->reset_pin,
-+ "cf_reset");
-+ if (board->vcc_pin != GPIO_PIN_NONE)
-+ cf->vcc_pin = request_pin(pdev, board->vcc_pin,
-+ "cf_vcc");
-+ if (board->ready_pin != GPIO_PIN_NONE)
-+ /* READY is also used for irq through EIM */
-+ cf->ready_pin = board->ready_pin;
++#ifdef CONFIG_MTD_PARTITIONS
++ struct mtd_partition *partitions = NULL;
++ int num_partitions = 0;
++#endif
+
-+ debug(cf, 2, "pins: detect=%d reset=%d vcc=%d\n",
-+ cf->detect_pin, cf->reset_pin, cf->vcc_pin);
++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!mem) {
++ printk(KERN_ERR "atmel_nand: can't get I/O resource mem\n");
++ return -ENXIO;
++ }
+
-+ cf->socket.pci_irq = irq;
-+ cf->socket.ops = &at32_cf_ops;
-+ cf->socket.resource_ops = &pccard_static_ops;
-+ cf->socket.dev.parent = &pdev->dev;
-+ cf->socket.owner = THIS_MODULE;
-+ cf->socket.features =
-+ SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP | SS_CAP_PCCARD;
-+ cf->socket.map_size = CF_RES_SIZE;
++ /* Allocate memory for the device structure (and zero it) */
++ host = kzalloc(sizeof(struct atmel_nand_host), GFP_KERNEL);
++ if (!host) {
++ printk(KERN_ERR "atmel_nand: failed to allocate device structure.\n");
++ return -ENOMEM;
++ }
+
-+ cf->res_attr.start = res_skt->start + CF_ATTR_OFFSET;
-+ cf->res_attr.end = cf->res_attr.start + CF_RES_SIZE - 1;
-+ cf->res_attr.name = "attribute";
-+ cf->res_attr.flags = IORESOURCE_MEM;
-+ ret = request_resource(res_skt, &cf->res_attr);
-+ if (ret)
-+ goto err_request_res_attr;
++ host->io_base = ioremap(mem->start, mem->end - mem->start + 1);
++ if (host->io_base == NULL) {
++ printk(KERN_ERR "atmel_nand: ioremap failed\n");
++ res = -EIO;
++ goto err_nand_ioremap;
++ }
+
-+ cf->res_mem.start = res_skt->start + CF_MEM_OFFSET;
-+ cf->res_mem.end = cf->res_mem.start + CF_RES_SIZE - 1;
-+ cf->res_mem.name = "memory";
-+ cf->res_mem.flags = IORESOURCE_MEM;
-+ ret = request_resource(res_skt, &cf->res_mem);
-+ if (ret)
-+ goto err_request_res_mem;
++ mtd = &host->mtd;
++ nand_chip = &host->nand_chip;
++ host->board = pdev->dev.platform_data;
++ host->dev = &pdev->dev;
+
-+ cf->res_io.start = res_skt->start + CF_IO_OFFSET;
-+ cf->res_io.end = cf->res_io.start + CF_RES_SIZE - 1;
-+ cf->res_io.name = "io";
-+ cf->res_io.flags = IORESOURCE_MEM;
-+ ret = request_resource(res_skt, &cf->res_io);
-+ if (ret)
-+ goto err_request_res_io;
++ nand_chip->priv = host; /* link the private data structures */
++ mtd->priv = nand_chip;
++ mtd->owner = THIS_MODULE;
+
-+ cf->socket.io_offset = cf->res_io.start;
++ /* Set address of NAND IO lines */
++ nand_chip->IO_ADDR_R = host->io_base;
++ nand_chip->IO_ADDR_W = host->io_base;
++ nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
+
-+ if (cf->detect_pin >= 0) {
-+ ret = request_irq(gpio_to_irq(cf->detect_pin), at32_cf_irq,
-+ IRQF_SHARED, "cf_detect", cf);
-+ if (ret) {
-+ debug(cf, 1,
-+ "failed to request cf_detect interrupt\n");
-+ goto err_detect_irq;
++ if (host->board->rdy_pin)
++ nand_chip->dev_ready = atmel_nand_device_ready;
++
++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ if (!regs && hard_ecc) {
++ printk(KERN_ERR "atmel_nand: can't get I/O resource "
++ "regs\nFalling back on software ECC\n");
++ }
++
++ nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
++ if (no_ecc)
++ nand_chip->ecc.mode = NAND_ECC_NONE;
++ if (hard_ecc && regs) {
++ host->ecc = ioremap(regs->start, regs->end - regs->start + 1);
++ if (host->ecc == NULL) {
++ printk(KERN_ERR "atmel_nand: ioremap failed\n");
++ res = -EIO;
++ goto err_ecc_ioremap;
+ }
++ nand_chip->ecc.mode = NAND_ECC_HW_SYNDROME;
++ nand_chip->ecc.calculate = atmel_nand_calculate;
++ nand_chip->ecc.correct = atmel_nand_correct;
++ nand_chip->ecc.hwctl = atmel_nand_hwctl;
++ nand_chip->ecc.read_page = atmel_nand_read_page;
++ nand_chip->ecc.bytes = 4;
++ nand_chip->ecc.prepad = 0;
++ nand_chip->ecc.postpad = 0;
+ }
+
-+ cf->present = at32_cf_present(cf);
++ nand_chip->chip_delay = 20; /* 20us command delay time */
+
-+ /* Setup SMC timings */
-+ smc_set_timing(&cf->smc, &at32_cf_timing);
++ if (host->board->bus_width_16) { /* 16-bit bus width */
++ nand_chip->options |= NAND_BUSWIDTH_16;
++ nand_chip->read_buf = atmel_read_buf16;
++ nand_chip->write_buf = atmel_write_buf16;
++ } else {
++ nand_chip->read_buf = atmel_read_buf;
++ nand_chip->write_buf = atmel_write_buf;
++ }
+
-+ cf->smc.bus_width = 2;
-+ cf->smc.nrd_controlled = 1;
-+ cf->smc.nwe_controlled = 1;
-+ cf->smc.nwait_mode = 0;
-+ cf->smc.byte_write = 0;
-+ cf->smc.tdf_cycles = 8;
-+ cf->smc.tdf_mode = 0;
++ platform_set_drvdata(pdev, host);
++ atmel_nand_enable(host);
+
-+ ret = smc_set_configuration(cf->cf_cs, &cf->smc);
-+ if (ret) {
-+ debug(cf, 1, "failed to configure SMC\n", ret);
-+ goto err_smc;
++ if (host->board->det_pin) {
++ if (gpio_get_value(host->board->det_pin)) {
++ printk("No SmartMedia card inserted.\n");
++ res = ENXIO;
++ goto err_no_card;
++ }
+ }
+
-+ ret = pcmcia_register_socket(&cf->socket);
-+ if (ret) {
-+ debug(cf, 1, "failed to register socket: %d\n", ret);
-+ goto err_register_socket;
++ /* first scan to find the device and get the page size */
++ if (nand_scan_ident(mtd, 1)) {
++ res = -ENXIO;
++ goto err_scan_ident;
+ }
+
-+ if (cf->reset_pin >= 0)
-+ gpio_direction_output(cf->reset_pin, 0);
++ if (nand_chip->ecc.mode == NAND_ECC_HW_SYNDROME) {
++ /* ECC is calculated for the whole page (1 step) */
++ nand_chip->ecc.size = mtd->writesize;
++
++ /* set ECC page size and oob layout */
++ switch (mtd->writesize) {
++ case 512:
++ nand_chip->ecc.layout = &atmel_oobinfo_small;
++ nand_chip->ecc.read_oob = atmel_nand_read_oob_512;
++ nand_chip->ecc.write_oob = atmel_nand_write_oob_512;
++ ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
++ break;
++ case 1024:
++ nand_chip->ecc.layout = &atmel_oobinfo_large;
++ ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
++ break;
++ case 2048:
++ nand_chip->ecc.layout = &atmel_oobinfo_large;
++ ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
++ break;
++ case 4096:
++ nand_chip->ecc.layout = &atmel_oobinfo_large;
++ ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
++ break;
++ default:
++ /* page size not handled by HW ECC */
++ /* switching back to soft ECC */
++ nand_chip->ecc.mode = NAND_ECC_SOFT;
++ nand_chip->ecc.calculate = NULL;
++ nand_chip->ecc.correct = NULL;
++ nand_chip->ecc.hwctl = NULL;
++ nand_chip->ecc.read_page = NULL;
++ nand_chip->ecc.postpad = 0;
++ nand_chip->ecc.prepad = 0;
++ nand_chip->ecc.bytes = 0;
++ break;
++ }
++ }
+
-+ platform_set_drvdata(pdev, cf);
++ /* second phase scan */
++ if (nand_scan_tail(mtd)) {
++ res = -ENXIO;
++ goto err_scan_tail;
++ }
+
-+ dev_info(&pdev->dev, "Atmel SMC CF interface at 0x%08lx\n",
-+ (unsigned long)res_skt->start);
++#ifdef CONFIG_MTD_PARTITIONS
++#ifdef CONFIG_MTD_CMDLINE_PARTS
++ mtd->name = "atmel_nand";
++ num_partitions = parse_mtd_partitions(mtd, part_probes,
++ &partitions, 0);
++#endif
++ if (num_partitions <= 0 && host->board->partition_info)
++ partitions = host->board->partition_info(mtd->size,
++ &num_partitions);
++
++ if ((!partitions) || (num_partitions == 0)) {
++ printk(KERN_ERR "atmel_nand: No parititions defined, or unsupported device.\n");
++ res = ENXIO;
++ goto err_no_partitions;
++ }
+
-+ return 0;
++ res = add_mtd_partitions(mtd, partitions, num_partitions);
++#else
++ res = add_mtd_device(mtd);
++#endif
+
-+err_register_socket:
-+err_smc:
-+ if (cf->detect_pin >= 0)
-+ free_irq(gpio_to_irq(cf->detect_pin), cf);
-+err_detect_irq:
-+ release_resource(&cf->res_io);
-+err_request_res_io:
-+ release_resource(&cf->res_mem);
-+err_request_res_mem:
-+ release_resource(&cf->res_attr);
-+err_request_res_attr:
-+ if (cf->vcc_pin >= 0)
-+ gpio_free(cf->vcc_pin);
-+ if (cf->reset_pin >= 0)
-+ gpio_free(cf->reset_pin);
-+ if (cf->detect_pin >= 0)
-+ gpio_free(cf->detect_pin);
-+ kfree(cf);
++ if (!res)
++ return res;
+
-+ return ret;
++#ifdef CONFIG_MTD_PARTITIONS
++err_no_partitions:
++#endif
++ nand_release(mtd);
++err_scan_tail:
++err_scan_ident:
++err_no_card:
++ atmel_nand_disable(host);
++ platform_set_drvdata(pdev, NULL);
++ if (host->ecc)
++ iounmap(host->ecc);
++err_ecc_ioremap:
++ iounmap(host->io_base);
++err_nand_ioremap:
++ kfree(host);
++ return res;
+}
+
-+static int __exit at32_cf_remove(struct platform_device *pdev)
++/*
++ * Remove a NAND device.
++ */
++static int __exit atmel_nand_remove(struct platform_device *pdev)
+{
-+ struct at32_cf_socket *cf = platform_get_drvdata(pdev);
++ struct atmel_nand_host *host = platform_get_drvdata(pdev);
++ struct mtd_info *mtd = &host->mtd;
+
-+ pcmcia_unregister_socket(&cf->socket);
-+ if (cf->detect_pin >= 0) {
-+ free_irq(gpio_to_irq(cf->detect_pin), cf);
-+ gpio_free(cf->detect_pin);
-+ }
-+ if (cf->vcc_pin >= 0)
-+ gpio_free(cf->vcc_pin);
-+ if (cf->reset_pin >= 0)
-+ gpio_free(cf->reset_pin);
++ nand_release(mtd);
+
-+ release_resource(&cf->res_io);
-+ release_resource(&cf->res_mem);
-+ release_resource(&cf->res_attr);
-+ kfree(cf);
-+ platform_set_drvdata(pdev, NULL);
++ atmel_nand_disable(host);
++
++ if (host->ecc)
++ iounmap(host->ecc);
++ iounmap(host->io_base);
++ kfree(host);
+
+ return 0;
+}
+
-+static struct platform_driver at32_cf_driver = {
-+ .remove = __exit_p(at32_cf_remove),
++static struct platform_driver atmel_nand_driver = {
++ .remove = __exit_p(atmel_nand_remove),
+ .driver = {
-+ .name = "at32_cf",
++ .name = "atmel_nand",
+ .owner = THIS_MODULE,
+ },
+};
+
-+static int __init at32_cf_init(void)
++static int __init atmel_nand_init(void)
+{
-+ int ret;
-+
-+ ret = platform_driver_probe(&at32_cf_driver, at32_cf_probe);
-+ if (ret)
-+ printk(KERN_ERR "at32_cf: probe failed: %d\n", ret);
-+ return ret;
++ return platform_driver_probe(&atmel_nand_driver, atmel_nand_probe);
+}
+
-+static void __exit at32_cf_exit(void)
++
++static void __exit atmel_nand_exit(void)
+{
-+ platform_driver_unregister(&at32_cf_driver);
++ platform_driver_unregister(&atmel_nand_driver);
+}
+
-+module_init(at32_cf_init);
-+module_exit(at32_cf_exit);
++
++module_init(atmel_nand_init);
++module_exit(atmel_nand_exit);
+
+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("Driver for SMC PCMCIA interface");
-+MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
++MODULE_AUTHOR("Rick Bronson");
++MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
++MODULE_ALIAS("platform:atmel_nand");
+--- /dev/null
++++ b/drivers/mtd/nand/atmel_nand_ecc.h
+@@ -0,0 +1,36 @@
++/*
++ * Error Corrected Code Controller (ECC) - System peripherals regsters.
++ * Based on AT91SAM9260 datasheet revision B.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#ifndef ATMEL_NAND_ECC_H
++#define ATMEL_NAND_ECC_H
++
++#define ATMEL_ECC_CR 0x00 /* Control register */
++#define ATMEL_ECC_RST (1 << 0) /* Reset parity */
++
++#define ATMEL_ECC_MR 0x04 /* Mode register */
++#define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */
++#define ATMEL_ECC_PAGESIZE_528 (0)
++#define ATMEL_ECC_PAGESIZE_1056 (1)
++#define ATMEL_ECC_PAGESIZE_2112 (2)
++#define ATMEL_ECC_PAGESIZE_4224 (3)
++
++#define ATMEL_ECC_SR 0x08 /* Status register */
++#define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */
++#define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
++#define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */
++
++#define ATMEL_ECC_PR 0x0c /* Parity register */
++#define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */
++#define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
++
++#define ATMEL_ECC_NPR 0x10 /* NParity register */
++#define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
++
++#endif
+--- a/drivers/mtd/nand/bf5xx_nand.c
++++ b/drivers/mtd/nand/bf5xx_nand.c
+@@ -803,3 +803,4 @@
+ MODULE_LICENSE("GPL");
+ MODULE_AUTHOR(DRV_AUTHOR);
+ MODULE_DESCRIPTION(DRV_DESC);
++MODULE_ALIAS("platform:" DRV_NAME);
+--- a/drivers/mtd/nand/ndfc.c
++++ b/drivers/mtd/nand/ndfc.c
+@@ -317,3 +317,5 @@
+ MODULE_LICENSE("GPL");
+ MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
+ MODULE_DESCRIPTION("Platform driver for NDFC");
++MODULE_ALIAS("platform:ndfc-chip");
++MODULE_ALIAS("platform:ndfc-nand");
+--- a/drivers/mtd/nand/orion_nand.c
++++ b/drivers/mtd/nand/orion_nand.c
+@@ -169,3 +169,4 @@
+ MODULE_LICENSE("GPL");
+ MODULE_AUTHOR("Tzachi Perelstein");
+ MODULE_DESCRIPTION("NAND glue for Orion platforms");
++MODULE_ALIAS("platform:orion_nand");
+--- a/drivers/mtd/nand/plat_nand.c
++++ b/drivers/mtd/nand/plat_nand.c
+@@ -161,3 +161,4 @@
+ MODULE_LICENSE("GPL");
+ MODULE_AUTHOR("Vitaly Wool");
+ MODULE_DESCRIPTION("Simple generic NAND driver");
++MODULE_ALIAS("platform:gen_nand");
+--- a/drivers/mtd/nand/s3c2410.c
++++ b/drivers/mtd/nand/s3c2410.c
+@@ -927,3 +927,6 @@
+ MODULE_LICENSE("GPL");
+ MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+ MODULE_DESCRIPTION("S3C24XX MTD NAND driver");
++MODULE_ALIAS("platform:s3c2410-nand");
++MODULE_ALIAS("platform:s3c2412-nand");
++MODULE_ALIAS("platform:s3c2440-nand");
+--- a/drivers/net/macb.c
++++ b/drivers/net/macb.c
+@@ -1277,8 +1277,45 @@
+ return 0;
+ }
+
++#ifdef CONFIG_PM
++static int macb_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct net_device *netdev = platform_get_drvdata(pdev);
++ struct macb *bp = netdev_priv(netdev);
++
++ netif_device_detach(netdev);
++
++#ifndef CONFIG_ARCH_AT91
++ clk_disable(bp->hclk);
++#endif
++ clk_disable(bp->pclk);
++
++ return 0;
++}
++
++static int macb_resume(struct platform_device *pdev)
++{
++ struct net_device *netdev = platform_get_drvdata(pdev);
++ struct macb *bp = netdev_priv(netdev);
++
++ clk_enable(bp->pclk);
++#ifndef CONFIG_ARCH_AT91
++ clk_enable(bp->hclk);
++#endif
++
++ netif_device_attach(netdev);
++
++ return 0;
++}
++#else
++#define macb_suspend NULL
++#define macb_resume NULL
++#endif
++
+ static struct platform_driver macb_driver = {
+ .remove = __exit_p(macb_remove),
++ .suspend = macb_suspend,
++ .resume = macb_resume,
+ .driver = {
+ .name = "macb",
+ },
+--- a/drivers/parport/Kconfig
++++ b/drivers/parport/Kconfig
+@@ -36,7 +36,7 @@
+ config PARPORT_PC
+ tristate "PC-style hardware"
+ depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && \
+- (!M68K || ISA) && !MN10300
++ (!M68K || ISA) && !MN10300 && !AVR32
+ ---help---
+ You should say Y here if you have a PC-style parallel port. All
+ IBM PC compatible computers and some Alphas have PC-style
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
-@@ -276,6 +276,13 @@
+@@ -277,6 +277,13 @@
Say Y here to support the CompactFlash controller on the
PA Semi Electra eval board.
sa11xx_core-y += soc_common.o sa11xx_base.o
pxa2xx_core-y += soc_common.o pxa2xx_base.o
---- a/drivers/serial/atmel_serial.c
-+++ b/drivers/serial/atmel_serial.c
-@@ -7,6 +7,8 @@
- * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
- * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
- *
-+ * DMA support added by Chip Coldwell.
+--- /dev/null
++++ b/drivers/pcmcia/at32_cf.c
+@@ -0,0 +1,533 @@
++/*
++ * Driver for AVR32 Static Memory Controller: CompactFlash support
+ *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
-@@ -33,7 +35,9 @@
- #include <linux/sysrq.h>
- #include <linux/tty_flip.h>
- #include <linux/platform_device.h>
++ * Copyright (C) 2006 Atmel Norway
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
++ * 02111-1307, USA.
++ *
++ * The full GNU General Public License is included in this
++ * distribution in the file called COPYING.
++ */
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/err.h>
++#include <linux/clk.h>
+#include <linux/dma-mapping.h>
- #include <linux/atmel_pdc.h>
-+#include <linux/atmel_serial.h>
-
- #include <asm/io.h>
-
-@@ -45,7 +49,9 @@
- #include <asm/arch/gpio.h>
- #endif
-
--#include "atmel_serial.h"
-+#define PDC_BUFFER_SIZE 512
-+/* Revisit: We should calculate this based on the actual port settings */
-+#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
-
- #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
- #define SUPPORT_SYSRQ
-@@ -74,6 +80,7 @@
-
- #define ATMEL_ISR_PASS_LIMIT 256
-
-+/* UART registers. CR is write-only, hence no GET macro */
- #define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
- #define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
- #define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
-@@ -87,8 +94,6 @@
- #define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
- #define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
-
--// #define UART_GET_CR(port) __raw_readl((port)->membase + ATMEL_US_CR) // is write-only
--
- /* PDC registers */
- #define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
- #define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
-@@ -101,12 +106,24 @@
-
- #define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
- #define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
--//#define UART_PUT_TNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNPR)
--//#define UART_PUT_TNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNCR)
-
- static int (*atmel_open_hook)(struct uart_port *);
- static void (*atmel_close_hook)(struct uart_port *);
-
-+struct atmel_dma_buffer {
-+ unsigned char *buf;
-+ dma_addr_t dma_addr;
-+ unsigned int dma_size;
-+ unsigned int ofs;
-+};
+
-+struct atmel_uart_char {
-+ u16 status;
-+ u16 ch;
-+};
++#include <pcmcia/ss.h>
+
-+#define ATMEL_SERIAL_RINGSIZE 1024
++#include <asm/gpio.h>
++#include <asm/io.h>
++#include <asm/arch/board.h>
+
- /*
- * We wrap our port structure around the generic uart_port.
- */
-@@ -115,6 +132,19 @@
- struct clk *clk; /* uart clock */
- unsigned short suspended; /* is port suspended? */
- int break_active; /* break being received */
++#include <asm/arch/smc.h>
+
-+ short use_dma_rx; /* enable PDC receiver */
-+ short pdc_rx_idx; /* current PDC RX buffer */
-+ struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
++struct at32_cf_socket {
++ struct pcmcia_socket socket;
++ int detect_pin;
++ int reset_pin;
++ int vcc_pin;
++ int ready_pin;
++ struct resource res_attr;
++ struct resource res_mem;
++ struct resource res_io;
++ struct smc_config smc;
++ unsigned int irq;
++ unsigned int cf_cs;
++ socket_state_t state;
++ unsigned present:1;
++};
++#define to_at32_cf(sock) container_of(sock, struct at32_cf_socket, socket)
+
-+ short use_dma_tx; /* enable PDC transmitter */
-+ struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
++/*
++ * We have the following memory layout relative to the base address:
++ *
++ * Alt IDE Mode: 00e0 0000 -> 00ff ffff
++ * True IDE Mode: 00c0 0000 -> 00df ffff
++ * I/O memory: 0080 0000 -> 00bf ffff
++ * Common memory: 0040 0000 -> 007f ffff
++ * Attribute memory: 0000 0000 -> 003f ffff
++ */
++#define CF_ATTR_OFFSET 0x00000000
++#define CF_MEM_OFFSET 0x00400000
++#define CF_IO_OFFSET 0x00800000
++#define CF_RES_SIZE 4096
+
-+ struct tasklet_struct tasklet;
-+ unsigned int irq_status;
-+ unsigned int irq_status_prev;
++#ifdef DEBUG
+
-+ struct circ_buf rx_ring;
- };
-
- static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
-@@ -123,6 +153,38 @@
- static struct console atmel_console;
- #endif
-
-+static inline struct atmel_uart_port *
-+to_atmel_uart_port(struct uart_port *uart)
-+{
-+ return container_of(uart, struct atmel_uart_port, uart);
-+}
++static int pc_debug;
++module_param(pc_debug, int, 0644);
+
-+#ifdef CONFIG_SERIAL_ATMEL_PDC
-+static bool atmel_use_dma_rx(struct uart_port *port)
++static void at32_cf_debug(struct at32_cf_socket *cf, const char *func,
++ int level, const char *fmt, ...)
+{
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++ va_list args;
+
-+ return atmel_port->use_dma_rx;
++ if (pc_debug > level) {
++ printk(KERN_DEBUG "at32_cf/%u: %s: ", cf->cf_cs, func);
++ va_start(args, fmt);
++ vprintk(fmt, args);
++ va_end(args);
++ }
+}
+
-+static bool atmel_use_dma_tx(struct uart_port *port)
-+{
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++#define debug(cf, lvl, fmt, arg...) \
++ at32_cf_debug(cf, __func__, lvl, fmt, ##arg)
+
-+ return atmel_port->use_dma_tx;
-+}
+#else
-+static bool atmel_use_dma_rx(struct uart_port *port)
-+{
-+ return false;
-+}
-+
-+static bool atmel_use_dma_tx(struct uart_port *port)
-+{
-+ return false;
-+}
++#define debug(cf, lvl, fmt, arg...) do { } while (0)
+#endif
+
- /*
- * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
- */
-@@ -142,8 +204,8 @@
- #ifdef CONFIG_ARCH_AT91RM9200
- if (cpu_is_at91rm9200()) {
- /*
-- * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
-- * We need to drive the pin manually.
-+ * AT91RM9200 Errata #39: RTS0 is not internally connected
-+ * to PA21. We need to drive the pin manually.
- */
- if (port->mapbase == AT91RM9200_BASE_US0) {
- if (mctrl & TIOCM_RTS)
-@@ -204,7 +266,12 @@
- */
- static void atmel_stop_tx(struct uart_port *port)
- {
-- UART_PUT_IDR(port, ATMEL_US_TXRDY);
-+ if (atmel_use_dma_tx(port)) {
-+ /* disable PDC transmit */
-+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
-+ UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
-+ } else
-+ UART_PUT_IDR(port, ATMEL_US_TXRDY);
- }
-
- /*
-@@ -212,7 +279,17 @@
- */
- static void atmel_start_tx(struct uart_port *port)
- {
-- UART_PUT_IER(port, ATMEL_US_TXRDY);
-+ if (atmel_use_dma_tx(port)) {
-+ if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
-+ /* The transmitter is already running. Yes, we
-+ really need this.*/
-+ return;
-+
-+ UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
-+ /* re-enable PDC transmit */
-+ UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
-+ } else
-+ UART_PUT_IER(port, ATMEL_US_TXRDY);
- }
-
- /*
-@@ -220,7 +297,12 @@
- */
- static void atmel_stop_rx(struct uart_port *port)
- {
-- UART_PUT_IDR(port, ATMEL_US_RXRDY);
-+ if (atmel_use_dma_rx(port)) {
-+ /* disable PDC receive */
-+ UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
-+ UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
-+ } else
-+ UART_PUT_IDR(port, ATMEL_US_RXRDY);
- }
-
- /*
-@@ -228,7 +310,8 @@
- */
- static void atmel_enable_ms(struct uart_port *port)
- {
-- UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
-+ UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
-+ | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
- }
-
- /*
-@@ -243,22 +326,63 @@
- }
-
- /*
-+ * Stores the incoming character in the ring buffer
-+ */
-+static void
-+atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
-+ unsigned int ch)
++static inline int at32_cf_present(struct at32_cf_socket *cf)
+{
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-+ struct circ_buf *ring = &atmel_port->rx_ring;
-+ struct atmel_uart_char *c;
-+
-+ if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
-+ /* Buffer overflow, ignore char */
-+ return;
-+
-+ c = &((struct atmel_uart_char *)ring->buf)[ring->head];
-+ c->status = status;
-+ c->ch = ch;
++ int present = 1;
+
-+ /* Make sure the character is stored before we update head. */
-+ smp_wmb();
++ /* If we don't have a detect pin, assume the card is present */
++ if (cf->detect_pin >= 0)
++ present = !gpio_get_value(cf->detect_pin);
+
-+ ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
++ return present;
+}
+
-+/*
-+ * Deal with parity, framing and overrun errors.
-+ */
-+static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
++static irqreturn_t at32_cf_irq(int irq, void *dev_id)
+{
-+ /* clear error */
-+ UART_PUT_CR(port, ATMEL_US_RSTSTA);
++ struct at32_cf_socket *cf = dev_id;
++ unsigned int present;
+
-+ if (status & ATMEL_US_RXBRK) {
-+ /* ignore side-effect */
-+ status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
-+ port->icount.brk++;
++ present = at32_cf_present(cf);
++ if (present != cf->present) {
++ cf->present = present;
++ debug(cf, 3, "card %s\n", present ? "present" : "gone");
++ pcmcia_parse_events(&cf->socket, SS_DETECT);
+ }
-+ if (status & ATMEL_US_PARE)
-+ port->icount.parity++;
-+ if (status & ATMEL_US_FRAME)
-+ port->icount.frame++;
-+ if (status & ATMEL_US_OVRE)
-+ port->icount.overrun++;
-+}
+
-+/*
- * Characters received (called from interrupt handler)
- */
- static void atmel_rx_chars(struct uart_port *port)
- {
-- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
-- struct tty_struct *tty = port->info->tty;
-- unsigned int status, ch, flg;
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-+ unsigned int status, ch;
-
- status = UART_GET_CSR(port);
- while (status & ATMEL_US_RXRDY) {
- ch = UART_GET_CHAR(port);
-
-- port->icount.rx++;
--
-- flg = TTY_NORMAL;
--
- /*
- * note that the error handling code is
- * out of the main execution path
-@@ -266,15 +390,14 @@
- if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
- | ATMEL_US_OVRE | ATMEL_US_RXBRK)
- || atmel_port->break_active)) {
-- UART_PUT_CR(port, ATMEL_US_RSTSTA); /* clear error */
-+
-+ /* clear error */
-+ UART_PUT_CR(port, ATMEL_US_RSTSTA);
-+
- if (status & ATMEL_US_RXBRK
- && !atmel_port->break_active) {
-- status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */
-- port->icount.brk++;
- atmel_port->break_active = 1;
- UART_PUT_IER(port, ATMEL_US_RXBRK);
-- if (uart_handle_break(port))
-- goto ignore_char;
- } else {
- /*
- * This is either the end-of-break
-@@ -287,52 +410,30 @@
- status &= ~ATMEL_US_RXBRK;
- atmel_port->break_active = 0;
- }
-- if (status & ATMEL_US_PARE)
-- port->icount.parity++;
-- if (status & ATMEL_US_FRAME)
-- port->icount.frame++;
-- if (status & ATMEL_US_OVRE)
-- port->icount.overrun++;
--
-- status &= port->read_status_mask;
--
-- if (status & ATMEL_US_RXBRK)
-- flg = TTY_BREAK;
-- else if (status & ATMEL_US_PARE)
-- flg = TTY_PARITY;
-- else if (status & ATMEL_US_FRAME)
-- flg = TTY_FRAME;
- }
-
-- if (uart_handle_sysrq_char(port, ch))
-- goto ignore_char;
--
-- uart_insert_char(port, status, ATMEL_US_OVRE, ch, flg);
--
-- ignore_char:
-+ atmel_buffer_rx_char(port, status, ch);
- status = UART_GET_CSR(port);
- }
-
-- tty_flip_buffer_push(tty);
-+ tasklet_schedule(&atmel_port->tasklet);
- }
-
- /*
-- * Transmit characters (called from interrupt handler)
-+ * Transmit characters (called from tasklet with TXRDY interrupt
-+ * disabled)
- */
- static void atmel_tx_chars(struct uart_port *port)
- {
- struct circ_buf *xmit = &port->info->xmit;
-
-- if (port->x_char) {
-+ if (port->x_char && UART_GET_CSR(port) & ATMEL_US_TXRDY) {
- UART_PUT_CHAR(port, port->x_char);
- port->icount.tx++;
- port->x_char = 0;
-- return;
- }
-- if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
-- atmel_stop_tx(port);
-+ if (uart_circ_empty(xmit) || uart_tx_stopped(port))
- return;
-- }
-
- while (UART_GET_CSR(port) & ATMEL_US_TXRDY) {
- UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
-@@ -345,8 +446,88 @@
- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
- uart_write_wakeup(port);
-
-- if (uart_circ_empty(xmit))
-- atmel_stop_tx(port);
-+ if (!uart_circ_empty(xmit))
-+ UART_PUT_IER(port, ATMEL_US_TXRDY);
++ return IRQ_HANDLED;
+}
+
-+/*
-+ * receive interrupt handler.
-+ */
-+static void
-+atmel_handle_receive(struct uart_port *port, unsigned int pending)
++static int at32_cf_get_status(struct pcmcia_socket *sock, u_int *value)
+{
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++ struct at32_cf_socket *cf;
++ u_int status = 0;
+
-+ if (atmel_use_dma_rx(port)) {
-+ /*
-+ * PDC receive. Just schedule the tasklet and let it
-+ * figure out the details.
-+ *
-+ * TODO: We're not handling error flags correctly at
-+ * the moment.
-+ */
-+ if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
-+ UART_PUT_IDR(port, (ATMEL_US_ENDRX
-+ | ATMEL_US_TIMEOUT));
-+ tasklet_schedule(&atmel_port->tasklet);
-+ }
++ cf = container_of(sock, struct at32_cf_socket, socket);
+
-+ if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
-+ ATMEL_US_FRAME | ATMEL_US_PARE))
-+ atmel_pdc_rxerr(port, pending);
++ if (at32_cf_present(cf)) {
++ /* NOTE: gpio on AP7xxx is 3.3V */
++ status = SS_DETECT | SS_3VCARD;
++ if (cf->ready_pin < 0 || gpio_get_value(cf->ready_pin))
++ status |= SS_READY;
++ if (cf->vcc_pin < 0 || gpio_get_value(cf->vcc_pin))
++ status |= SS_POWERON;
+ }
+
-+ /* Interrupt receive */
-+ if (pending & ATMEL_US_RXRDY)
-+ atmel_rx_chars(port);
-+ else if (pending & ATMEL_US_RXBRK) {
-+ /*
-+ * End of break detected. If it came along with a
-+ * character, atmel_rx_chars will handle it.
-+ */
-+ UART_PUT_CR(port, ATMEL_US_RSTSTA);
-+ UART_PUT_IDR(port, ATMEL_US_RXBRK);
-+ atmel_port->break_active = 0;
-+ }
++ *value = status;
++ return 0;
+}
+
-+/*
-+ * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
-+ */
-+static void
-+atmel_handle_transmit(struct uart_port *port, unsigned int pending)
++static int at32_cf_set_socket(struct pcmcia_socket *sock, socket_state_t *state)
+{
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++ struct at32_cf_socket *cf = container_of(sock, struct at32_cf_socket, socket);
+
-+ if (atmel_use_dma_tx(port)) {
-+ /* PDC transmit */
-+ if (pending & (ATMEL_US_ENDTX | ATMEL_US_TXBUFE)) {
-+ UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
-+ tasklet_schedule(&atmel_port->tasklet);
-+ }
-+ } else {
-+ /* Interrupt transmit */
-+ if (pending & ATMEL_US_TXRDY) {
-+ UART_PUT_IDR(port, ATMEL_US_TXRDY);
-+ tasklet_schedule(&atmel_port->tasklet);
-+ }
++ debug(cf, 2, "mask: %s%s%s%s%s%sflags: %s%s%s%s%s%sVcc %d Vpp %d irq %d\n",
++ (state->csc_mask==0)?"<NONE> ":"",
++ (state->csc_mask&SS_DETECT)?"DETECT ":"",
++ (state->csc_mask&SS_READY)?"READY ":"",
++ (state->csc_mask&SS_BATDEAD)?"BATDEAD ":"",
++ (state->csc_mask&SS_BATWARN)?"BATWARN ":"",
++ (state->csc_mask&SS_STSCHG)?"STSCHG ":"",
++ (state->flags==0)?"<NONE> ":"",
++ (state->flags&SS_PWR_AUTO)?"PWR_AUTO ":"",
++ (state->flags&SS_IOCARD)?"IOCARD ":"",
++ (state->flags&SS_RESET)?"RESET ":"",
++ (state->flags&SS_SPKR_ENA)?"SPKR_ENA ":"",
++ (state->flags&SS_OUTPUT_ENA)?"OUTPUT_ENA ":"",
++ state->Vcc, state->Vpp, state->io_irq);
++
++ /*
++ * TODO: Allow boards to override this in case they have level
++ * converters.
++ */
++ switch (state->Vcc) {
++ case 0:
++ if (cf->vcc_pin >= 0)
++ gpio_set_value(cf->vcc_pin, 0);
++ break;
++ case 33:
++ if (cf->vcc_pin >= 0)
++ gpio_set_value(cf->vcc_pin, 1);
++ break;
++ default:
++ return -EINVAL;
+ }
-+}
+
-+/*
-+ * status flags interrupt handler.
-+ */
-+static void
-+atmel_handle_status(struct uart_port *port, unsigned int pending,
-+ unsigned int status)
-+{
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
++ if (cf->reset_pin >= 0)
++ gpio_set_value(cf->reset_pin, state->flags & SS_RESET);
+
-+ if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
-+ | ATMEL_US_CTSIC)) {
-+ atmel_port->irq_status = status;
-+ tasklet_schedule(&atmel_port->tasklet);
-+ }
- }
-
- /*
-@@ -355,47 +536,255 @@
- static irqreturn_t atmel_interrupt(int irq, void *dev_id)
- {
- struct uart_port *port = dev_id;
-- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
- unsigned int status, pending, pass_counter = 0;
-
-- status = UART_GET_CSR(port);
-- pending = status & UART_GET_IMR(port);
-- while (pending) {
-- /* Interrupt receive */
-- if (pending & ATMEL_US_RXRDY)
-- atmel_rx_chars(port);
-- else if (pending & ATMEL_US_RXBRK) {
-+ do {
-+ status = UART_GET_CSR(port);
-+ pending = status & UART_GET_IMR(port);
-+ if (!pending)
-+ break;
++ cf->state = *state;
+
-+ atmel_handle_receive(port, pending);
-+ atmel_handle_status(port, pending, status);
-+ atmel_handle_transmit(port, pending);
-+ } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
++ return 0;
++}
+
-+ return IRQ_HANDLED;
++static int at32_cf_socket_init(struct pcmcia_socket *sock)
++{
++ debug(to_at32_cf(sock), 2, "called\n");
++
++ return 0;
+}
+
-+/*
-+ * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
-+ */
-+static void atmel_tx_dma(struct uart_port *port)
++static int at32_cf_suspend(struct pcmcia_socket *sock)
+{
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-+ struct circ_buf *xmit = &port->info->xmit;
-+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
-+ int count;
-+
-+ xmit->tail += pdc->ofs;
-+ xmit->tail &= UART_XMIT_SIZE - 1;
-+
-+ port->icount.tx += pdc->ofs;
-+ pdc->ofs = 0;
-+
-+ if (!uart_circ_empty(xmit)) {
-+ /* more to transmit - setup next transfer */
-+
-+ /* disable PDC transmit */
-+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
-+ dma_sync_single_for_device(port->dev,
-+ pdc->dma_addr,
-+ pdc->dma_size,
-+ DMA_TO_DEVICE);
-+
-+ count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
-+ pdc->ofs = count;
-+
-+ UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
-+ UART_PUT_TCR(port, count);
-+ /* re-enable PDC transmit and interrupts */
-+ UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
-+ UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
-+ } else {
-+ /* nothing left to transmit - disable the transmitter */
++ debug(to_at32_cf(sock), 2, "called\n");
+
-+ /* disable PDC transmit */
-+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
-+ }
++ at32_cf_set_socket(sock, &dead_socket);
+
-+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
-+ uart_write_wakeup(port);
++ return 0;
+}
+
-+static void atmel_rx_from_ring(struct uart_port *port)
++static int at32_cf_set_io_map(struct pcmcia_socket *sock,
++ struct pccard_io_map *map)
+{
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-+ struct circ_buf *ring = &atmel_port->rx_ring;
-+ unsigned int flg;
-+ unsigned int status;
-+
-+ while (ring->head != ring->tail) {
-+ struct atmel_uart_char c;
++ struct at32_cf_socket *cf = container_of(sock, struct at32_cf_socket, socket);
++ int retval;
+
-+ /* Make sure c is loaded after head. */
-+ smp_rmb();
++ debug(cf, 2, "map %u speed %u start 0x%08x stop 0x%08x\n",
++ map->map, map->speed, map->start, map->stop);
++ debug(cf, 2, "flags: %s%s%s%s%s%s%s%s\n",
++ (map->flags == 0) ? "<NONE>":"",
++ (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
++ (map->flags & MAP_16BIT) ? "16BIT " : "",
++ (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
++ (map->flags & MAP_0WS) ? "0WS " : "",
++ (map->flags & MAP_WRPROT) ? "WRPROT " : "",
++ (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
++ (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
+
-+ c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
++ map->flags &= MAP_ACTIVE | MAP_16BIT | MAP_USE_WAIT;
+
-+ ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
++ if (map->flags & MAP_16BIT)
++ cf->smc.bus_width = 2;
++ else
++ cf->smc.bus_width = 1;
+
-+ port->icount.rx++;
-+ status = c.status;
-+ flg = TTY_NORMAL;
++ if (map->flags & MAP_USE_WAIT)
++ cf->smc.nwait_mode = 3;
++ else
++ cf->smc.nwait_mode = 0;
+
-+ /*
-+ * note that the error handling code is
-+ * out of the main execution path
-+ */
-+ if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
-+ | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
-+ if (status & ATMEL_US_RXBRK) {
-+ /* ignore side-effect */
-+ status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
-+
-+ port->icount.brk++;
-+ if (uart_handle_break(port))
-+ continue;
-+ }
-+ if (status & ATMEL_US_PARE)
-+ port->icount.parity++;
-+ if (status & ATMEL_US_FRAME)
-+ port->icount.frame++;
-+ if (status & ATMEL_US_OVRE)
-+ port->icount.overrun++;
-+
-+ status &= port->read_status_mask;
-+
-+ if (status & ATMEL_US_RXBRK)
-+ flg = TTY_BREAK;
-+ else if (status & ATMEL_US_PARE)
-+ flg = TTY_PARITY;
-+ else if (status & ATMEL_US_FRAME)
-+ flg = TTY_FRAME;
-+ }
++ retval = smc_set_configuration(cf->cf_cs, &cf->smc);
++ if (retval) {
++ printk(KERN_ERR "at32_cf: could not set up SMC for I/O\n");
++ return retval;
++ }
+
++ map->start = cf->socket.io_offset;
++ map->stop = map->start + CF_RES_SIZE - 1;
+
-+ if (uart_handle_sysrq_char(port, c.ch))
-+ continue;
++ return 0;
++}
+
-+ uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
-+ }
++static int
++at32_cf_set_mem_map(struct pcmcia_socket *sock, struct pccard_mem_map *map)
++{
++ struct at32_cf_socket *cf;
++ struct resource *res;
++ int retval;
+
-+ /*
-+ * Drop the lock here since it might end up calling
-+ * uart_start(), which takes the lock.
-+ */
-+ spin_unlock(&port->lock);
-+ tty_flip_buffer_push(port->info->tty);
-+ spin_lock(&port->lock);
-+}
++ cf = container_of(sock, struct at32_cf_socket, socket);
+
-+static void atmel_rx_from_dma(struct uart_port *port)
-+{
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-+ struct tty_struct *tty = port->info->tty;
-+ struct atmel_dma_buffer *pdc;
-+ int rx_idx = atmel_port->pdc_rx_idx;
-+ unsigned int head;
-+ unsigned int tail;
-+ unsigned int count;
++ debug(cf, 2, "map %u speed %u card_start %08x\n",
++ map->map, map->speed, map->card_start);
++ debug(cf, 2, "flags: %s%s%s%s%s%s%s%s\n",
++ (map->flags==0)?"<NONE>":"",
++ (map->flags&MAP_ACTIVE)?"ACTIVE ":"",
++ (map->flags&MAP_16BIT)?"16BIT ":"",
++ (map->flags&MAP_AUTOSZ)?"AUTOSZ ":"",
++ (map->flags&MAP_0WS)?"0WS ":"",
++ (map->flags&MAP_WRPROT)?"WRPROT ":"",
++ (map->flags&MAP_ATTRIB)?"ATTRIB ":"",
++ (map->flags&MAP_USE_WAIT)?"USE_WAIT ":"");
+
-+ do {
-+ /* Reset the UART timeout early so that we don't miss one */
-+ UART_PUT_CR(port, ATMEL_US_STTTO);
-+
-+ pdc = &atmel_port->pdc_rx[rx_idx];
-+ head = UART_GET_RPR(port) - pdc->dma_addr;
-+ tail = pdc->ofs;
-+
-+ /* If the PDC has switched buffers, RPR won't contain
-+ * any address within the current buffer. Since head
-+ * is unsigned, we just need a one-way comparison to
-+ * find out.
-+ *
-+ * In this case, we just need to consume the entire
-+ * buffer and resubmit it for DMA. This will clear the
-+ * ENDRX bit as well, so that we can safely re-enable
-+ * all interrupts below.
-+ */
-+ head = min(head, pdc->dma_size);
-+
-+ if (likely(head != tail)) {
-+ dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
-+ pdc->dma_size, DMA_FROM_DEVICE);
-+
- /*
-- * End of break detected. If it came along
-- * with a character, atmel_rx_chars will
-- * handle it.
-+ * head will only wrap around when we recycle
-+ * the DMA buffer, and when that happens, we
-+ * explicitly set tail to 0. So head will
-+ * always be greater than tail.
- */
-- UART_PUT_CR(port, ATMEL_US_RSTSTA);
-- UART_PUT_IDR(port, ATMEL_US_RXBRK);
-- atmel_port->break_active = 0;
-+ count = head - tail;
++ if (map->card_start)
++ return -EINVAL;
+
-+ tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
++ map->flags &= MAP_ACTIVE | MAP_ATTRIB | MAP_16BIT | MAP_USE_WAIT;
+
-+ dma_sync_single_for_device(port->dev, pdc->dma_addr,
-+ pdc->dma_size, DMA_FROM_DEVICE);
++ if (map->flags & MAP_ATTRIB) {
++ res = &cf->res_attr;
+
-+ port->icount.rx += count;
-+ pdc->ofs = head;
-+ }
++ /* Linksys WCF12 seems to use WAIT when reading CIS */
++ map->flags |= MAP_USE_WAIT;
++ } else {
++ res = &cf->res_mem;
++ }
+
-+ /*
-+ * If the current buffer is full, we need to check if
-+ * the next one contains any additional data.
-+ */
-+ if (head >= pdc->dma_size) {
-+ pdc->ofs = 0;
-+ UART_PUT_RNPR(port, pdc->dma_addr);
-+ UART_PUT_RNCR(port, pdc->dma_size);
++ if (map->flags & MAP_USE_WAIT)
++ cf->smc.nwait_mode = 3;
++ else
++ cf->smc.nwait_mode = 0;
+
-+ rx_idx = !rx_idx;
-+ atmel_port->pdc_rx_idx = rx_idx;
- }
-+ } while (head >= pdc->dma_size);
++ retval = smc_set_configuration(cf->cf_cs, &cf->smc);
++ if (retval) {
++ printk(KERN_ERR "at32_cf: could not set up SMC for mem\n");
++ return retval;
++ }
+
-+ /*
-+ * Drop the lock here since it might end up calling
-+ * uart_start(), which takes the lock.
-+ */
-+ spin_unlock(&port->lock);
-+ tty_flip_buffer_push(tty);
-+ spin_lock(&port->lock);
++ map->static_start = res->start;
+
-+ UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
++ return 0;
+}
-
-- // TODO: All reads to CSR will clear these interrupts!
-- if (pending & ATMEL_US_RIIC) port->icount.rng++;
-- if (pending & ATMEL_US_DSRIC) port->icount.dsr++;
-- if (pending & ATMEL_US_DCDIC)
-+/*
-+ * tasklet handling tty stuff outside the interrupt handler.
-+ */
-+static void atmel_tasklet_func(unsigned long data)
++
++static struct pccard_operations at32_cf_ops = {
++ .init = at32_cf_socket_init,
++ .suspend = at32_cf_suspend,
++ .get_status = at32_cf_get_status,
++ .set_socket = at32_cf_set_socket,
++ .set_io_map = at32_cf_set_io_map,
++ .set_mem_map = at32_cf_set_mem_map,
++};
++
++static int __init request_pin(struct platform_device *pdev,
++ unsigned int pin, const char *name)
+{
-+ struct uart_port *port = (struct uart_port *)data;
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-+ unsigned int status;
-+ unsigned int status_change;
++ if (gpio_request(pin, name)) {
++ dev_warn(&pdev->dev, "failed to request %s pin\n", name);
++ return -1;
++ }
+
-+ /* The interrupt handler does not take the lock */
-+ spin_lock(&port->lock);
++ return pin;
++}
+
-+ if (atmel_use_dma_tx(port))
-+ atmel_tx_dma(port);
-+ else
-+ atmel_tx_chars(port);
-+
-+ status = atmel_port->irq_status;
-+ status_change = status ^ atmel_port->irq_status_prev;
-+
-+ if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
-+ | ATMEL_US_DCD | ATMEL_US_CTS)) {
-+ /* TODO: All reads to CSR will clear these interrupts! */
-+ if (status_change & ATMEL_US_RI)
-+ port->icount.rng++;
-+ if (status_change & ATMEL_US_DSR)
-+ port->icount.dsr++;
-+ if (status_change & ATMEL_US_DCD)
- uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
-- if (pending & ATMEL_US_CTSIC)
-+ if (status_change & ATMEL_US_CTS)
- uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
-- if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC))
-- wake_up_interruptible(&port->info->delta_msr_wait);
--
-- /* Interrupt transmit */
-- if (pending & ATMEL_US_TXRDY)
-- atmel_tx_chars(port);
-
-- if (pass_counter++ > ATMEL_ISR_PASS_LIMIT)
-- break;
-+ wake_up_interruptible(&port->info->delta_msr_wait);
-
-- status = UART_GET_CSR(port);
-- pending = status & UART_GET_IMR(port);
-+ atmel_port->irq_status_prev = status;
- }
-- return IRQ_HANDLED;
++static struct smc_timing at32_cf_timing __initdata = {
++ .ncs_read_setup = 30,
++ .nrd_setup = 100,
++ .ncs_write_setup = 30,
++ .nwe_setup = 100,
+
-+ if (atmel_use_dma_rx(port))
-+ atmel_rx_from_dma(port);
-+ else
-+ atmel_rx_from_ring(port);
++ .ncs_read_pulse = 360,
++ .nrd_pulse = 290,
++ .ncs_write_pulse = 360,
++ .nwe_pulse = 290,
+
-+ spin_unlock(&port->lock);
- }
-
- /*
-@@ -403,6 +792,8 @@
- */
- static int atmel_startup(struct uart_port *port)
- {
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-+ struct tty_struct *tty = port->info->tty;
- int retval;
-
- /*
-@@ -415,13 +806,64 @@
- /*
- * Allocate the IRQ
- */
-- retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, "atmel_serial", port);
-+ retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
-+ tty ? tty->name : "atmel_serial", port);
- if (retval) {
- printk("atmel_serial: atmel_startup - Can't get irq\n");
- return retval;
- }
-
- /*
-+ * Initialize DMA (if necessary)
-+ */
-+ if (atmel_use_dma_rx(port)) {
-+ int i;
-+
-+ for (i = 0; i < 2; i++) {
-+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
-+
-+ pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
-+ if (pdc->buf == NULL) {
-+ if (i != 0) {
-+ dma_unmap_single(port->dev,
-+ atmel_port->pdc_rx[0].dma_addr,
-+ PDC_BUFFER_SIZE,
-+ DMA_FROM_DEVICE);
-+ kfree(atmel_port->pdc_rx[0].buf);
-+ }
-+ free_irq(port->irq, port);
-+ return -ENOMEM;
-+ }
-+ pdc->dma_addr = dma_map_single(port->dev,
-+ pdc->buf,
-+ PDC_BUFFER_SIZE,
-+ DMA_FROM_DEVICE);
-+ pdc->dma_size = PDC_BUFFER_SIZE;
-+ pdc->ofs = 0;
-+ }
++ .read_cycle = 420,
++ .write_cycle = 420,
++};
+
-+ atmel_port->pdc_rx_idx = 0;
++static int __init at32_cf_probe(struct platform_device *pdev)
++{
++ struct at32_cf_socket *cf;
++ struct cf_platform_data *board = pdev->dev.platform_data;
++ struct resource *res_skt;
++ int irq;
++ int ret;
+
-+ UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
-+ UART_PUT_RCR(port, PDC_BUFFER_SIZE);
++ dev_dbg(&pdev->dev, "probe");
+
-+ UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
-+ UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
-+ }
-+ if (atmel_use_dma_tx(port)) {
-+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
-+ struct circ_buf *xmit = &port->info->xmit;
-+
-+ pdc->buf = xmit->buf;
-+ pdc->dma_addr = dma_map_single(port->dev,
-+ pdc->buf,
-+ UART_XMIT_SIZE,
-+ DMA_TO_DEVICE);
-+ pdc->dma_size = UART_XMIT_SIZE;
-+ pdc->ofs = 0;
-+ }
++ if (!board)
++ return -ENXIO;
+
-+ /*
- * If there is a specific "open" function (to register
- * control line interrupts)
- */
-@@ -437,9 +879,21 @@
- * Finally, enable the serial port
- */
- UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
-- UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */
-+ /* enable xmit & rcvr */
-+ UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
-
-- UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */
-+ if (atmel_use_dma_rx(port)) {
-+ /* set UART timeout */
-+ UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
-+ UART_PUT_CR(port, ATMEL_US_STTTO);
-+
-+ UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
-+ /* enable PDC controller */
-+ UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
-+ } else {
-+ /* enable receive only */
-+ UART_PUT_IER(port, ATMEL_US_RXRDY);
-+ }
-
- return 0;
- }
-@@ -449,6 +903,38 @@
- */
- static void atmel_shutdown(struct uart_port *port)
- {
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-+ /*
-+ * Ensure everything is stopped.
-+ */
-+ atmel_stop_rx(port);
-+ atmel_stop_tx(port);
++ res_skt = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res_skt)
++ return -ENXIO;
+
-+ /*
-+ * Shut-down the DMA.
-+ */
-+ if (atmel_use_dma_rx(port)) {
-+ int i;
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0)
++ return irq;
+
-+ for (i = 0; i < 2; i++) {
-+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
++ cf = kzalloc(sizeof(struct at32_cf_socket), GFP_KERNEL);
++ if (!cf)
++ return -ENOMEM;
+
-+ dma_unmap_single(port->dev,
-+ pdc->dma_addr,
-+ pdc->dma_size,
-+ DMA_FROM_DEVICE);
-+ kfree(pdc->buf);
-+ }
-+ }
-+ if (atmel_use_dma_tx(port)) {
-+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
++ cf->detect_pin = -1;
++ cf->reset_pin = -1;
++ cf->vcc_pin = -1;
++ cf->ready_pin = -1;
++ cf->cf_cs = board->cs;
+
-+ dma_unmap_single(port->dev,
-+ pdc->dma_addr,
-+ pdc->dma_size,
-+ DMA_TO_DEVICE);
-+ }
++ if (board->detect_pin != GPIO_PIN_NONE)
++ cf->detect_pin = request_pin(pdev, board->detect_pin,
++ "cf_detect");
++ if (board->reset_pin != GPIO_PIN_NONE)
++ cf->reset_pin = request_pin(pdev, board->reset_pin,
++ "cf_reset");
++ if (board->vcc_pin != GPIO_PIN_NONE)
++ cf->vcc_pin = request_pin(pdev, board->vcc_pin,
++ "cf_vcc");
++ if (board->ready_pin != GPIO_PIN_NONE)
++ /* READY is also used for irq through EIM */
++ cf->ready_pin = board->ready_pin;
+
- /*
- * Disable all interrupts, port and break condition.
- */
-@@ -471,45 +957,48 @@
- /*
- * Power / Clock management.
- */
--static void atmel_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
-+static void atmel_serial_pm(struct uart_port *port, unsigned int state,
-+ unsigned int oldstate)
- {
-- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-
- switch (state) {
-- case 0:
-- /*
-- * Enable the peripheral clock for this serial port.
-- * This is called on uart_open() or a resume event.
-- */
-- clk_enable(atmel_port->clk);
-- break;
-- case 3:
-- /*
-- * Disable the peripheral clock for this serial port.
-- * This is called on uart_close() or a suspend event.
-- */
-- clk_disable(atmel_port->clk);
-- break;
-- default:
-- printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
-+ case 0:
-+ /*
-+ * Enable the peripheral clock for this serial port.
-+ * This is called on uart_open() or a resume event.
-+ */
-+ clk_enable(atmel_port->clk);
-+ break;
-+ case 3:
-+ /*
-+ * Disable the peripheral clock for this serial port.
-+ * This is called on uart_close() or a suspend event.
-+ */
-+ clk_disable(atmel_port->clk);
-+ break;
-+ default:
-+ printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
- }
- }
-
- /*
- * Change the port parameters
- */
--static void atmel_set_termios(struct uart_port *port, struct ktermios * termios, struct ktermios * old)
-+static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
-+ struct ktermios *old)
- {
- unsigned long flags;
- unsigned int mode, imr, quot, baud;
-
- /* Get current mode register */
-- mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
-+ mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
-+ | ATMEL_US_NBSTOP | ATMEL_US_PAR);
-
-- baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
-+ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
- quot = uart_get_divisor(port, baud);
-
-- if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
-+ if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
- quot /= 8;
- mode |= ATMEL_US_USCLKS_MCK_DIV8;
- }
-@@ -536,18 +1025,17 @@
-
- /* parity */
- if (termios->c_cflag & PARENB) {
-- if (termios->c_cflag & CMSPAR) { /* Mark or Space parity */
-+ /* Mark or Space parity */
-+ if (termios->c_cflag & CMSPAR) {
- if (termios->c_cflag & PARODD)
- mode |= ATMEL_US_PAR_MARK;
- else
- mode |= ATMEL_US_PAR_SPACE;
-- }
-- else if (termios->c_cflag & PARODD)
-+ } else if (termios->c_cflag & PARODD)
- mode |= ATMEL_US_PAR_ODD;
- else
- mode |= ATMEL_US_PAR_EVEN;
-- }
-- else
-+ } else
- mode |= ATMEL_US_PAR_NONE;
-
- spin_lock_irqsave(&port->lock, flags);
-@@ -558,6 +1046,10 @@
- if (termios->c_iflag & (BRKINT | PARMRK))
- port->read_status_mask |= ATMEL_US_RXBRK;
-
-+ if (atmel_use_dma_rx(port))
-+ /* need to enable error interrupts */
-+ UART_PUT_IER(port, port->read_status_mask);
++ debug(cf, 2, "pins: detect=%d reset=%d vcc=%d\n",
++ cf->detect_pin, cf->reset_pin, cf->vcc_pin);
+
- /*
- * Characters to ignore
- */
-@@ -573,16 +1065,16 @@
- if (termios->c_iflag & IGNPAR)
- port->ignore_status_mask |= ATMEL_US_OVRE;
- }
--
-- // TODO: Ignore all characters if CREAD is set.
-+ /* TODO: Ignore all characters if CREAD is set.*/
-
- /* update the per-port timeout */
- uart_update_timeout(port, termios->c_cflag, baud);
-
-- /* disable interrupts and drain transmitter */
-- imr = UART_GET_IMR(port); /* get interrupt mask */
-- UART_PUT_IDR(port, -1); /* disable all interrupts */
-- while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) { barrier(); }
-+ /* save/disable interrupts and drain transmitter */
-+ imr = UART_GET_IMR(port);
-+ UART_PUT_IDR(port, -1);
-+ while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
-+ cpu_relax();
-
- /* disable receiver and transmitter */
- UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
-@@ -708,7 +1200,8 @@
- /*
- * Configure the port from the platform device resource info.
- */
--static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, struct platform_device *pdev)
-+static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
-+ struct platform_device *pdev)
- {
- struct uart_port *port = &atmel_port->uart;
- struct atmel_uart_data *data = pdev->dev.platform_data;
-@@ -723,6 +1216,11 @@
- port->mapbase = pdev->resource[0].start;
- port->irq = pdev->resource[1].start;
-
-+ tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
-+ (unsigned long)port);
-+
-+ memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
-+
- if (data->regs)
- /* Already mapped by setup code */
- port->membase = data->regs;
-@@ -731,11 +1229,17 @@
- port->membase = NULL;
- }
-
-- if (!atmel_port->clk) { /* for console, the clock could already be configured */
-+ /* for console, the clock could already be configured */
-+ if (!atmel_port->clk) {
- atmel_port->clk = clk_get(&pdev->dev, "usart");
- clk_enable(atmel_port->clk);
- port->uartclk = clk_get_rate(atmel_port->clk);
- }
++ cf->socket.pci_irq = irq;
++ cf->socket.ops = &at32_cf_ops;
++ cf->socket.resource_ops = &pccard_static_ops;
++ cf->socket.dev.parent = &pdev->dev;
++ cf->socket.owner = THIS_MODULE;
++ cf->socket.features =
++ SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP | SS_CAP_PCCARD;
++ cf->socket.map_size = CF_RES_SIZE;
+
-+ atmel_port->use_dma_rx = data->use_dma_rx;
-+ atmel_port->use_dma_tx = data->use_dma_tx;
-+ if (atmel_use_dma_tx(port))
-+ port->fifosize = PDC_BUFFER_SIZE;
- }
-
- /*
-@@ -755,12 +1259,11 @@
- atmel_pops.set_wake = fns->set_wake;
- }
-
--
- #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
- static void atmel_console_putchar(struct uart_port *port, int ch)
- {
- while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
-- barrier();
-+ cpu_relax();
- UART_PUT_CHAR(port, ch);
- }
-
-@@ -773,38 +1276,40 @@
- unsigned int status, imr;
-
- /*
-- * First, save IMR and then disable interrupts
-+ * First, save IMR and then disable interrupts
- */
-- imr = UART_GET_IMR(port); /* get interrupt mask */
-+ imr = UART_GET_IMR(port);
- UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY);
-
- uart_console_write(port, s, count, atmel_console_putchar);
-
- /*
-- * Finally, wait for transmitter to become empty
-- * and restore IMR
-+ * Finally, wait for transmitter to become empty
-+ * and restore IMR
- */
- do {
- status = UART_GET_CSR(port);
- } while (!(status & ATMEL_US_TXRDY));
-- UART_PUT_IER(port, imr); /* set interrupts back the way they were */
-+ /* set interrupts back the way they were */
-+ UART_PUT_IER(port, imr);
- }
-
- /*
-- * If the port was already initialised (eg, by a boot loader), try to determine
-- * the current setup.
-+ * If the port was already initialised (eg, by a boot loader),
-+ * try to determine the current setup.
- */
--static void __init atmel_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
-+static void __init atmel_console_get_options(struct uart_port *port, int *baud,
-+ int *parity, int *bits)
- {
- unsigned int mr, quot;
-
--// TODO: CR is a write-only register
--// unsigned int cr;
--//
--// cr = UART_GET_CR(port) & (ATMEL_US_RXEN | ATMEL_US_TXEN);
--// if (cr == (ATMEL_US_RXEN | ATMEL_US_TXEN)) {
--// /* ok, the port was enabled */
--// }
-+ /*
-+ * If the baud rate generator isn't running, the port wasn't
-+ * initialized by the boot loader.
-+ */
-+ quot = UART_GET_BRGR(port);
-+ if (!quot)
-+ return;
-
- mr = UART_GET_MR(port) & ATMEL_US_CHRL;
- if (mr == ATMEL_US_CHRL_8)
-@@ -824,7 +1329,6 @@
- * lower than one of those, as it would make us fall through
- * to a much lower baud rate than we really want.
- */
-- quot = UART_GET_BRGR(port);
- *baud = port->uartclk / (16 * (quot - 1));
- }
-
-@@ -836,10 +1340,12 @@
- int parity = 'n';
- int flow = 'n';
-
-- if (port->membase == 0) /* Port not initialized yet - delay setup */
-+ if (port->membase == NULL) {
-+ /* Port not initialized yet - delay setup */
- return -ENODEV;
++ cf->res_attr.start = res_skt->start + CF_ATTR_OFFSET;
++ cf->res_attr.end = cf->res_attr.start + CF_RES_SIZE - 1;
++ cf->res_attr.name = "attribute";
++ cf->res_attr.flags = IORESOURCE_MEM;
++ ret = request_resource(res_skt, &cf->res_attr);
++ if (ret)
++ goto err_request_res_attr;
++
++ cf->res_mem.start = res_skt->start + CF_MEM_OFFSET;
++ cf->res_mem.end = cf->res_mem.start + CF_RES_SIZE - 1;
++ cf->res_mem.name = "memory";
++ cf->res_mem.flags = IORESOURCE_MEM;
++ ret = request_resource(res_skt, &cf->res_mem);
++ if (ret)
++ goto err_request_res_mem;
++
++ cf->res_io.start = res_skt->start + CF_IO_OFFSET;
++ cf->res_io.end = cf->res_io.start + CF_RES_SIZE - 1;
++ cf->res_io.name = "io";
++ cf->res_io.flags = IORESOURCE_MEM;
++ ret = request_resource(res_skt, &cf->res_io);
++ if (ret)
++ goto err_request_res_io;
++
++ cf->socket.io_offset = cf->res_io.start;
++
++ if (cf->detect_pin >= 0) {
++ ret = request_irq(gpio_to_irq(cf->detect_pin), at32_cf_irq,
++ IRQF_SHARED, "cf_detect", cf);
++ if (ret) {
++ debug(cf, 1,
++ "failed to request cf_detect interrupt\n");
++ goto err_detect_irq;
++ }
+ }
-
-- UART_PUT_IDR(port, -1); /* disable interrupts */
-+ UART_PUT_IDR(port, -1);
- UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
- UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
-
-@@ -871,13 +1377,16 @@
- static int __init atmel_console_init(void)
- {
- if (atmel_default_console_device) {
-- add_preferred_console(ATMEL_DEVICENAME, atmel_default_console_device->id, NULL);
-- atmel_init_port(&(atmel_ports[atmel_default_console_device->id]), atmel_default_console_device);
-+ add_preferred_console(ATMEL_DEVICENAME,
-+ atmel_default_console_device->id, NULL);
-+ atmel_init_port(&atmel_ports[atmel_default_console_device->id],
-+ atmel_default_console_device);
- register_console(&atmel_console);
- }
-
- return 0;
- }
+
- console_initcall(atmel_console_init);
-
- /*
-@@ -885,34 +1394,48 @@
- */
- static int __init atmel_late_console_init(void)
- {
-- if (atmel_default_console_device && !(atmel_console.flags & CON_ENABLED))
-+ if (atmel_default_console_device
-+ && !(atmel_console.flags & CON_ENABLED))
- register_console(&atmel_console);
-
- return 0;
- }
++ cf->present = at32_cf_present(cf);
+
- core_initcall(atmel_late_console_init);
-
-+static inline bool atmel_is_console_port(struct uart_port *port)
-+{
-+ return port->cons && port->cons->index == port->line;
-+}
++ /* Setup SMC timings */
++ smc_set_timing(&cf->smc, &at32_cf_timing);
+
- #else
- #define ATMEL_CONSOLE_DEVICE NULL
++ cf->smc.bus_width = 2;
++ cf->smc.nrd_controlled = 1;
++ cf->smc.nwe_controlled = 1;
++ cf->smc.nwait_mode = 0;
++ cf->smc.byte_write = 0;
++ cf->smc.tdf_cycles = 8;
++ cf->smc.tdf_mode = 0;
+
-+static inline bool atmel_is_console_port(struct uart_port *port)
-+{
-+ return false;
-+}
- #endif
-
- static struct uart_driver atmel_uart = {
-- .owner = THIS_MODULE,
-- .driver_name = "atmel_serial",
-- .dev_name = ATMEL_DEVICENAME,
-- .major = SERIAL_ATMEL_MAJOR,
-- .minor = MINOR_START,
-- .nr = ATMEL_MAX_UART,
-- .cons = ATMEL_CONSOLE_DEVICE,
-+ .owner = THIS_MODULE,
-+ .driver_name = "atmel_serial",
-+ .dev_name = ATMEL_DEVICENAME,
-+ .major = SERIAL_ATMEL_MAJOR,
-+ .minor = MINOR_START,
-+ .nr = ATMEL_MAX_UART,
-+ .cons = ATMEL_CONSOLE_DEVICE,
- };
-
- #ifdef CONFIG_PM
--static int atmel_serial_suspend(struct platform_device *pdev, pm_message_t state)
-+static int atmel_serial_suspend(struct platform_device *pdev,
-+ pm_message_t state)
- {
- struct uart_port *port = platform_get_drvdata(pdev);
-- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-
-- if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock())
-+ if (device_may_wakeup(&pdev->dev)
-+ && !at91_suspend_entering_slow_clock())
- enable_irq_wake(port->irq);
- else {
- uart_suspend_port(&atmel_uart, port);
-@@ -925,13 +1448,12 @@
- static int atmel_serial_resume(struct platform_device *pdev)
- {
- struct uart_port *port = platform_get_drvdata(pdev);
-- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
-
- if (atmel_port->suspended) {
- uart_resume_port(&atmel_uart, port);
- atmel_port->suspended = 0;
-- }
-- else
-+ } else
- disable_irq_wake(port->irq);
-
- return 0;
-@@ -944,15 +1466,40 @@
- static int __devinit atmel_serial_probe(struct platform_device *pdev)
- {
- struct atmel_uart_port *port;
-+ void *data;
- int ret;
-
-+ BUILD_BUG_ON(!is_power_of_2(ATMEL_SERIAL_RINGSIZE));
++ ret = smc_set_configuration(cf->cf_cs, &cf->smc);
++ if (ret) {
++ debug(cf, 1, "failed to configure SMC\n", ret);
++ goto err_smc;
++ }
+
- port = &atmel_ports[pdev->id];
- atmel_init_port(port, pdev);
-
-+ if (!atmel_use_dma_rx(&port->uart)) {
-+ ret = -ENOMEM;
-+ data = kmalloc(sizeof(struct atmel_uart_char)
-+ * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
-+ if (!data)
-+ goto err_alloc_ring;
-+ port->rx_ring.buf = data;
++ ret = pcmcia_register_socket(&cf->socket);
++ if (ret) {
++ debug(cf, 1, "failed to register socket: %d\n", ret);
++ goto err_register_socket;
+ }
+
- ret = uart_add_one_port(&atmel_uart, &port->uart);
-- if (!ret) {
-- device_init_wakeup(&pdev->dev, 1);
-- platform_set_drvdata(pdev, port);
-+ if (ret)
-+ goto err_add_port;
++ if (cf->reset_pin >= 0)
++ gpio_direction_output(cf->reset_pin, 0);
+
-+ device_init_wakeup(&pdev->dev, 1);
-+ platform_set_drvdata(pdev, port);
++ platform_set_drvdata(pdev, cf);
++
++ dev_info(&pdev->dev, "Atmel SMC CF interface at 0x%08lx\n",
++ (unsigned long)res_skt->start);
+
+ return 0;
+
-+err_add_port:
-+ kfree(port->rx_ring.buf);
-+ port->rx_ring.buf = NULL;
-+err_alloc_ring:
-+ if (!atmel_is_console_port(&port->uart)) {
-+ clk_disable(port->clk);
-+ clk_put(port->clk);
-+ port->clk = NULL;
- }
-
- return ret;
-@@ -961,19 +1508,21 @@
- static int __devexit atmel_serial_remove(struct platform_device *pdev)
- {
- struct uart_port *port = platform_get_drvdata(pdev);
-- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
-+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
- int ret = 0;
-
-- clk_disable(atmel_port->clk);
-- clk_put(atmel_port->clk);
--
- device_init_wakeup(&pdev->dev, 0);
- platform_set_drvdata(pdev, NULL);
-
-- if (port) {
-- ret = uart_remove_one_port(&atmel_uart, port);
-- kfree(port);
-- }
-+ ret = uart_remove_one_port(&atmel_uart, port);
++err_register_socket:
++err_smc:
++ if (cf->detect_pin >= 0)
++ free_irq(gpio_to_irq(cf->detect_pin), cf);
++err_detect_irq:
++ release_resource(&cf->res_io);
++err_request_res_io:
++ release_resource(&cf->res_mem);
++err_request_res_mem:
++ release_resource(&cf->res_attr);
++err_request_res_attr:
++ if (cf->vcc_pin >= 0)
++ gpio_free(cf->vcc_pin);
++ if (cf->reset_pin >= 0)
++ gpio_free(cf->reset_pin);
++ if (cf->detect_pin >= 0)
++ gpio_free(cf->detect_pin);
++ kfree(cf);
+
-+ tasklet_kill(&atmel_port->tasklet);
-+ kfree(atmel_port->rx_ring.buf);
++ return ret;
++}
+
-+ /* "port" is allocated statically, so we shouldn't free it */
++static int __exit at32_cf_remove(struct platform_device *pdev)
++{
++ struct at32_cf_socket *cf = platform_get_drvdata(pdev);
+
-+ clk_disable(atmel_port->clk);
-+ clk_put(atmel_port->clk);
-
- return ret;
- }
---- a/drivers/serial/atmel_serial.h
-+++ /dev/null
-@@ -1,127 +0,0 @@
--/*
-- * drivers/serial/atmel_serial.h
-- *
-- * Copyright (C) 2005 Ivan Kokshaysky
-- * Copyright (C) SAN People
-- *
-- * USART registers.
-- * Based on AT91RM9200 datasheet revision E.
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; either version 2 of the License, or
-- * (at your option) any later version.
-- */
--
--#ifndef ATMEL_SERIAL_H
--#define ATMEL_SERIAL_H
--
--#define ATMEL_US_CR 0x00 /* Control Register */
--#define ATMEL_US_RSTRX (1 << 2) /* Reset Receiver */
--#define ATMEL_US_RSTTX (1 << 3) /* Reset Transmitter */
--#define ATMEL_US_RXEN (1 << 4) /* Receiver Enable */
--#define ATMEL_US_RXDIS (1 << 5) /* Receiver Disable */
--#define ATMEL_US_TXEN (1 << 6) /* Transmitter Enable */
--#define ATMEL_US_TXDIS (1 << 7) /* Transmitter Disable */
--#define ATMEL_US_RSTSTA (1 << 8) /* Reset Status Bits */
--#define ATMEL_US_STTBRK (1 << 9) /* Start Break */
--#define ATMEL_US_STPBRK (1 << 10) /* Stop Break */
--#define ATMEL_US_STTTO (1 << 11) /* Start Time-out */
--#define ATMEL_US_SENDA (1 << 12) /* Send Address */
--#define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */
--#define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
--#define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */
--#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */
--#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */
--#define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */
--#define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */
--
--#define ATMEL_US_MR 0x04 /* Mode Register */
--#define ATMEL_US_USMODE (0xf << 0) /* Mode of the USART */
--#define ATMEL_US_USMODE_NORMAL 0
--#define ATMEL_US_USMODE_RS485 1
--#define ATMEL_US_USMODE_HWHS 2
--#define ATMEL_US_USMODE_MODEM 3
--#define ATMEL_US_USMODE_ISO7816_T0 4
--#define ATMEL_US_USMODE_ISO7816_T1 6
--#define ATMEL_US_USMODE_IRDA 8
--#define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */
--#define ATMEL_US_USCLKS_MCK (0 << 4)
--#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
--#define ATMEL_US_USCLKS_SCK (3 << 4)
--#define ATMEL_US_CHRL (3 << 6) /* Character Length */
--#define ATMEL_US_CHRL_5 (0 << 6)
--#define ATMEL_US_CHRL_6 (1 << 6)
--#define ATMEL_US_CHRL_7 (2 << 6)
--#define ATMEL_US_CHRL_8 (3 << 6)
--#define ATMEL_US_SYNC (1 << 8) /* Synchronous Mode Select */
--#define ATMEL_US_PAR (7 << 9) /* Parity Type */
--#define ATMEL_US_PAR_EVEN (0 << 9)
--#define ATMEL_US_PAR_ODD (1 << 9)
--#define ATMEL_US_PAR_SPACE (2 << 9)
--#define ATMEL_US_PAR_MARK (3 << 9)
--#define ATMEL_US_PAR_NONE (4 << 9)
--#define ATMEL_US_PAR_MULTI_DROP (6 << 9)
--#define ATMEL_US_NBSTOP (3 << 12) /* Number of Stop Bits */
--#define ATMEL_US_NBSTOP_1 (0 << 12)
--#define ATMEL_US_NBSTOP_1_5 (1 << 12)
--#define ATMEL_US_NBSTOP_2 (2 << 12)
--#define ATMEL_US_CHMODE (3 << 14) /* Channel Mode */
--#define ATMEL_US_CHMODE_NORMAL (0 << 14)
--#define ATMEL_US_CHMODE_ECHO (1 << 14)
--#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14)
--#define ATMEL_US_CHMODE_REM_LOOP (3 << 14)
--#define ATMEL_US_MSBF (1 << 16) /* Bit Order */
--#define ATMEL_US_MODE9 (1 << 17) /* 9-bit Character Length */
--#define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */
--#define ATMEL_US_OVER (1 << 19) /* Oversampling Mode */
--#define ATMEL_US_INACK (1 << 20) /* Inhibit Non Acknowledge */
--#define ATMEL_US_DSNACK (1 << 21) /* Disable Successive NACK */
--#define ATMEL_US_MAX_ITER (7 << 24) /* Max Iterations */
--#define ATMEL_US_FILTER (1 << 28) /* Infrared Receive Line Filter */
--
--#define ATMEL_US_IER 0x08 /* Interrupt Enable Register */
--#define ATMEL_US_RXRDY (1 << 0) /* Receiver Ready */
--#define ATMEL_US_TXRDY (1 << 1) /* Transmitter Ready */
--#define ATMEL_US_RXBRK (1 << 2) /* Break Received / End of Break */
--#define ATMEL_US_ENDRX (1 << 3) /* End of Receiver Transfer */
--#define ATMEL_US_ENDTX (1 << 4) /* End of Transmitter Transfer */
--#define ATMEL_US_OVRE (1 << 5) /* Overrun Error */
--#define ATMEL_US_FRAME (1 << 6) /* Framing Error */
--#define ATMEL_US_PARE (1 << 7) /* Parity Error */
--#define ATMEL_US_TIMEOUT (1 << 8) /* Receiver Time-out */
--#define ATMEL_US_TXEMPTY (1 << 9) /* Transmitter Empty */
--#define ATMEL_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */
--#define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
--#define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */
--#define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */
--#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */
--#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */
--#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */
--#define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */
--#define ATMEL_US_RI (1 << 20) /* RI */
--#define ATMEL_US_DSR (1 << 21) /* DSR */
--#define ATMEL_US_DCD (1 << 22) /* DCD */
--#define ATMEL_US_CTS (1 << 23) /* CTS */
--
--#define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */
--#define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */
--#define ATMEL_US_CSR 0x14 /* Channel Status Register */
--#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
--#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
--#define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */
--
--#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
--#define ATMEL_US_CD (0xffff << 0) /* Clock Divider */
--
--#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */
--#define ATMEL_US_TO (0xffff << 0) /* Time-out Value */
--
--#define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */
--#define ATMEL_US_TG (0xff << 0) /* Timeguard Value */
--
--#define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */
--#define ATMEL_US_NER 0x44 /* Number of Errors Register */
--#define ATMEL_US_IF 0x4c /* IrDA Filter Register */
--
--#endif
---- a/drivers/serial/Kconfig
-+++ b/drivers/serial/Kconfig
-@@ -380,6 +380,21 @@
- console is the device which receives all kernel messages and
- warnings and which allows logins in single user mode).
-
-+config SERIAL_ATMEL_PDC
-+ bool "Support DMA transfers on AT91 / AT32 serial port"
-+ depends on SERIAL_ATMEL
-+ default y
-+ help
-+ Say Y here if you wish to use the PDC to do DMA transfers to
-+ and from the Atmel AT91 / AT32 serial port. In order to
-+ actually use DMA transfers, make sure that the use_dma_tx
-+ and use_dma_rx members in the atmel_uart_data struct is set
-+ appropriately for each port.
-+
-+ Note that break and error handling currently doesn't work
-+ properly when DMA is enabled. Make sure that ports where
-+ this matters don't use DMA.
-+
- config SERIAL_ATMEL_TTYAT
- bool "Install as device ttyATn instead of ttySn"
- depends on SERIAL_ATMEL=y
---- a/drivers/spi/atmel_spi.c
-+++ b/drivers/spi/atmel_spi.c
-@@ -51,7 +51,9 @@
- u8 stopping;
- struct list_head queue;
- struct spi_transfer *current_transfer;
-- unsigned long remaining_bytes;
-+ unsigned long current_remaining_bytes;
-+ struct spi_transfer *next_transfer;
-+ unsigned long next_remaining_bytes;
-
- void *buffer;
- dma_addr_t buffer_dma;
-@@ -113,6 +115,16 @@
- unsigned gpio = (unsigned) spi->controller_data;
- unsigned active = spi->mode & SPI_CS_HIGH;
- u32 mr;
-+ int i;
-+ u32 csr;
-+ u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
-+
-+ /* Make sure clock polarity is correct */
-+ for (i = 0; i < spi->master->num_chipselect; i++) {
-+ csr = spi_readl(as, CSR0 + 4 * i);
-+ if ((csr ^ cpol) & SPI_BIT(CPOL))
-+ spi_writel(as, CSR0 + 4 * i, csr ^ SPI_BIT(CPOL));
++ pcmcia_unregister_socket(&cf->socket);
++ if (cf->detect_pin >= 0) {
++ free_irq(gpio_to_irq(cf->detect_pin), cf);
++ gpio_free(cf->detect_pin);
+ }
-
- /* only deactivate *this* device; sometimes transfers to
- * another device may be active when this routine is called.
-@@ -131,6 +143,48 @@
- gpio_set_value(gpio, !active);
- }
-
-+static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
-+ struct spi_transfer *xfer)
-+{
-+ return msg->transfers.prev == &xfer->transfer_list;
-+}
++ if (cf->vcc_pin >= 0)
++ gpio_free(cf->vcc_pin);
++ if (cf->reset_pin >= 0)
++ gpio_free(cf->reset_pin);
+
-+static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
-+{
-+ return xfer->delay_usecs == 0 && !xfer->cs_change;
++ release_resource(&cf->res_io);
++ release_resource(&cf->res_mem);
++ release_resource(&cf->res_attr);
++ kfree(cf);
++ platform_set_drvdata(pdev, NULL);
++
++ return 0;
+}
+
-+static void atmel_spi_next_xfer_data(struct spi_master *master,
-+ struct spi_transfer *xfer,
-+ dma_addr_t *tx_dma,
-+ dma_addr_t *rx_dma,
-+ u32 *plen)
++static struct platform_driver at32_cf_driver = {
++ .remove = __exit_p(at32_cf_remove),
++ .driver = {
++ .name = "at32_cf",
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init at32_cf_init(void)
+{
-+ struct atmel_spi *as = spi_master_get_devdata(master);
-+ u32 len = *plen;
++ int ret;
+
-+ /* use scratch buffer only when rx or tx data is unspecified */
-+ if (xfer->rx_buf)
-+ *rx_dma = xfer->rx_dma + xfer->len - len;
-+ else {
-+ *rx_dma = as->buffer_dma;
-+ if (len > BUFFER_SIZE)
-+ len = BUFFER_SIZE;
-+ }
-+ if (xfer->tx_buf)
-+ *tx_dma = xfer->tx_dma + xfer->len - len;
-+ else {
-+ *tx_dma = as->buffer_dma;
-+ if (len > BUFFER_SIZE)
-+ len = BUFFER_SIZE;
-+ memset(as->buffer, 0, len);
-+ dma_sync_single_for_device(&as->pdev->dev,
-+ as->buffer_dma, len, DMA_TO_DEVICE);
-+ }
++ ret = platform_driver_probe(&at32_cf_driver, at32_cf_probe);
++ if (ret)
++ printk(KERN_ERR "at32_cf: probe failed: %d\n", ret);
++ return ret;
++}
+
-+ *plen = len;
++static void __exit at32_cf_exit(void)
++{
++ platform_driver_unregister(&at32_cf_driver);
+}
+
- /*
- * Submit next transfer for DMA.
- * lock is held, spi irq is blocked
-@@ -140,53 +194,78 @@
++module_init(at32_cf_init);
++module_exit(at32_cf_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Driver for SMC PCMCIA interface");
++MODULE_AUTHOR("Hans-Christian Egtvedt <hcegtvedt@atmel.com>");
+--- a/drivers/rtc/rtc-at32ap700x.c
++++ b/drivers/rtc/rtc-at32ap700x.c
+@@ -262,6 +262,7 @@
+ }
+
+ platform_set_drvdata(pdev, rtc);
++ device_init_wakeup(&pdev->dev, 1);
+
+ dev_info(&pdev->dev, "Atmel RTC for AT32AP700x at %08lx irq %ld\n",
+ (unsigned long)rtc->regs, rtc->irq);
+@@ -281,6 +282,8 @@
{
- struct atmel_spi *as = spi_master_get_devdata(master);
- struct spi_transfer *xfer;
-- u32 len;
-+ u32 len, remaining, total;
- dma_addr_t tx_dma, rx_dma;
+ struct rtc_at32ap700x *rtc = platform_get_drvdata(pdev);
-- xfer = as->current_transfer;
-- if (!xfer || as->remaining_bytes == 0) {
-- if (xfer)
-- xfer = list_entry(xfer->transfer_list.next,
-- struct spi_transfer, transfer_list);
-- else
-- xfer = list_entry(msg->transfers.next,
-- struct spi_transfer, transfer_list);
-- as->remaining_bytes = xfer->len;
-- as->current_transfer = xfer;
-+ if (!as->current_transfer)
-+ xfer = list_entry(msg->transfers.next,
-+ struct spi_transfer, transfer_list);
-+ else if (!as->next_transfer)
-+ xfer = list_entry(as->current_transfer->transfer_list.next,
-+ struct spi_transfer, transfer_list);
-+ else
-+ xfer = NULL;
++ device_init_wakeup(&pdev->dev, 0);
+
-+ if (xfer) {
-+ len = xfer->len;
-+ atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
-+ remaining = xfer->len - len;
+ free_irq(rtc->irq, rtc);
+ iounmap(rtc->regs);
+ rtc_device_unregister(rtc->rtc);
+--- a/drivers/serial/atmel_serial.c
++++ b/drivers/serial/atmel_serial.c
+@@ -957,6 +957,20 @@
+ }
+
+ /*
++ * Flush any TX data submitted for DMA. Called when the TX circular
++ * buffer is reset.
++ */
++static void atmel_flush_buffer(struct uart_port *port)
++{
++ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+
-+ spi_writel(as, RPR, rx_dma);
-+ spi_writel(as, TPR, tx_dma);
++ if (atmel_use_dma_tx(port)) {
++ UART_PUT_TCR(port, 0);
++ atmel_port->pdc_tx.ofs = 0;
++ }
++}
+
-+ if (msg->spi->bits_per_word > 8)
-+ len >>= 1;
-+ spi_writel(as, RCR, len);
-+ spi_writel(as, TCR, len);
++/*
+ * Power / Clock management.
+ */
+ static void atmel_serial_pm(struct uart_port *port, unsigned int state,
+@@ -1190,6 +1204,7 @@
+ .break_ctl = atmel_break_ctl,
+ .startup = atmel_startup,
+ .shutdown = atmel_shutdown,
++ .flush_buffer = atmel_flush_buffer,
+ .set_termios = atmel_set_termios,
+ .type = atmel_type,
+ .release_port = atmel_release_port,
+@@ -1440,6 +1455,15 @@
+ };
+
+ #ifdef CONFIG_PM
++static bool atmel_serial_clk_will_stop(void)
++{
++#ifdef CONFIG_ARCH_AT91
++ return at91_suspend_entering_slow_clock();
++#else
++ return false;
++#endif
++}
+
-+ dev_dbg(&msg->spi->dev,
-+ " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
-+ xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
-+ xfer->rx_buf, xfer->rx_dma);
-+ } else {
-+ xfer = as->next_transfer;
-+ remaining = as->next_remaining_bytes;
- }
+ static int atmel_serial_suspend(struct platform_device *pdev,
+ pm_message_t state)
+ {
+@@ -1447,7 +1471,7 @@
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+
+ if (device_may_wakeup(&pdev->dev)
+- && !at91_suspend_entering_slow_clock())
++ && !atmel_serial_clk_will_stop())
+ enable_irq_wake(port->irq);
+ else {
+ uart_suspend_port(&atmel_uart, port);
+--- a/drivers/serial/serial_core.c
++++ b/drivers/serial/serial_core.c
+@@ -552,6 +552,8 @@
+
+ spin_lock_irqsave(&port->lock, flags);
+ uart_circ_clear(&state->info->xmit);
++ if (port->ops->flush_buffer)
++ port->ops->flush_buffer(port);
+ spin_unlock_irqrestore(&port->lock, flags);
+ tty_wakeup(tty);
+ }
+--- a/drivers/spi/atmel_spi.c
++++ b/drivers/spi/atmel_spi.c
+@@ -51,9 +51,7 @@
+ u8 stopping;
+ struct list_head queue;
+ struct spi_transfer *current_transfer;
+- unsigned long current_remaining_bytes;
+- struct spi_transfer *next_transfer;
+- unsigned long next_remaining_bytes;
++ unsigned long remaining_bytes;
-- len = as->remaining_bytes;
-+ as->current_transfer = xfer;
-+ as->current_remaining_bytes = remaining;
-
-- tx_dma = xfer->tx_dma + xfer->len - len;
-- rx_dma = xfer->rx_dma + xfer->len - len;
-+ if (remaining > 0)
-+ len = remaining;
-+ else if (!atmel_spi_xfer_is_last(msg, xfer)
-+ && atmel_spi_xfer_can_be_chained(xfer)) {
-+ xfer = list_entry(xfer->transfer_list.next,
-+ struct spi_transfer, transfer_list);
-+ len = xfer->len;
-+ } else
-+ xfer = NULL;
+ void *buffer;
+ dma_addr_t buffer_dma;
+@@ -133,48 +131,6 @@
+ gpio_set_value(gpio, !active);
+ }
+-static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
+- struct spi_transfer *xfer)
+-{
+- return msg->transfers.prev == &xfer->transfer_list;
+-}
+-
+-static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
+-{
+- return xfer->delay_usecs == 0 && !xfer->cs_change;
+-}
+-
+-static void atmel_spi_next_xfer_data(struct spi_master *master,
+- struct spi_transfer *xfer,
+- dma_addr_t *tx_dma,
+- dma_addr_t *rx_dma,
+- u32 *plen)
+-{
+- struct atmel_spi *as = spi_master_get_devdata(master);
+- u32 len = *plen;
+-
- /* use scratch buffer only when rx or tx data is unspecified */
-- if (!xfer->rx_buf) {
-- rx_dma = as->buffer_dma;
+- if (xfer->rx_buf)
+- *rx_dma = xfer->rx_dma + xfer->len - len;
+- else {
+- *rx_dma = as->buffer_dma;
- if (len > BUFFER_SIZE)
- len = BUFFER_SIZE;
- }
-- if (!xfer->tx_buf) {
-- tx_dma = as->buffer_dma;
+- if (xfer->tx_buf)
+- *tx_dma = xfer->tx_dma + xfer->len - len;
+- else {
+- *tx_dma = as->buffer_dma;
- if (len > BUFFER_SIZE)
- len = BUFFER_SIZE;
- memset(as->buffer, 0, len);
- dma_sync_single_for_device(&as->pdev->dev,
- as->buffer_dma, len, DMA_TO_DEVICE);
- }
-+ as->next_transfer = xfer;
-
-- spi_writel(as, RPR, rx_dma);
-- spi_writel(as, TPR, tx_dma);
-+ if (xfer) {
-+ total = len;
-+ atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
-+ as->next_remaining_bytes = total - len;
-+
-+ spi_writel(as, RNPR, rx_dma);
-+ spi_writel(as, TNPR, tx_dma);
-+
-+ if (msg->spi->bits_per_word > 8)
-+ len >>= 1;
-+ spi_writel(as, RNCR, len);
-+ spi_writel(as, TNCR, len);
-+
-+ dev_dbg(&msg->spi->dev,
-+ " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
-+ xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
-+ xfer->rx_buf, xfer->rx_dma);
-+ } else {
-+ spi_writel(as, RNCR, 0);
-+ spi_writel(as, TNCR, 0);
-+ }
+-
+- *plen = len;
+-}
+-
+ /*
+ * Submit next transfer for DMA.
+ * lock is held, spi irq is blocked
+@@ -184,78 +140,53 @@
+ {
+ struct atmel_spi *as = spi_master_get_devdata(master);
+ struct spi_transfer *xfer;
+- u32 len, remaining, total;
++ u32 len;
+ dma_addr_t tx_dma, rx_dma;
-- as->remaining_bytes -= len;
-- if (msg->spi->bits_per_word > 8)
-- len >>= 1;
+- if (!as->current_transfer)
+- xfer = list_entry(msg->transfers.next,
+- struct spi_transfer, transfer_list);
+- else if (!as->next_transfer)
+- xfer = list_entry(as->current_transfer->transfer_list.next,
+- struct spi_transfer, transfer_list);
+- else
+- xfer = NULL;
-
-- /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
-- * mechanism might help avoid the IRQ latency between transfers
-- * (and improve the nCS0 errata handling on at91rm9200 chips)
-- *
-- * We're also waiting for ENDRX before we start the next
-+ /* REVISIT: We're waiting for ENDRX before we start the next
+- if (xfer) {
+- len = xfer->len;
+- atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
+- remaining = xfer->len - len;
+-
+- spi_writel(as, RPR, rx_dma);
+- spi_writel(as, TPR, tx_dma);
+-
+- if (msg->spi->bits_per_word > 8)
+- len >>= 1;
+- spi_writel(as, RCR, len);
+- spi_writel(as, TCR, len);
+-
+- dev_dbg(&msg->spi->dev,
+- " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
+- xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
+- xfer->rx_buf, xfer->rx_dma);
+- } else {
+- xfer = as->next_transfer;
+- remaining = as->next_remaining_bytes;
++ xfer = as->current_transfer;
++ if (!xfer || as->remaining_bytes == 0) {
++ if (xfer)
++ xfer = list_entry(xfer->transfer_list.next,
++ struct spi_transfer, transfer_list);
++ else
++ xfer = list_entry(msg->transfers.next,
++ struct spi_transfer, transfer_list);
++ as->remaining_bytes = xfer->len;
++ as->current_transfer = xfer;
+ }
+
+- as->current_transfer = xfer;
+- as->current_remaining_bytes = remaining;
+-
+- if (remaining > 0)
+- len = remaining;
+- else if (!atmel_spi_xfer_is_last(msg, xfer)
+- && atmel_spi_xfer_can_be_chained(xfer)) {
+- xfer = list_entry(xfer->transfer_list.next,
+- struct spi_transfer, transfer_list);
+- len = xfer->len;
+- } else
+- xfer = NULL;
++ len = as->remaining_bytes;
+
+- as->next_transfer = xfer;
++ tx_dma = xfer->tx_dma + xfer->len - len;
++ rx_dma = xfer->rx_dma + xfer->len - len;
+
+- if (xfer) {
+- total = len;
+- atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
+- as->next_remaining_bytes = total - len;
+-
+- spi_writel(as, RNPR, rx_dma);
+- spi_writel(as, TNPR, tx_dma);
+-
+- if (msg->spi->bits_per_word > 8)
+- len >>= 1;
+- spi_writel(as, RNCR, len);
+- spi_writel(as, TNCR, len);
+-
+- dev_dbg(&msg->spi->dev,
+- " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
+- xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
+- xfer->rx_buf, xfer->rx_dma);
+- } else {
+- spi_writel(as, RNCR, 0);
+- spi_writel(as, TNCR, 0);
++ /* use scratch buffer only when rx or tx data is unspecified */
++ if (!xfer->rx_buf) {
++ rx_dma = as->buffer_dma;
++ if (len > BUFFER_SIZE)
++ len = BUFFER_SIZE;
+ }
++ if (!xfer->tx_buf) {
++ tx_dma = as->buffer_dma;
++ if (len > BUFFER_SIZE)
++ len = BUFFER_SIZE;
++ memset(as->buffer, 0, len);
++ dma_sync_single_for_device(&as->pdev->dev,
++ as->buffer_dma, len, DMA_TO_DEVICE);
++ }
++
++ spi_writel(as, RPR, rx_dma);
++ spi_writel(as, TPR, tx_dma);
+
+- /* REVISIT: We're waiting for ENDRX before we start the next
++ as->remaining_bytes -= len;
++ if (msg->spi->bits_per_word > 8)
++ len >>= 1;
++
++ /* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
++ * mechanism might help avoid the IRQ latency between transfers
++ * (and improve the nCS0 errata handling on at91rm9200 chips)
++ *
++ * We're also waiting for ENDRX before we start the next
* transfer because we need to handle some difficult timing
* issues otherwise. If we wait for ENDTX in one transfer and
* then starts waiting for ENDRX in the next, it's difficult
-@@ -196,17 +275,7 @@
+@@ -265,7 +196,17 @@
*
* It should be doable, though. Just not now...
*/
-- spi_writel(as, TNCR, 0);
-- spi_writel(as, RNCR, 0);
++ spi_writel(as, TNCR, 0);
++ spi_writel(as, RNCR, 0);
spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
--
-- dev_dbg(&msg->spi->dev,
-- " start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n",
-- xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
-- xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR));
--
-- spi_writel(as, RCR, len);
-- spi_writel(as, TCR, len);
++
++ dev_dbg(&msg->spi->dev,
++ " start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n",
++ xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
++ xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR));
++
++ spi_writel(as, RCR, len);
++ spi_writel(as, TCR, len);
spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
}
-@@ -304,6 +373,7 @@
+@@ -363,7 +304,6 @@
spin_lock(&as->lock);
as->current_transfer = NULL;
-+ as->next_transfer = NULL;
+- as->next_transfer = NULL;
/* continue if needed */
if (list_empty(&as->queue) || as->stopping)
-@@ -387,7 +457,7 @@
+@@ -447,7 +387,7 @@
spi_writel(as, IDR, pending);
-- if (as->remaining_bytes == 0) {
-+ if (as->current_remaining_bytes == 0) {
+- if (as->current_remaining_bytes == 0) {
++ if (as->remaining_bytes == 0) {
msg->actual_length += xfer->len;
if (!msg->is_dma_mapped)
-@@ -397,7 +467,7 @@
+@@ -457,7 +397,7 @@
if (xfer->delay_usecs)
udelay(xfer->delay_usecs);
-- if (msg->transfers.prev == &xfer->transfer_list) {
-+ if (atmel_spi_xfer_is_last(msg, xfer)) {
+- if (atmel_spi_xfer_is_last(msg, xfer)) {
++ if (msg->transfers.prev == &xfer->transfer_list) {
/* report completed message */
atmel_spi_msg_done(master, as, msg, 0,
xfer->cs_change);
-@@ -500,9 +570,14 @@
- if (!(spi->mode & SPI_CPHA))
- csr |= SPI_BIT(NCPHA);
-
-- /* TODO: DLYBS and DLYBCT */
-- csr |= SPI_BF(DLYBS, 10);
-- csr |= SPI_BF(DLYBCT, 10);
-+ /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
-+ *
-+ * DLYBCT would add delays between words, slowing down transfers.
-+ * It could potentially be useful to cope with DMA bottlenecks, but
-+ * in those cases it's probably best to just use a lower bitrate.
-+ */
-+ csr |= SPI_BF(DLYBS, 0);
-+ csr |= SPI_BF(DLYBCT, 0);
+--- a/drivers/usb/gadget/Kconfig
++++ b/drivers/usb/gadget/Kconfig
+@@ -118,10 +118,10 @@
+ config USB_GADGET_ATMEL_USBA
+ boolean "Atmel USBA"
+ select USB_GADGET_DUALSPEED
+- depends on AVR32
++ depends on AVR32 || ARCH_AT91CAP9
+ help
+ USBA is the integrated high-speed USB Device controller on
+- the AT32AP700x processors from Atmel.
++ the AT32AP700x and AT91CAP9 processors from Atmel.
- /* chipselect must have been muxed as GPIO (e.g. in board setup) */
- npcs_pin = (unsigned int)spi->controller_data;
+ config USB_ATMEL_USBA
+ tristate
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -18,6 +18,7 @@
#ifdef CONFIG_USB_GADGET_DEBUG_FS
#include <linux/debugfs.h>
-@@ -324,53 +326,6 @@
+@@ -324,53 +326,28 @@
return 1;
}
-static void copy_to_fifo(void __iomem *fifo, const void *buf, int len)
-{
- unsigned long tmp;
--
++#if defined(CONFIG_AVR32)
+
- DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
- for (; len > 0; len -= 4, buf += 4, fifo += 4) {
- tmp = *(unsigned long *)buf;
- break;
- }
- }
--}
--
++static void toggle_bias(int is_on)
++{
+ }
+
-static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
--{
++#elif defined(CONFIG_ARCH_AT91)
++
++#include <asm/arch/at91_pmc.h>
++
++static void toggle_bias(int is_on)
+ {
- union {
- unsigned long *w;
- unsigned char *b;
- } while (--len);
- }
- }
--}
--
++ unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
++
++ if (is_on)
++ at91_sys_write(AT91_CKGR_UCKR, uckr | AT91_PMC_BIASEN);
++ else
++ at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
+ }
+
++#endif /* CONFIG_ARCH_AT91 */
++
static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
{
unsigned int transaction_len;
-@@ -387,7 +342,7 @@
+@@ -387,7 +364,7 @@
ep->ep.name, req, transaction_len,
req->last_transaction ? ", done" : "");
usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
req->req.actual += transaction_len;
}
-@@ -476,7 +431,7 @@
+@@ -476,7 +453,7 @@
bytecount = req->req.length - req->req.actual;
}
ep->fifo, bytecount);
req->req.actual += bytecount;
-@@ -1029,33 +984,6 @@
+@@ -1029,33 +1006,6 @@
.set_selfpowered = usba_udc_set_selfpowered,
};
static struct usb_endpoint_descriptor usba_ep0_desc = {
.bLength = USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
-@@ -1074,7 +1002,6 @@
+@@ -1074,7 +1024,6 @@
static struct usba_udc the_udc = {
.gadget = {
.ops = &usba_udc_ops,
.ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
.is_dualspeed = 1,
.name = "atmel_usba_udc",
-@@ -1231,7 +1158,7 @@
+@@ -1231,7 +1180,7 @@
} else {
usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
usba_writel(udc, TST, USBA_TST_PKT_MODE);
sizeof(test_packet_buffer));
usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
dev_info(dev, "Entering Test_Packet mode...\n");
-@@ -1539,7 +1466,7 @@
+@@ -1530,13 +1479,13 @@
+ DBG(DBG_HW, "Packet length: %u\n", pkt_len);
+ if (pkt_len != sizeof(crq)) {
+ pr_warning("udc: Invalid packet length %u "
+- "(expected %lu)\n", pkt_len, sizeof(crq));
++ "(expected %zu)\n", pkt_len, sizeof(crq));
+ set_protocol_stall(udc, ep);
+ return;
}
DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
/* Free up one bank in the FIFO so that we can
* generate or receive a reply right away. */
-@@ -1911,7 +1838,7 @@
+@@ -1688,6 +1637,7 @@
+ DBG(DBG_INT, "irq, status=%#08x\n", status);
+
+ if (status & USBA_DET_SUSPEND) {
++ toggle_bias(0);
+ usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
+ DBG(DBG_BUS, "Suspend detected\n");
+ if (udc->gadget.speed != USB_SPEED_UNKNOWN
+@@ -1699,6 +1649,7 @@
+ }
+
+ if (status & USBA_WAKE_UP) {
++ toggle_bias(1);
+ usba_writel(udc, INT_CLR, USBA_WAKE_UP);
+ DBG(DBG_BUS, "Wake Up CPU detected\n");
+ }
+@@ -1792,12 +1743,14 @@
+ vbus = gpio_get_value(udc->vbus_pin);
+ if (vbus != udc->vbus_prev) {
+ if (vbus) {
+- usba_writel(udc, CTRL, USBA_EN_USBA);
++ toggle_bias(1);
++ usba_writel(udc, CTRL, USBA_ENABLE_MASK);
+ usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
+ } else {
+ udc->gadget.speed = USB_SPEED_UNKNOWN;
+ reset_all_endpoints(udc);
+- usba_writel(udc, CTRL, 0);
++ toggle_bias(0);
++ usba_writel(udc, CTRL, USBA_DISABLE_MASK);
+ spin_unlock(&udc->lock);
+ udc->driver->disconnect(&udc->gadget);
+ spin_lock(&udc->lock);
+@@ -1850,7 +1803,8 @@
+ /* If Vbus is present, enable the controller and wait for reset */
+ spin_lock_irqsave(&udc->lock, flags);
+ if (vbus_is_present(udc) && udc->vbus_prev == 0) {
+- usba_writel(udc, CTRL, USBA_EN_USBA);
++ toggle_bias(1);
++ usba_writel(udc, CTRL, USBA_ENABLE_MASK);
+ usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
+ }
+ spin_unlock_irqrestore(&udc->lock, flags);
+@@ -1883,7 +1837,8 @@
+ spin_unlock_irqrestore(&udc->lock, flags);
+
+ /* This will also disable the DP pullup */
+- usba_writel(udc, CTRL, 0);
++ toggle_bias(0);
++ usba_writel(udc, CTRL, USBA_DISABLE_MASK);
+
+ driver->unbind(&udc->gadget);
+ udc->gadget.dev.driver = NULL;
+@@ -1908,7 +1863,7 @@
regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
return -ENXIO;
irq = platform_get_irq(pdev, 0);
-@@ -1959,16 +1886,44 @@
- usba_writel(udc, CTRL, 0);
+@@ -1953,19 +1908,48 @@
+
+ /* Make sure we start from a clean slate */
+ clk_enable(pclk);
+- usba_writel(udc, CTRL, 0);
++ toggle_bias(0);
++ usba_writel(udc, CTRL, USBA_DISABLE_MASK);
clk_disable(pclk);
+ usba_ep = kmalloc(sizeof(struct usba_ep) * pdata->num_ep,
list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
}
-@@ -1987,7 +1942,7 @@
+@@ -1984,7 +1968,7 @@
goto err_device_add;
}
if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
udc->vbus_pin = pdata->vbus_pin;
-@@ -2007,7 +1962,7 @@
+@@ -2004,7 +1988,7 @@
}
usba_init_debugfs(udc);
usba_ep_init_debugfs(udc, &usba_ep[i]);
return 0;
-@@ -2015,6 +1970,8 @@
+@@ -2012,6 +1996,8 @@
err_device_add:
free_irq(irq, udc);
err_request_irq:
iounmap(udc->fifo);
err_map_fifo:
iounmap(udc->regs);
-@@ -2032,10 +1989,11 @@
+@@ -2029,10 +2015,11 @@
{
struct usba_udc *udc;
int i;
usba_ep_cleanup_debugfs(&usba_ep[i]);
usba_cleanup_debugfs(udc);
+@@ -2040,6 +2027,7 @@
+ gpio_free(udc->vbus_pin);
+
+ free_irq(udc->irq, udc);
++ kfree(usba_ep);
+ iounmap(udc->fifo);
+ iounmap(udc->regs);
+ clk_put(udc->hclk);
+--- a/drivers/usb/gadget/atmel_usba_udc.h
++++ b/drivers/usb/gadget/atmel_usba_udc.h
+@@ -41,6 +41,15 @@
+ #define USBA_EN_USBA (1 << 8)
+ #define USBA_DETACH (1 << 9)
+ #define USBA_REMOTE_WAKE_UP (1 << 10)
++#define USBA_PULLD_DIS (1 << 11)
++
++#if defined(CONFIG_AVR32)
++#define USBA_ENABLE_MASK USBA_EN_USBA
++#define USBA_DISABLE_MASK 0
++#elif defined(CONFIG_ARCH_AT91)
++#define USBA_ENABLE_MASK (USBA_EN_USBA | USBA_PULLD_DIS)
++#define USBA_DISABLE_MASK USBA_DETACH
++#endif /* CONFIG_ARCH_AT91 */
+
+ /* Bitfields in FNUM */
+ #define USBA_MICRO_FRAME_NUM_OFFSET 0
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
-@@ -16,6 +16,7 @@
- #include <linux/fb.h>
- #include <linux/init.h>
- #include <linux/delay.h>
-+#include <linux/backlight.h>
-
- #include <asm/arch/board.h>
- #include <asm/arch/cpu.h>
-@@ -37,7 +38,9 @@
+@@ -38,7 +38,9 @@
#endif
#if defined(CONFIG_ARCH_AT91)
static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
struct fb_var_screeninfo *var)
-@@ -69,12 +72,113 @@
- }
- #endif
-
-+static const u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
-+ | ATMEL_LCDC_POL_POSITIVE
-+ | ATMEL_LCDC_ENA_PWMENABLE;
-+
-+#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
-+
-+/* some bl->props field just changed */
-+static int atmel_bl_update_status(struct backlight_device *bl)
-+{
-+ struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
-+ int power = sinfo->bl_power;
-+ int brightness = bl->props.brightness;
-+
-+ /* REVISIT there may be a meaningful difference between
-+ * fb_blank and power ... there seem to be some cases
-+ * this doesn't handle correctly.
-+ */
-+ if (bl->props.fb_blank != sinfo->bl_power)
-+ power = bl->props.fb_blank;
-+ else if (bl->props.power != sinfo->bl_power)
-+ power = bl->props.power;
-+
-+ if (brightness < 0 && power == FB_BLANK_UNBLANK)
-+ brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
-+ else if (power != FB_BLANK_UNBLANK)
-+ brightness = 0;
-+
-+ lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
-+ lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
-+ brightness ? contrast_ctr : 0);
-+
-+ bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
-+
-+ return 0;
-+}
-+
-+static int atmel_bl_get_brightness(struct backlight_device *bl)
-+{
-+ struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
-+
-+ return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
-+}
-+
-+static struct backlight_ops atmel_lcdc_bl_ops = {
-+ .update_status = atmel_bl_update_status,
-+ .get_brightness = atmel_bl_get_brightness,
-+};
-+
-+static void init_backlight(struct atmel_lcdfb_info *sinfo)
-+{
-+ struct backlight_device *bl;
-+
-+ sinfo->bl_power = FB_BLANK_UNBLANK;
-+
-+ if (sinfo->backlight)
-+ return;
-+
-+ bl = backlight_device_register("backlight", &sinfo->pdev->dev,
-+ sinfo, &atmel_lcdc_bl_ops);
-+ if (IS_ERR(sinfo->backlight)) {
-+ dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
-+ PTR_ERR(bl));
-+ return;
-+ }
-+ sinfo->backlight = bl;
-+
-+ bl->props.power = FB_BLANK_UNBLANK;
-+ bl->props.fb_blank = FB_BLANK_UNBLANK;
-+ bl->props.max_brightness = 0xff;
-+ bl->props.brightness = atmel_bl_get_brightness(bl);
-+}
-+
-+static void exit_backlight(struct atmel_lcdfb_info *sinfo)
-+{
-+ if (sinfo->backlight)
-+ backlight_device_unregister(sinfo->backlight);
-+}
-+
-+#else
-+
-+static void init_backlight(struct atmel_lcdfb_info *sinfo)
-+{
-+ dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
-+}
-+
-+static void exit_backlight(struct atmel_lcdfb_info *sinfo)
-+{
-+}
-+
-+#endif
-+
-+static void init_contrast(struct atmel_lcdfb_info *sinfo)
-+{
-+ /* have some default contrast/backlight settings */
-+ lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
-+ lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
-+
-+ if (sinfo->lcdcon_is_backlight)
-+ init_backlight(sinfo);
-+}
-+
-
- static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
+@@ -176,7 +178,7 @@
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.xpanstep = 0,
.ywrapstep = 0,
.accel = FB_ACCEL_NONE,
};
-@@ -148,6 +252,8 @@
+@@ -250,6 +252,8 @@
return -ENOMEM;
}
return 0;
}
-@@ -203,6 +309,26 @@
- var->transp.offset = var->transp.length = 0;
- var->xoffset = var->yoffset = 0;
-
-+ /* Saturate vertical and horizontal timings at maximum values */
-+ var->vsync_len = min_t(u32, var->vsync_len,
-+ (ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
-+ var->upper_margin = min_t(u32, var->upper_margin,
-+ ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
-+ var->lower_margin = min_t(u32, var->lower_margin,
-+ ATMEL_LCDC_VFP);
-+ var->right_margin = min_t(u32, var->right_margin,
-+ (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
-+ var->hsync_len = min_t(u32, var->hsync_len,
-+ (ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
-+ var->left_margin = min_t(u32, var->left_margin,
-+ ATMEL_LCDC_HBP + 1);
-+
-+ /* Some parameters can't be zero */
-+ var->vsync_len = max_t(u32, var->vsync_len, 1);
-+ var->right_margin = max_t(u32, var->right_margin, 1);
-+ var->hsync_len = max_t(u32, var->hsync_len, 1);
-+ var->left_margin = max_t(u32, var->left_margin, 1);
-+
- switch (var->bits_per_pixel) {
- case 1:
- case 2:
-@@ -370,10 +496,6 @@
- /* Disable all interrupts */
- lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
-
-- /* Set contrast */
-- value = ATMEL_LCDC_PS_DIV8 | ATMEL_LCDC_POL_POSITIVE | ATMEL_LCDC_ENA_PWMENABLE;
-- lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, value);
-- lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
- /* ...wait for DMA engine to become idle... */
- while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
- msleep(10);
-@@ -516,7 +638,6 @@
+@@ -634,7 +638,6 @@
struct fb_info *info = sinfo->info;
int ret = 0;
info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
dev_info(info->device,
-@@ -577,6 +698,7 @@
- sinfo->default_monspecs = pdata_sinfo->default_monspecs;
- sinfo->atmel_lcdfb_power_control = pdata_sinfo->atmel_lcdfb_power_control;
- sinfo->guard_time = pdata_sinfo->guard_time;
-+ sinfo->lcdcon_is_backlight = pdata_sinfo->lcdcon_is_backlight;
- } else {
- dev_err(dev, "cannot get default configuration\n");
- goto free_info;
-@@ -645,6 +767,11 @@
+@@ -764,6 +767,11 @@
info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
if (!info->screen_base)
goto release_intmem;
} else {
/* alocate memory buffer */
ret = atmel_lcdfb_alloc_video_memory(sinfo);
-@@ -670,6 +797,9 @@
- goto release_mem;
- }
+--- a/fs/fs-writeback.c
++++ b/fs/fs-writeback.c
+@@ -385,8 +385,6 @@
+ * WB_SYNC_HOLD is a hack for sys_sync(): reattach the inode to sb->s_dirty so
+ * that it can be located for waiting on in __writeback_single_inode().
+ *
+- * Called under inode_lock.
+- *
+ * If `bdi' is non-zero then we're being asked to writeback a specific queue.
+ * This function assumes that the blockdev superblock's inodes are backed by
+ * a variety of queues, so all inodes are searched. For other superblocks,
+@@ -402,11 +400,12 @@
+ * on the writer throttling path, and we get decent balancing between many
+ * throttled threads: we don't want them all piling up on inode_sync_wait.
+ */
+-static void
+-sync_sb_inodes(struct super_block *sb, struct writeback_control *wbc)
++void generic_sync_sb_inodes(struct super_block *sb,
++ struct writeback_control *wbc)
+ {
+ const unsigned long start = jiffies; /* livelock avoidance */
-+ /* Initialize PWM for contrast or backlight ("off") */
-+ init_contrast(sinfo);
-+
- /* interrupt */
- ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
- if (ret) {
-@@ -721,6 +851,7 @@
- unregister_irqs:
- free_irq(sinfo->irq_base, info);
- unmap_mmio:
-+ exit_backlight(sinfo);
- iounmap(sinfo->mmio);
- release_mem:
- release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
-@@ -755,6 +886,7 @@
- if (!sinfo)
- return 0;
-
-+ exit_backlight(sinfo);
- if (sinfo->atmel_lcdfb_power_control)
- sinfo->atmel_lcdfb_power_control(0);
- unregister_framebuffer(info);
-@@ -781,6 +913,9 @@
-
- static struct platform_driver atmel_lcdfb_driver = {
- .remove = __exit_p(atmel_lcdfb_remove),
-+
-+// FIXME need suspend, resume
-+
- .driver = {
- .name = "atmel_lcdfb",
- .owner = THIS_MODULE,
---- a/drivers/video/backlight/Kconfig
-+++ b/drivers/video/backlight/Kconfig
-@@ -50,6 +50,19 @@
- To have support for your specific LCD panel you will have to
- select the proper drivers which depend on this option.
-
-+config BACKLIGHT_ATMEL_LCDC
-+ bool "Atmel LCDC Contrast-as-Backlight control"
-+ depends on BACKLIGHT_CLASS_DEVICE && FB_ATMEL
-+ default y if MACH_SAM9261EK || MACH_SAM9263EK
-+ help
-+ This provides a backlight control internal to the Atmel LCDC
-+ driver. If the LCD "contrast control" on your board is wired
-+ so it controls the backlight brightness, select this option to
-+ export this as a PWM-based backlight control.
-+
-+ If in doubt, it's safe to enable this option; it doesn't kick
-+ in unless the board's description says it's wired that way.
-+
- config BACKLIGHT_CORGI
- tristate "Generic (aka Sharp Corgi) Backlight Driver"
- depends on BACKLIGHT_CLASS_DEVICE
---- a/drivers/video/console/Kconfig
-+++ b/drivers/video/console/Kconfig
-@@ -6,7 +6,7 @@
++ spin_lock(&inode_lock);
+ if (!wbc->for_kupdate || list_empty(&sb->s_io))
+ queue_io(sb, wbc->older_than_this);
- config VGA_CONSOLE
- bool "VGA text console" if EMBEDDED || !X86
-- depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN
-+ depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN && !AVR32
- default y
- help
- Saying Y here will allow you to use Linux in text mode through a
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -223,7 +223,7 @@
-
- config AT32AP700X_WDT
- tristate "AT32AP700x watchdog"
-- depends on CPU_AT32AP7000
-+ depends on CPU_AT32AP700X
- help
- Watchdog timer embedded into AT32AP700x devices. This will reboot
- your system when the timeout is reached.
---- a/include/asm-avr32/arch-at32ap/at32ap7000.h
-+++ /dev/null
-@@ -1,35 +0,0 @@
--/*
-- * Pin definitions for AT32AP7000.
-- *
-- * Copyright (C) 2006 Atmel Corporation
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License version 2 as
-- * published by the Free Software Foundation.
-- */
--#ifndef __ASM_ARCH_AT32AP7000_H__
--#define __ASM_ARCH_AT32AP7000_H__
--
--#define GPIO_PERIPH_A 0
--#define GPIO_PERIPH_B 1
--
--#define NR_GPIO_CONTROLLERS 4
--
--/*
-- * Pin numbers identifying specific GPIO pins on the chip. They can
-- * also be converted to IRQ numbers by passing them through
-- * gpio_to_irq().
-- */
--#define GPIO_PIOA_BASE (0)
--#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
--#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
--#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
--#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
--
--#define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N))
--#define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N))
--#define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N))
--#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
--#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
--
--#endif /* __ASM_ARCH_AT32AP7000_H__ */
---- /dev/null
-+++ b/include/asm-avr32/arch-at32ap/at32ap700x.h
-@@ -0,0 +1,35 @@
-+/*
-+ * Pin definitions for AT32AP7000.
-+ *
-+ * Copyright (C) 2006 Atmel Corporation
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+#ifndef __ASM_ARCH_AT32AP700X_H__
-+#define __ASM_ARCH_AT32AP700X_H__
-+
-+#define GPIO_PERIPH_A 0
-+#define GPIO_PERIPH_B 1
-+
-+#define NR_GPIO_CONTROLLERS 4
+@@ -485,8 +484,16 @@
+ if (!list_empty(&sb->s_more_io))
+ wbc->more_io = 1;
+ }
++ spin_unlock(&inode_lock);
+ return; /* Leave any unwritten inodes on s_io */
+ }
++EXPORT_SYMBOL_GPL(generic_sync_sb_inodes);
+
-+/*
-+ * Pin numbers identifying specific GPIO pins on the chip. They can
-+ * also be converted to IRQ numbers by passing them through
-+ * gpio_to_irq().
-+ */
-+#define GPIO_PIOA_BASE (0)
-+#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
-+#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
-+#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
-+#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
-+
-+#define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N))
-+#define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N))
-+#define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N))
-+#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
-+#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
-+
-+#endif /* __ASM_ARCH_AT32AP700X_H__ */
++static void sync_sb_inodes(struct super_block *sb,
++ struct writeback_control *wbc)
++{
++ generic_sync_sb_inodes(sb, wbc);
++}
+
+ /*
+ * Start writeback of dirty pagecache data against all unlocked inodes.
+@@ -526,11 +533,8 @@
+ * be unmounted by the time it is released.
+ */
+ if (down_read_trylock(&sb->s_umount)) {
+- if (sb->s_root) {
+- spin_lock(&inode_lock);
++ if (sb->s_root)
+ sync_sb_inodes(sb, wbc);
+- spin_unlock(&inode_lock);
+- }
+ up_read(&sb->s_umount);
+ }
+ spin_lock(&sb_lock);
+@@ -568,9 +572,7 @@
+ (inodes_stat.nr_inodes - inodes_stat.nr_unused) +
+ nr_dirty + nr_unstable;
+ wbc.nr_to_write += wbc.nr_to_write / 2; /* Bit more for luck */
+- spin_lock(&inode_lock);
+ sync_sb_inodes(sb, &wbc);
+- spin_unlock(&inode_lock);
+ }
+
+ /*
--- a/include/asm-avr32/arch-at32ap/board.h
+++ b/include/asm-avr32/arch-at32ap/board.h
-@@ -38,9 +38,7 @@
+@@ -8,6 +8,12 @@
+
+ #define GPIO_PIN_NONE (-1)
+
++/*
++ * Clock rates for various on-board oscillators. The number of entries
++ * in this array is chip-dependent.
++ */
++extern unsigned long at32_board_osc_rates[];
++
+ /* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
+ void at32_add_system_devices(void);
+
+@@ -36,11 +42,10 @@
+ struct atmel_lcdfb_info;
+ struct platform_device *
at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
- unsigned long fbmem_start, unsigned long fbmem_len);
+- unsigned long fbmem_start, unsigned long fbmem_len);
++ unsigned long fbmem_start, unsigned long fbmem_len,
++ unsigned int pin_config);
-struct usba_platform_data {
- int vbus_pin;
struct platform_device *
at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
-@@ -51,6 +49,9 @@
- at32_add_device_ide(unsigned int id, unsigned int extint,
- struct ide_platform_data *data);
-
-+/* mask says which PWM channels to mux */
-+struct platform_device *at32_add_device_pwm(u32 mask);
-+
- /* depending on what's hooked up, not all SSC pins will be used */
- #define ATMEL_SSC_TK 0x01
- #define ATMEL_SSC_TF 0x02
-@@ -65,8 +66,17 @@
+@@ -68,9 +73,27 @@
struct platform_device *
at32_add_device_ssc(unsigned int id, unsigned int flags);
-struct platform_device *at32_add_device_twi(unsigned int id);
-struct platform_device *at32_add_device_mci(unsigned int id);
+-struct platform_device *at32_add_device_ac97c(unsigned int id);
+struct i2c_board_info;
+struct platform_device *at32_add_device_twi(unsigned int id,
-+ struct i2c_board_info *b,
-+ unsigned int n);
++ struct i2c_board_info *b,
++ unsigned int n);
+
+struct mci_platform_data {
+ int detect_pin;
+};
+struct platform_device *
+at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
- struct platform_device *at32_add_device_ac97c(unsigned int id);
++
++struct ac97c_platform_data {
++ unsigned short dma_rx_periph_id;
++ unsigned short dma_tx_periph_id;
++ unsigned short dma_controller_id;
++ int reset_pin;
++};
++struct platform_device *
++at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data);
++
struct platform_device *at32_add_device_abdac(unsigned int id);
-@@ -81,4 +91,7 @@
+ struct cf_platform_data {
+@@ -84,4 +107,20 @@
at32_add_device_cf(unsigned int id, unsigned int extint,
struct cf_platform_data *data);
+struct platform_device *
+at32_add_device_psif(unsigned int id);
++
++/* NAND / SmartMedia */
++struct atmel_nand_data {
++ int enable_pin; /* chip enable */
++ int det_pin; /* card detect */
++ int rdy_pin; /* ready/busy */
++ u8 ale; /* address line number connected to ALE */
++ u8 cle; /* address line number connected to CLE */
++ u8 bus_width_16; /* buswidth is 16 bit */
++ struct mtd_partition *(*partition_info)(int size, int *num_partitions);
++};
++struct platform_device *
++at32_add_device_nand(unsigned int id, struct atmel_nand_data *data);
+
#endif /* __ASM_ARCH_BOARD_H */
---- a/include/asm-avr32/arch-at32ap/cpu.h
-+++ b/include/asm-avr32/arch-at32ap/cpu.h
-@@ -14,7 +14,7 @@
- * Only AT32AP7000 is defined for now. We can identify the specific
- * chip at runtime, but I'm not sure if it's really worth it.
- */
--#ifdef CONFIG_CPU_AT32AP7000
-+#ifdef CONFIG_CPU_AT32AP700X
- # define cpu_is_at32ap7000() (1)
- #else
- # define cpu_is_at32ap7000() (0)
---- a/include/asm-avr32/arch-at32ap/io.h
-+++ b/include/asm-avr32/arch-at32ap/io.h
-@@ -4,7 +4,7 @@
- /* For "bizarre" halfword swapping */
- #include <linux/byteorder/swabb.h>
-
--#if defined(CONFIG_AP7000_32_BIT_SMC)
-+#if defined(CONFIG_AP700X_32_BIT_SMC)
- # define __swizzle_addr_b(addr) (addr ^ 3UL)
- # define __swizzle_addr_w(addr) (addr ^ 2UL)
- # define __swizzle_addr_l(addr) (addr)
-@@ -14,7 +14,7 @@
- # define __mem_ioswabb(a, x) (x)
- # define __mem_ioswabw(a, x) swab16(x)
- # define __mem_ioswabl(a, x) swab32(x)
--#elif defined(CONFIG_AP7000_16_BIT_SMC)
-+#elif defined(CONFIG_AP700X_16_BIT_SMC)
- # define __swizzle_addr_b(addr) (addr ^ 1UL)
- # define __swizzle_addr_w(addr) (addr)
- # define __swizzle_addr_l(addr) (addr)
+--- a/include/asm-avr32/arch-at32ap/init.h
++++ b/include/asm-avr32/arch-at32ap/init.h
+@@ -13,10 +13,6 @@
+ void setup_platform(void);
+ void setup_board(void);
+
+-/* Called by setup_platform */
+-void at32_clock_init(void);
+-void at32_portmux_init(void);
+-
+ void at32_setup_serial_console(unsigned int usart_id);
+
+ #endif /* __ASM_AVR32_AT32AP_INIT_H__ */
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap/pm.h
-@@ -0,0 +1,48 @@
+@@ -0,0 +1,51 @@
+/*
+ * AVR32 AP Power Management.
+ *
+
+#ifndef __ASSEMBLY__
+extern void cpu_enter_idle(void);
++extern void cpu_enter_standby(unsigned long sdramc_base);
+
+extern bool disable_idle_sleep;
+
+ else
+ cpu_enter_idle();
+}
++
++void intc_set_suspend_handler(unsigned long offset);
+#endif
+
+#endif /* __ASM_AVR32_ARCH_PM_H */
+int at32_select_gpio_pins(unsigned int port, u32 pins, u32 oe_mask);
+void at32_deselect_pins(unsigned int port, u32 pins);
+
-+u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins);
-+void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask);
++u32 at32_gpio_get_value_multiple(unsigned int port, u32 pins);
++void at32_gpio_set_value_multiple(unsigned int port, u32 value, u32 mask);
++
++#endif /* CONFIG_GPIO_DEV */
++
+ #endif /* __ASM_ARCH_PORTMUX_H__ */
+--- /dev/null
++++ b/include/asm-avr32/arch-at32ap/sram.h
+@@ -0,0 +1,30 @@
++/*
++ * Simple SRAM allocator
++ *
++ * Copyright (C) 2008 Atmel Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#ifndef __ASM_AVR32_ARCH_SRAM_H
++#define __ASM_AVR32_ARCH_SRAM_H
++
++#include <linux/genalloc.h>
++
++extern struct gen_pool *sram_pool;
++
++static inline unsigned long sram_alloc(size_t len)
++{
++ if (!sram_pool)
++ return 0UL;
+
-+#endif /* CONFIG_GPIO_DEV */
++ return gen_pool_alloc(sram_pool, len);
++}
+
- #endif /* __ASM_ARCH_PORTMUX_H__ */
++static inline void sram_free(unsigned long addr, size_t len)
++{
++ return gen_pool_free(sram_pool, addr, len);
++}
++
++#endif /* __ASM_AVR32_ARCH_SRAM_H */
--- a/include/asm-avr32/arch-at32ap/time.h
+++ /dev/null
@@ -1,112 +0,0 @@
#ifdef CONFIG_FRAME_POINTER
.macro save_fp
---- a/include/asm-avr32/byteorder.h
-+++ b/include/asm-avr32/byteorder.h
-@@ -12,8 +12,10 @@
- extern unsigned short __builtin_bswap_16(unsigned short x);
- #endif
-
-+#if 0
- #define __arch__swab32(x) __builtin_bswap_32(x)
- #define __arch__swab16(x) __builtin_bswap_16(x)
-+#endif
-
- #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
- # define __BYTEORDER_HAS_U64__
--- /dev/null
+++ b/include/asm-avr32/dma-controller.h
@@ -0,0 +1,166 @@
-#endif /* __ASM_AVR32_INTC_H */
--- a/include/asm-avr32/irq.h
+++ b/include/asm-avr32/irq.h
-@@ -11,4 +11,14 @@
-
- #define irq_canonicalize(i) (i)
-
-+#ifndef __ASSEMBLER__
-+int nmi_enable(void);
-+void nmi_disable(void);
+@@ -14,6 +14,11 @@
+ #ifndef __ASSEMBLER__
+ int nmi_enable(void);
+ void nmi_disable(void);
+
+/*
+ * Returns a bitmask of pending interrupts in a group.
+ */
+extern unsigned long intc_get_pending(unsigned int group);
-+#endif
-+
+ #endif
+
#endif /* __ASM_AVR32_IOCTLS_H */
---- a/include/asm-avr32/kdebug.h
-+++ b/include/asm-avr32/kdebug.h
-@@ -5,6 +5,7 @@
- enum die_val {
- DIE_BREAKPOINT,
- DIE_SSTEP,
-+ DIE_NMI,
- };
+--- a/include/asm-avr32/mmu_context.h
++++ b/include/asm-avr32/mmu_context.h
+@@ -13,7 +13,6 @@
+ #define __ASM_AVR32_MMU_CONTEXT_H
- #endif /* __ASM_AVR32_KDEBUG_H */
---- a/include/asm-avr32/ocd.h
-+++ b/include/asm-avr32/ocd.h
-@@ -533,6 +533,11 @@
- #define ocd_read(reg) __ocd_read(OCD_##reg)
- #define ocd_write(reg, value) __ocd_write(OCD_##reg, value)
+ #include <asm/tlbflush.h>
+-#include <asm/pgalloc.h>
+ #include <asm/sysreg.h>
+ #include <asm-generic/mm_hooks.h>
-+struct task_struct;
-+
-+void ocd_enable(struct task_struct *child);
-+void ocd_disable(struct task_struct *child);
+--- a/include/asm-avr32/page.h
++++ b/include/asm-avr32/page.h
+@@ -8,13 +8,11 @@
+ #ifndef __ASM_AVR32_PAGE_H
+ #define __ASM_AVR32_PAGE_H
+
++#include <linux/const.h>
+
- #endif /* !__ASSEMBLER__ */
+ /* PAGE_SHIFT determines the page size */
+ #define PAGE_SHIFT 12
+-#ifdef __ASSEMBLY__
+-#define PAGE_SIZE (1 << PAGE_SHIFT)
+-#else
+-#define PAGE_SIZE (1UL << PAGE_SHIFT)
+-#endif
++#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
+ #define PAGE_MASK (~(PAGE_SIZE-1))
+ #define PTE_MASK PAGE_MASK
- #endif /* __ASM_AVR32_OCD_H */
---- a/include/asm-avr32/pgtable.h
-+++ b/include/asm-avr32/pgtable.h
-@@ -157,6 +157,7 @@
- #define _PAGE_S(x) _PAGE_NORMAL(x)
+--- a/include/asm-avr32/pci.h
++++ b/include/asm-avr32/pci.h
+@@ -5,4 +5,6 @@
- #define PAGE_COPY _PAGE_P(PAGE_WRITE | PAGE_READ)
-+#define PAGE_SHARED _PAGE_S(PAGE_WRITE | PAGE_READ)
+ #define PCI_DMA_BUS_IS_PHYS (1)
- #ifndef __ASSEMBLY__
- /*
---- a/include/asm-avr32/processor.h
-+++ b/include/asm-avr32/processor.h
-@@ -57,11 +57,25 @@
- unsigned short cpu_revision;
- enum tlb_config tlb_config;
- unsigned long features;
-+ u32 device_id;
-
- struct cache_info icache;
- struct cache_info dcache;
- };
++#include <asm-generic/pci-dma-compat.h>
++
+ #endif /* __ASM_AVR32_PCI_H__ */
+--- a/include/asm-avr32/pgalloc.h
++++ b/include/asm-avr32/pgalloc.h
+@@ -8,65 +8,79 @@
+ #ifndef __ASM_AVR32_PGALLOC_H
+ #define __ASM_AVR32_PGALLOC_H
-+static inline unsigned int avr32_get_manufacturer_id(struct avr32_cpuinfo *cpu)
+-#include <asm/processor.h>
+-#include <linux/threads.h>
+-#include <linux/slab.h>
+-#include <linux/mm.h>
++#include <linux/quicklist.h>
++#include <asm/page.h>
++#include <asm/pgtable.h>
+
+-#define pmd_populate_kernel(mm, pmd, pte) \
+- set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
++#define QUICK_PGD 0 /* Preserve kernel mappings over free */
++#define QUICK_PT 1 /* Zero on free */
+
+-static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
++static inline void pmd_populate_kernel(struct mm_struct *mm,
++ pmd_t *pmd, pte_t *pte)
+{
-+ return (cpu->device_id >> 1) & 0x7f;
++ set_pmd(pmd, __pmd((unsigned long)pte));
+}
-+static inline unsigned int avr32_get_product_number(struct avr32_cpuinfo *cpu)
++
++static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
+ pgtable_t pte)
+ {
+- set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte)));
++ set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
+ }
+ #define pmd_pgtable(pmd) pmd_page(pmd)
+
++static inline void pgd_ctor(void *x)
+{
-+ return (cpu->device_id >> 12) & 0xffff;
++ pgd_t *pgd = x;
++
++ memcpy(pgd + USER_PTRS_PER_PGD,
++ swapper_pg_dir + USER_PTRS_PER_PGD,
++ (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+}
-+static inline unsigned int avr32_get_chip_revision(struct avr32_cpuinfo *cpu)
++
+ /*
+ * Allocate and free page tables
+ */
+-static __inline__ pgd_t *pgd_alloc(struct mm_struct *mm)
++static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+ {
+- return kcalloc(USER_PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
++ return quicklist_alloc(QUICK_PGD, GFP_KERNEL | __GFP_REPEAT, pgd_ctor);
+ }
+
+ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+ {
+- kfree(pgd);
++ quicklist_free(QUICK_PGD, NULL, pgd);
+ }
+
+ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+ unsigned long address)
+ {
+- pte_t *pte;
+-
+- pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
+-
+- return pte;
++ return quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
+ }
+
+-static inline struct page *pte_alloc_one(struct mm_struct *mm,
++static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+ unsigned long address)
+ {
+- struct page *pte;
++ struct page *page;
++ void *pg;
+
+- pte = alloc_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
+- if (!pte)
++ pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
++ if (!pg)
+ return NULL;
+- pgtable_page_ctor(pte);
+- return pte;
++
++ page = virt_to_page(pg);
++ pgtable_page_ctor(page);
++
++ return page;
+ }
+
+ static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+ {
+- free_page((unsigned long)pte);
++ quicklist_free(QUICK_PT, NULL, pte);
+ }
+
+ static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
+ {
+ pgtable_page_dtor(pte);
+- __free_page(pte);
++ quicklist_free_page(QUICK_PT, NULL, pte);
+ }
+
+ #define __pte_free_tlb(tlb,pte) \
+@@ -75,6 +89,10 @@
+ tlb_remove_page((tlb), pte); \
+ } while (0)
+
+-#define check_pgt_cache() do { } while(0)
++static inline void check_pgt_cache(void)
+{
-+ return (cpu->device_id >> 28) & 0x0f;
++ quicklist_trim(QUICK_PGD, NULL, 25, 16);
++ quicklist_trim(QUICK_PT, NULL, 25, 16);
+}
-+
- extern struct avr32_cpuinfo boot_cpu_data;
- #ifdef CONFIG_SMP
---- a/include/asm-avr32/ptrace.h
-+++ b/include/asm-avr32/ptrace.h
-@@ -121,7 +121,15 @@
- };
+ #endif /* __ASM_AVR32_PGALLOC_H */
+--- a/include/asm-avr32/pgtable.h
++++ b/include/asm-avr32/pgtable.h
+@@ -129,13 +129,6 @@
+
+ #define _PAGE_FLAGS_CACHE_MASK (_PAGE_CACHABLE | _PAGE_BUFFER | _PAGE_WT)
+
+-/* TODO: Check for saneness */
+-/* User-mode page table flags (to be set in a pgd or pmd entry) */
+-#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_TYPE_SMALL | _PAGE_RW \
+- | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
+-/* Kernel-mode page table flags */
+-#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_TYPE_SMALL | _PAGE_RW \
+- | _PAGE_ACCESSED | _PAGE_DIRTY)
+ /* Flags that may be modified by software */
+ #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY \
+ | _PAGE_FLAGS_CACHE_MASK)
+@@ -254,10 +247,14 @@
+ }
- #ifdef __KERNEL__
--# define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
+ #define pmd_none(x) (!pmd_val(x))
+-#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
+-#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
+-#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) \
+- != _KERNPG_TABLE)
++#define pmd_present(x) (pmd_val(x))
+
-+#include <asm/ocd.h>
-+
-+#define arch_ptrace_attach(child) ocd_enable(child)
-+
-+#define user_mode(regs) (((regs)->sr & MODE_MASK) == MODE_USER)
-+#define instruction_pointer(regs) ((regs)->pc)
-+#define profile_pc(regs) instruction_pointer(regs)
++static inline void pmd_clear(pmd_t *pmdp)
++{
++ set_pmd(pmdp, __pmd(0));
++}
+
- extern void show_regs (struct pt_regs *);
++#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
- static __inline__ int valid_user_regs(struct pt_regs *regs)
-@@ -141,9 +149,6 @@
- return 0;
- }
+ /*
+ * Permanent address of a page. We don't support highmem, so this is
+@@ -295,19 +292,16 @@
+
+ #define page_pte(page) page_pte_prot(page, __pgprot(0))
--#define instruction_pointer(regs) ((regs)->pc)
+-#define pmd_page_vaddr(pmd) \
+- ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
-
--#define profile_pc(regs) instruction_pointer(regs)
+-#define pmd_page(pmd) (phys_to_page(pmd_val(pmd)))
++#define pmd_page_vaddr(pmd) pmd_val(pmd)
++#define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
- #endif /* __KERNEL__ */
+ /* to find an entry in a page-table-directory. */
+-#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
+-#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
+-#define pgd_offset_current(address) \
+- ((pgd_t *)__mfsr(SYSREG_PTBR) + pgd_index(address))
++#define pgd_index(address) (((address) >> PGDIR_SHIFT) \
++ & (PTRS_PER_PGD - 1))
++#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+ /* to find an entry in a kernel page-table-directory */
+-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
++#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+ /* Find an entry in the third-level page table.. */
+ #define pte_index(address) \
+--- /dev/null
++++ b/include/asm-avr32/serial.h
+@@ -0,0 +1,13 @@
++#ifndef _ASM_SERIAL_H
++#define _ASM_SERIAL_H
++
++/*
++ * This assumes you have a 1.8432 MHz clock for your UART.
++ *
++ * It'd be nice if someone built a serial card with a 24.576 MHz
++ * clock, since the 16550A is capable of handling a top speed of 1.5
++ * megabits/second; but this requires the faster clock.
++ */
++#define BASE_BAUD (1843200 / 16)
++
++#endif /* _ASM_SERIAL_H */
--- a/include/asm-avr32/thread_info.h
+++ b/include/asm-avr32/thread_info.h
@@ -88,6 +88,7 @@
#define TIF_MEMDIE 6
#define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal */
#define TIF_CPU_GOING_TO_SLEEP 8 /* CPU is entering sleep 0 mode */
-+#define TIF_DEBUG 30 /* debugging enabled */
++#define TIF_FREEZE 29
+ #define TIF_DEBUG 30 /* debugging enabled */
#define TIF_USERSPACE 31 /* true if FS sets userspace */
- #define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
---- /dev/null
-+++ b/include/linux/atmel_pwm.h
-@@ -0,0 +1,70 @@
-+#ifndef __LINUX_ATMEL_PWM_H
-+#define __LINUX_ATMEL_PWM_H
-+
-+/**
-+ * struct pwm_channel - driver handle to a PWM channel
-+ * @regs: base of this channel's registers
-+ * @index: number of this channel (0..31)
-+ * @mck: base clock rate, which can be prescaled and maybe subdivided
-+ *
-+ * Drivers initialize a pwm_channel structure using pwm_channel_alloc().
-+ * Then they configure its clock rate (derived from MCK), alignment,
-+ * polarity, and duty cycle by writing directly to the channel registers,
-+ * before enabling the channel by calling pwm_channel_enable().
-+ *
-+ * After emitting a PWM signal for the desired length of time, drivers
-+ * may then pwm_channel_disable() or pwm_channel_free(). Both of these
-+ * disable the channel, but when it's freed the IRQ is deconfigured and
-+ * the channel must later be re-allocated and reconfigured.
-+ *
-+ * Note that if the period or duty cycle need to be changed while the
-+ * PWM channel is operating, drivers must use the PWM_CUPD double buffer
-+ * mechanism, either polling until they change or getting implicitly
-+ * notified through a once-per-period interrupt handler.
-+ */
-+struct pwm_channel {
-+ void __iomem *regs;
-+ unsigned index;
-+ unsigned long mck;
-+};
-+
-+extern int pwm_channel_alloc(int index, struct pwm_channel *ch);
-+extern int pwm_channel_free(struct pwm_channel *ch);
-+
-+extern int pwm_clk_alloc(unsigned prescale, unsigned div);
-+extern void pwm_clk_free(unsigned clk);
-+
-+extern int __pwm_channel_onoff(struct pwm_channel *ch, int enabled);
-+
-+#define pwm_channel_enable(ch) __pwm_channel_onoff((ch), 1)
-+#define pwm_channel_disable(ch) __pwm_channel_onoff((ch), 0)
-+
-+/* periodic interrupts, mostly for CUPD changes to period or cycle */
-+extern int pwm_channel_handler(struct pwm_channel *ch,
-+ void (*handler)(struct pwm_channel *ch));
-+
-+/* per-channel registers (banked at pwm_channel->regs) */
-+#define PWM_CMR 0x00 /* mode register */
-+#define PWM_CPR_CPD (1 << 10) /* set: CUPD modifies period */
-+#define PWM_CPR_CPOL (1 << 9) /* set: idle high */
-+#define PWM_CPR_CALG (1 << 8) /* set: center align */
-+#define PWM_CPR_CPRE (0xf << 0) /* mask: rate is mck/(2^pre) */
-+#define PWM_CPR_CLKA (0xb << 0) /* rate CLKA */
-+#define PWM_CPR_CLKB (0xc << 0) /* rate CLKB */
-+#define PWM_CDTY 0x04 /* duty cycle (max of CPRD) */
-+#define PWM_CPRD 0x08 /* period (count up from zero) */
-+#define PWM_CCNT 0x0c /* counter (20 bits?) */
-+#define PWM_CUPD 0x10 /* update CPRD (or CDTY) next period */
-+
-+static inline void
-+pwm_channel_writel(struct pwm_channel *pwmc, unsigned offset, u32 val)
-+{
-+ __raw_writel(val, pwmc->regs + offset);
-+}
-+
-+static inline u32 pwm_channel_readl(struct pwm_channel *pwmc, unsigned offset)
-+{
-+ return __raw_readl(pwmc->regs + offset);
-+}
-+
-+#endif /* __LINUX_ATMEL_PWM_H */
+--- a/include/asm-avr32/tlbflush.h
++++ b/include/asm-avr32/tlbflush.h
+@@ -26,7 +26,6 @@
+ extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+ unsigned long end);
+ extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
+-extern void __flush_tlb_page(unsigned long asid, unsigned long page);
+
+ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+
--- /dev/null
-+++ b/include/linux/atmel_serial.h
-@@ -0,0 +1,127 @@
-+/*
-+ * include/linux/atmel_serial.h
-+ *
-+ * Copyright (C) 2005 Ivan Kokshaysky
-+ * Copyright (C) SAN People
-+ *
-+ * USART registers.
-+ * Based on AT91RM9200 datasheet revision E.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ */
++++ b/include/asm-avr32/xor.h
+@@ -0,0 +1,6 @@
++#ifndef _ASM_XOR_H
++#define _ASM_XOR_H
+
-+#ifndef ATMEL_SERIAL_H
-+#define ATMEL_SERIAL_H
-+
-+#define ATMEL_US_CR 0x00 /* Control Register */
-+#define ATMEL_US_RSTRX (1 << 2) /* Reset Receiver */
-+#define ATMEL_US_RSTTX (1 << 3) /* Reset Transmitter */
-+#define ATMEL_US_RXEN (1 << 4) /* Receiver Enable */
-+#define ATMEL_US_RXDIS (1 << 5) /* Receiver Disable */
-+#define ATMEL_US_TXEN (1 << 6) /* Transmitter Enable */
-+#define ATMEL_US_TXDIS (1 << 7) /* Transmitter Disable */
-+#define ATMEL_US_RSTSTA (1 << 8) /* Reset Status Bits */
-+#define ATMEL_US_STTBRK (1 << 9) /* Start Break */
-+#define ATMEL_US_STPBRK (1 << 10) /* Stop Break */
-+#define ATMEL_US_STTTO (1 << 11) /* Start Time-out */
-+#define ATMEL_US_SENDA (1 << 12) /* Send Address */
-+#define ATMEL_US_RSTIT (1 << 13) /* Reset Iterations */
-+#define ATMEL_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
-+#define ATMEL_US_RETTO (1 << 15) /* Rearm Time-out */
-+#define ATMEL_US_DTREN (1 << 16) /* Data Terminal Ready Enable [AT91RM9200 only] */
-+#define ATMEL_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable [AT91RM9200 only] */
-+#define ATMEL_US_RTSEN (1 << 18) /* Request To Send Enable */
-+#define ATMEL_US_RTSDIS (1 << 19) /* Request To Send Disable */
-+
-+#define ATMEL_US_MR 0x04 /* Mode Register */
-+#define ATMEL_US_USMODE (0xf << 0) /* Mode of the USART */
-+#define ATMEL_US_USMODE_NORMAL 0
-+#define ATMEL_US_USMODE_RS485 1
-+#define ATMEL_US_USMODE_HWHS 2
-+#define ATMEL_US_USMODE_MODEM 3
-+#define ATMEL_US_USMODE_ISO7816_T0 4
-+#define ATMEL_US_USMODE_ISO7816_T1 6
-+#define ATMEL_US_USMODE_IRDA 8
-+#define ATMEL_US_USCLKS (3 << 4) /* Clock Selection */
-+#define ATMEL_US_USCLKS_MCK (0 << 4)
-+#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
-+#define ATMEL_US_USCLKS_SCK (3 << 4)
-+#define ATMEL_US_CHRL (3 << 6) /* Character Length */
-+#define ATMEL_US_CHRL_5 (0 << 6)
-+#define ATMEL_US_CHRL_6 (1 << 6)
-+#define ATMEL_US_CHRL_7 (2 << 6)
-+#define ATMEL_US_CHRL_8 (3 << 6)
-+#define ATMEL_US_SYNC (1 << 8) /* Synchronous Mode Select */
-+#define ATMEL_US_PAR (7 << 9) /* Parity Type */
-+#define ATMEL_US_PAR_EVEN (0 << 9)
-+#define ATMEL_US_PAR_ODD (1 << 9)
-+#define ATMEL_US_PAR_SPACE (2 << 9)
-+#define ATMEL_US_PAR_MARK (3 << 9)
-+#define ATMEL_US_PAR_NONE (4 << 9)
-+#define ATMEL_US_PAR_MULTI_DROP (6 << 9)
-+#define ATMEL_US_NBSTOP (3 << 12) /* Number of Stop Bits */
-+#define ATMEL_US_NBSTOP_1 (0 << 12)
-+#define ATMEL_US_NBSTOP_1_5 (1 << 12)
-+#define ATMEL_US_NBSTOP_2 (2 << 12)
-+#define ATMEL_US_CHMODE (3 << 14) /* Channel Mode */
-+#define ATMEL_US_CHMODE_NORMAL (0 << 14)
-+#define ATMEL_US_CHMODE_ECHO (1 << 14)
-+#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14)
-+#define ATMEL_US_CHMODE_REM_LOOP (3 << 14)
-+#define ATMEL_US_MSBF (1 << 16) /* Bit Order */
-+#define ATMEL_US_MODE9 (1 << 17) /* 9-bit Character Length */
-+#define ATMEL_US_CLKO (1 << 18) /* Clock Output Select */
-+#define ATMEL_US_OVER (1 << 19) /* Oversampling Mode */
-+#define ATMEL_US_INACK (1 << 20) /* Inhibit Non Acknowledge */
-+#define ATMEL_US_DSNACK (1 << 21) /* Disable Successive NACK */
-+#define ATMEL_US_MAX_ITER (7 << 24) /* Max Iterations */
-+#define ATMEL_US_FILTER (1 << 28) /* Infrared Receive Line Filter */
-+
-+#define ATMEL_US_IER 0x08 /* Interrupt Enable Register */
-+#define ATMEL_US_RXRDY (1 << 0) /* Receiver Ready */
-+#define ATMEL_US_TXRDY (1 << 1) /* Transmitter Ready */
-+#define ATMEL_US_RXBRK (1 << 2) /* Break Received / End of Break */
-+#define ATMEL_US_ENDRX (1 << 3) /* End of Receiver Transfer */
-+#define ATMEL_US_ENDTX (1 << 4) /* End of Transmitter Transfer */
-+#define ATMEL_US_OVRE (1 << 5) /* Overrun Error */
-+#define ATMEL_US_FRAME (1 << 6) /* Framing Error */
-+#define ATMEL_US_PARE (1 << 7) /* Parity Error */
-+#define ATMEL_US_TIMEOUT (1 << 8) /* Receiver Time-out */
-+#define ATMEL_US_TXEMPTY (1 << 9) /* Transmitter Empty */
-+#define ATMEL_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */
-+#define ATMEL_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
-+#define ATMEL_US_RXBUFF (1 << 12) /* Reception Buffer Full */
-+#define ATMEL_US_NACK (1 << 13) /* Non Acknowledge */
-+#define ATMEL_US_RIIC (1 << 16) /* Ring Indicator Input Change [AT91RM9200 only] */
-+#define ATMEL_US_DSRIC (1 << 17) /* Data Set Ready Input Change [AT91RM9200 only] */
-+#define ATMEL_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change [AT91RM9200 only] */
-+#define ATMEL_US_CTSIC (1 << 19) /* Clear to Send Input Change */
-+#define ATMEL_US_RI (1 << 20) /* RI */
-+#define ATMEL_US_DSR (1 << 21) /* DSR */
-+#define ATMEL_US_DCD (1 << 22) /* DCD */
-+#define ATMEL_US_CTS (1 << 23) /* CTS */
-+
-+#define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */
-+#define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */
-+#define ATMEL_US_CSR 0x14 /* Channel Status Register */
-+#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
-+#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
-+#define ATMEL_US_SYNH (1 << 15) /* Transmit/Receive Sync [AT91SAM9261 only] */
-+
-+#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
-+#define ATMEL_US_CD (0xffff << 0) /* Clock Divider */
-+
-+#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register */
-+#define ATMEL_US_TO (0xffff << 0) /* Time-out Value */
-+
-+#define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */
-+#define ATMEL_US_TG (0xff << 0) /* Timeguard Value */
-+
-+#define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */
-+#define ATMEL_US_NER 0x44 /* Number of Errors Register */
-+#define ATMEL_US_IF 0x4c /* IrDA Filter Register */
++#include <asm-generic/xor.h>
+
+#endif
--- /dev/null
+#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
+
+#endif
+--- a/include/linux/fs.h
++++ b/include/linux/fs.h
+@@ -1692,6 +1692,8 @@
+ extern int invalidate_inode_pages2(struct address_space *mapping);
+ extern int invalidate_inode_pages2_range(struct address_space *mapping,
+ pgoff_t start, pgoff_t end);
++extern void generic_sync_sb_inodes(struct super_block *sb,
++ struct writeback_control *wbc);
+ extern int write_inode_now(struct inode *, int);
+ extern int filemap_fdatawrite(struct address_space *);
+ extern int filemap_flush(struct address_space *);
+--- a/include/linux/serial_core.h
++++ b/include/linux/serial_core.h
+@@ -188,6 +188,7 @@
+ void (*break_ctl)(struct uart_port *, int ctl);
+ int (*startup)(struct uart_port *);
+ void (*shutdown)(struct uart_port *);
++ void (*flush_buffer)(struct uart_port *);
+ void (*set_termios)(struct uart_port *, struct ktermios *new,
+ struct ktermios *old);
+ void (*pm)(struct uart_port *, unsigned int state,
--- /dev/null
+++ b/include/linux/usb/atmel_usba_udc.h
@@ -0,0 +1,22 @@
+};
+
+#endif /* __LINUX_USB_USBA_H */
---- a/include/video/atmel_lcdc.h
-+++ b/include/video/atmel_lcdc.h
-@@ -22,7 +22,7 @@
- #ifndef __ATMEL_LCDC_H__
- #define __ATMEL_LCDC_H__
-
-- /* LCD Controller info data structure */
-+ /* LCD Controller info data structure, stored in device platform_data */
- struct atmel_lcdfb_info {
- spinlock_t lock;
- struct fb_info *info;
-@@ -33,7 +33,14 @@
- struct platform_device *pdev;
- struct clk *bus_clk;
- struct clk *lcdc_clk;
-- unsigned int default_bpp;
-+
-+#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
-+ struct backlight_device *backlight;
-+ u8 bl_power;
-+#endif
-+ bool lcdcon_is_backlight;
-+
-+ u8 default_bpp;
- unsigned int default_lcdcon2;
- unsigned int default_dmacon;
- void (*atmel_lcdfb_power_control)(int on);
-@@ -115,20 +122,20 @@
- #define ATMEL_LCDC_MEMOR_LITTLE (1 << 31)
-
- #define ATMEL_LCDC_TIM1 0x0808
--#define ATMEL_LCDC_VFP (0xff << 0)
-+#define ATMEL_LCDC_VFP (0xffU << 0)
- #define ATMEL_LCDC_VBP_OFFSET 8
--#define ATMEL_LCDC_VBP (0xff << ATMEL_LCDC_VBP_OFFSET)
-+#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET)
- #define ATMEL_LCDC_VPW_OFFSET 16
--#define ATMEL_LCDC_VPW (0x3f << ATMEL_LCDC_VPW_OFFSET)
-+#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET)
- #define ATMEL_LCDC_VHDLY_OFFSET 24
--#define ATMEL_LCDC_VHDLY (0xf << ATMEL_LCDC_VHDLY_OFFSET)
-+#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET)
-
- #define ATMEL_LCDC_TIM2 0x080c
--#define ATMEL_LCDC_HBP (0xff << 0)
-+#define ATMEL_LCDC_HBP (0xffU << 0)
- #define ATMEL_LCDC_HPW_OFFSET 8
--#define ATMEL_LCDC_HPW (0x3f << ATMEL_LCDC_HPW_OFFSET)
-+#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET)
- #define ATMEL_LCDC_HFP_OFFSET 21
--#define ATMEL_LCDC_HFP (0x7ff << ATMEL_LCDC_HFP_OFFSET)
-+#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET)
-
- #define ATMEL_LCDC_LCDFRMCFG 0x0810
- #define ATMEL_LCDC_LINEVAL (0x7ff << 0)
---- a/init/do_mounts.c
-+++ b/init/do_mounts.c
-@@ -219,8 +219,14 @@
-
- static int __init rootwait_setup(char *str)
- {
-- if (*str)
-+ if (*str && *str != '=')
- return 0;
-+
-+ if (*str)
-+ printk(KERN_WARNING
-+ "WARNING: \"rootwait=1\" is deprecated, "
-+ "use \"rootwait\" instead.\n");
+--- a/mm/Kconfig
++++ b/mm/Kconfig
+@@ -187,7 +187,7 @@
+ config NR_QUICK
+ int
+ depends on QUICKLIST
+- default "2" if SUPERH
++ default "2" if SUPERH || AVR32
+ default "1"
+
+ config VIRT_TO_BUS
+--- a/sound/Kconfig
++++ b/sound/Kconfig
+@@ -63,6 +63,8 @@
+
+ source "sound/arm/Kconfig"
+
++source "sound/avr32/Kconfig"
+
- root_wait = 1;
- return 1;
- }
---- a/kernel/ptrace.c
-+++ b/kernel/ptrace.c
-@@ -470,6 +470,8 @@
- lock_kernel();
- if (request == PTRACE_TRACEME) {
- ret = ptrace_traceme();
-+ if (!ret)
-+ arch_ptrace_attach(current);
- goto out;
- }
+ if SPI
+ source "sound/spi/Kconfig"
+ endif
+--- a/sound/Makefile
++++ b/sound/Makefile
+@@ -6,7 +6,7 @@
+ obj-$(CONFIG_SOUND_PRIME) += oss/
+ obj-$(CONFIG_DMASOUND) += oss/
+ obj-$(CONFIG_SND) += core/ i2c/ drivers/ isa/ pci/ ppc/ arm/ sh/ synth/ usb/ \
+- sparc/ spi/ parisc/ pcmcia/ mips/ soc/
++ sparc/ spi/ parisc/ pcmcia/ mips/ soc/ avr32/
+ obj-$(CONFIG_SND_AOA) += aoa/
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -671,6 +671,12 @@
- W: http://www.at91.com/
- S: Maintained
-
-+ATMEL AT91 / AT32 SERIAL DRIVER
-+P: Haavard Skinnemoen
-+M: hskinnemoen@atmel.com
-+L: linux-kernel@vger.kernel.org
-+S: Supported
-+
- ATMEL LCDFB DRIVER
- P: Nicolas Ferre
- M: nicolas.ferre@atmel.com
+ # This one must be compilable even if sound is configured out
+--- /dev/null
++++ b/sound/avr32/Kconfig
+@@ -0,0 +1,11 @@
++menu "AVR32 devices"
++ depends on SND != n && AVR32
++
++config SND_ATMEL_AC97
++ tristate "Atmel AC97 Controller Driver"
++ select SND_PCM
++ select SND_AC97_CODEC
++ help
++ ALSA sound driver for the Atmel AC97 controller.
++
++endmenu
+--- /dev/null
++++ b/sound/avr32/Makefile
+@@ -0,0 +1,3 @@
++snd-atmel-ac97-objs := ac97c.o
++
++obj-$(CONFIG_SND_ATMEL_AC97) += snd-atmel-ac97.o
--- /dev/null
+++ b/sound/avr32/ac97c.c
-@@ -0,0 +1,914 @@
+@@ -0,0 +1,951 @@
+/*
+ * Driver for the Atmel AC97 controller
+ *
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
++#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/io.h>
+
-+#include <sound/driver.h>
+#include <sound/core.h>
+#include <sound/initval.h>
+#include <sound/pcm.h>
+#include <sound/ac97_codec.h>
+#include <sound/memalloc.h>
+
++#include <asm/arch/board.h>
+#include <asm/dma-controller.h>
+
+#include "ac97c.h"
+ struct dma_request_cyclic req_rx;
+ unsigned short rx_periph_id;
+ unsigned short tx_periph_id;
++ unsigned short controller;
+};
+
+struct atmel_ac97 {
+ struct snd_ac97_bus *ac97_bus;
+ int opened;
+ int period;
++ int reset_pin;
+ u64 cur_format;
+ unsigned int cur_rate;
+ struct clk *mck;
+ ac97c_writel(chip, COTHR, word);
+ goto read_reg;
+ }
-+ mdelay(10);
++ udelay(10);
+ } while (--timeout);
+
+ if (!--write)
+ unsigned short val = ac97c_readl(chip, CORHR);
+ return val;
+ }
-+ mdelay(10);
++ udelay(10);
+ } while (--timeout);
+
+ if (!--write)
+
+static void snd_atmel_ac97_reset(struct atmel_ac97 *chip)
+{
++ /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
++ if (chip->reset_pin >= 0) {
++ gpio_set_value(chip->reset_pin, 0);
++ /* AC97 v2.2 specifications says minimum 1 us. */
++ udelay(5);
++ gpio_set_value(chip->reset_pin, 1);
++ }
++
+ ac97c_writel(chip, MR, AC97C_MR_WRST);
+ mdelay(1);
+ ac97c_writel(chip, MR, AC97C_MR_ENA);
+ .read = snd_atmel_ac97_read,
+ };
+ struct atmel_ac97 *chip = get_chip(card);
++ struct ac97c_platform_data *pdata;
+ struct resource *regs;
+ struct clk *mck;
+ int err;
+ if (!regs)
+ return -ENXIO;
+
++ pdata = pdev->dev.platform_data;
++ if (!pdata)
++ return -ENXIO;
++
++ chip->reset_pin = pdata->reset_pin;
++
++ /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
++ if (chip->reset_pin >= 0) {
++ if (gpio_request(chip->reset_pin, chip->card->shortname)) {
++ dev_dbg(&pdev->dev, "ac97: reset pin not available\n");
++ chip->reset_pin = -1;
++ } else {
++ gpio_direction_output(chip->reset_pin, 1);
++ }
++ }
++
++ chip->dma.rx_periph_id = pdata->dma_rx_periph_id;
++ chip->dma.tx_periph_id = pdata->dma_tx_periph_id;
++ chip->dma.controller = pdata->dma_controller_id;
++
+ mck = clk_get(&pdev->dev, "pclk");
+ if (IS_ERR(mck))
+ return PTR_ERR(mck);
+ THIS_MODULE, sizeof(struct atmel_ac97));
+ if (!card)
+ goto out;
++
+ chip = get_chip(card);
++ chip->reset_pin = -1;
+
+ err = snd_atmel_ac97_create(card, pdev);
+ if (err)
+ if (err)
+ goto out_free_card;
+
-+ /* TODO: Get this information from the platform device */
-+ chip->dma.req_tx.req.dmac = find_dma_controller(0);
++ chip->dma.req_tx.req.dmac = find_dma_controller(chip->dma.controller);
+ if (!chip->dma.req_tx.req.dmac) {
+ dev_dbg(&chip->pdev->dev, "DMA controller for TX missing\n");
+ err = -ENODEV;
+ goto out_free_card;
+ }
-+ chip->dma.req_rx.req.dmac = find_dma_controller(0);
++ chip->dma.req_rx.req.dmac = find_dma_controller(chip->dma.controller);
+ if (!chip->dma.req_rx.req.dmac) {
+ dev_dbg(&chip->pdev->dev, "DMA controller for RX missing\n");
+ err = -ENODEV;
+ goto out_free_card;
+ }
+
-+ chip->dma.rx_periph_id = 3;
-+ chip->dma.tx_periph_id = 4;
-+
+ ch = dma_alloc_channel(chip->dma.req_tx.req.dmac);
+ if (ch < 0) {
+ dev_dbg(&chip->pdev->dev,
+ return 0;
+
+out_free_card:
++ /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
++ if (chip->reset_pin >= 0)
++ gpio_free(chip->reset_pin);
+ snd_card_free(card);
+out:
+ return err;
+
+static int snd_atmel_ac97_resume(struct platform_device *pdev)
+{
-+ struct snd_card *card = dev_get_drvdata(pdev);
++ struct snd_card *card = platform_get_drvdata(pdev);
+ struct atmel_ac97 *chip = card->private_data;
+
+ clk_enable(chip->mck);
+static int __devexit snd_atmel_ac97_remove(struct platform_device *pdev)
+{
+ struct snd_card *card = platform_get_drvdata(pdev);
++ struct atmel_ac97 *chip = get_chip(card);
+
++ /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
++ if (chip->reset_pin >= 0)
++ gpio_free(chip->reset_pin);
+ snd_card_free(card);
+ platform_set_drvdata(pdev, NULL);
+ return 0;
+#define AC97C_CHANNEL_B 0x2
+
+#endif /* __SOUND_AVR32_AC97C_H */
---- /dev/null
-+++ b/sound/avr32/Kconfig
-@@ -0,0 +1,11 @@
-+menu "AVR32 devices"
-+ depends on SND != n && AVR32
-+
-+config SND_ATMEL_AC97
-+ tristate "Atmel AC97 Controller Driver"
-+ select SND_PCM
-+ select SND_AC97_CODEC
-+ help
-+ ALSA sound driver for the Atmel AC97 controller.
-+
-+endmenu
---- /dev/null
-+++ b/sound/avr32/Makefile
-@@ -0,0 +1,3 @@
-+snd-atmel-ac97-objs := ac97c.o
+--- a/sound/oss/Kconfig
++++ b/sound/oss/Kconfig
+@@ -654,3 +654,7 @@
+ int "DAC channel"
+ default "1"
+ depends on SOUND_SH_DAC_AUDIO
+
-+obj-$(CONFIG_SND_ATMEL_AC97) += snd-atmel-ac97.o
---- a/sound/Kconfig
-+++ b/sound/Kconfig
-@@ -63,6 +63,8 @@
-
- source "sound/arm/Kconfig"
++config SOUND_AT32_ABDAC
++ tristate "Atmel AT32 Audio Bitstream DAC (ABDAC) support"
++ depends on SOUND_PRIME && AVR32
+--- a/sound/oss/Makefile
++++ b/sound/oss/Makefile
+@@ -9,6 +9,7 @@
-+source "sound/avr32/Kconfig"
-+
- if SPI
- source "sound/spi/Kconfig"
- endif
---- a/sound/Makefile
-+++ b/sound/Makefile
-@@ -6,7 +6,7 @@
- obj-$(CONFIG_SOUND_PRIME) += oss/
- obj-$(CONFIG_DMASOUND) += oss/
- obj-$(CONFIG_SND) += core/ i2c/ drivers/ isa/ pci/ ppc/ arm/ sh/ synth/ usb/ \
-- sparc/ spi/ parisc/ pcmcia/ mips/ soc/
-+ sparc/ spi/ parisc/ pcmcia/ mips/ soc/ avr32/
- obj-$(CONFIG_SND_AOA) += aoa/
+ # Please leave it as is, cause the link order is significant !
- # This one must be compilable even if sound is configured out
++obj-$(CONFIG_SOUND_AT32_ABDAC) += at32_abdac.o
+ obj-$(CONFIG_SOUND_SH_DAC_AUDIO) += sh_dac_audio.o
+ obj-$(CONFIG_SOUND_HAL2) += hal2.o
+ obj-$(CONFIG_SOUND_AEDSP16) += aedsp16.o
--- /dev/null
+++ b/sound/oss/at32_abdac.c
@@ -0,0 +1,722 @@
+ __raw_writel((value), (port)->regs + DAC_##reg)
+
+#endif /* __SOUND_OSS_AT32_ABDAC_H__ */
---- a/sound/oss/Kconfig
-+++ b/sound/oss/Kconfig
-@@ -654,3 +654,7 @@
- int "DAC channel"
- default "1"
- depends on SOUND_SH_DAC_AUDIO
-+
-+config SOUND_AT32_ABDAC
-+ tristate "Atmel AT32 Audio Bitstream DAC (ABDAC) support"
-+ depends on SOUND_PRIME && AVR32
---- a/sound/oss/Makefile
-+++ b/sound/oss/Makefile
-@@ -10,6 +10,7 @@
-
- # Please leave it as is, cause the link order is significant !
-
-+obj-$(CONFIG_SOUND_AT32_ABDAC) += at32_abdac.o
- obj-$(CONFIG_SOUND_SH_DAC_AUDIO) += sh_dac_audio.o
- obj-$(CONFIG_SOUND_HAL2) += hal2.o
- obj-$(CONFIG_SOUND_AEDSP16) += aedsp16.o
--- a/sound/spi/at73c213.c
+++ b/sound/spi/at73c213.c
-@@ -744,7 +744,7 @@
+@@ -737,7 +737,7 @@
/*
* Device functions
*/
{
/*
* Continuous clock output.
-@@ -774,7 +774,7 @@
+@@ -767,7 +767,7 @@
return 0;
}
{
int retval;
unsigned char dac_ctrl = 0;
-@@ -939,7 +939,7 @@
+@@ -933,7 +933,7 @@
return retval;
}
projects / openwrt.git / blobdiff